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105 lines
3.6 KiB
105 lines
3.6 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Device Tree Source for AM642 SoC Family |
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* |
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ |
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*/ |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/pinctrl/k3.h> |
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#include <dt-bindings/soc/ti,sci_pm_domain.h> |
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/ { |
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model = "Texas Instruments K3 AM642 SoC"; |
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compatible = "ti,am642"; |
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interrupt-parent = <&gic500>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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aliases { |
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serial0 = &mcu_uart0; |
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serial1 = &mcu_uart1; |
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serial2 = &main_uart0; |
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serial3 = &main_uart1; |
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serial4 = &main_uart2; |
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serial5 = &main_uart3; |
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serial6 = &main_uart4; |
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serial7 = &main_uart5; |
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serial8 = &main_uart6; |
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ethernet0 = &cpsw_port1; |
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ethernet1 = &cpsw_port2; |
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}; |
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chosen { }; |
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firmware { |
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optee { |
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compatible = "linaro,optee-tz"; |
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method = "smc"; |
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}; |
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psci: psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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}; |
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a53_timer0: timer-cl0-cpu0 { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ |
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}; |
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pmu: pmu { |
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compatible = "arm,cortex-a53-pmu"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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cbass_main: bus@f4000 { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ |
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ |
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<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ |
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<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ |
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<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ |
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<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ |
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<0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ |
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<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ |
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<0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ |
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<0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */ |
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<0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */ |
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<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ |
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<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ |
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<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ |
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ |
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<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ |
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<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ |
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<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ |
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<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ |
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<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ |
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */ |
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<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */ |
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<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ |
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ |
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/* MCU Domain Range */ |
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<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; |
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cbass_mcu: bus@4000000 { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ |
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}; |
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}; |
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}; |
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/* Now include the peripherals for each bus segments */ |
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#include "k3-am64-main.dtsi" |
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#include "k3-am64-mcu.dtsi"
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