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173 lines
3.7 KiB
173 lines
3.7 KiB
// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
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/* |
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* Copyright (C) 2018 Synaptics Incorporated |
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* |
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* Author: Jisheng Zhang <[email protected]> |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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compatible = "syna,as370"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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reg = <0x0>; |
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enable-method = "psci"; |
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next-level-cache = <&l2>; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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}; |
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cpu1: cpu@1 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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reg = <0x1>; |
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enable-method = "psci"; |
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next-level-cache = <&l2>; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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}; |
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cpu2: cpu@2 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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reg = <0x2>; |
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enable-method = "psci"; |
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next-level-cache = <&l2>; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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}; |
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cpu3: cpu@3 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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reg = <0x3>; |
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enable-method = "psci"; |
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next-level-cache = <&l2>; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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}; |
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l2: cache { |
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compatible = "cache"; |
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}; |
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idle-states { |
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entry-method = "psci"; |
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CPU_SLEEP_0: cpu-sleep-0 { |
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compatible = "arm,idle-state"; |
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local-timer-stop; |
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arm,psci-suspend-param = <0x0010000>; |
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entry-latency-us = <75>; |
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exit-latency-us = <155>; |
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min-residency-us = <1000>; |
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}; |
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}; |
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}; |
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osc: osc { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <25000000>; |
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}; |
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pmu { |
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compatible = "arm,cortex-a53-pmu"; |
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-affinity = <&cpu0>, |
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<&cpu1>, |
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<&cpu2>, |
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<&cpu3>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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soc@f7000000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0 0xf7000000 0x1000000>; |
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gic: interrupt-controller@901000 { |
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compatible = "arm,gic-400"; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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reg = <0x901000 0x1000>, |
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<0x902000 0x2000>, |
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<0x904000 0x2000>, |
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<0x906000 0x2000>; |
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
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}; |
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apb@e80000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0xe80000 0x10000>; |
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uart0: serial@c00 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0xc00 0x100>; |
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&osc>; |
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reg-shift = <2>; |
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status = "disabled"; |
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}; |
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gpio0: gpio@1800 { |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x1800 0x400>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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porta: gpio-port@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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ngpios = <32>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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gpio1: gpio@2000 { |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x2000 0x400>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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portb: gpio-port@1 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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ngpios = <32>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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}; |
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}; |
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};
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