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716 lines
14 KiB
716 lines
14 KiB
/* |
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* Spreadtrum SC9860 SoC |
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* |
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* Copyright (C) 2016, Spreadtrum Communications Inc. |
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* |
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/input/input.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#include "whale2.dtsi" |
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/ { |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&CPU0>; |
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}; |
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core1 { |
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cpu = <&CPU1>; |
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}; |
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core2 { |
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cpu = <&CPU2>; |
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}; |
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core3 { |
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cpu = <&CPU3>; |
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}; |
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}; |
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cluster1 { |
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core0 { |
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cpu = <&CPU4>; |
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}; |
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core1 { |
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cpu = <&CPU5>; |
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}; |
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core2 { |
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cpu = <&CPU6>; |
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}; |
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core3 { |
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cpu = <&CPU7>; |
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}; |
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}; |
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}; |
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CPU0: cpu@530000 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x530000>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>; |
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}; |
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CPU1: cpu@530001 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x530001>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>; |
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}; |
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CPU2: cpu@530002 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x530002>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>; |
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}; |
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CPU3: cpu@530003 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x530003>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>; |
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}; |
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CPU4: cpu@530100 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x530100>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>; |
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}; |
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CPU5: cpu@530101 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x530101>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>; |
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}; |
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CPU6: cpu@530102 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x530102>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>; |
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}; |
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CPU7: cpu@530103 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x530103>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>; |
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}; |
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}; |
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idle-states{ |
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entry-method = "psci"; |
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CORE_PD: core_pd { |
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compatible = "arm,idle-state"; |
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entry-latency-us = <1000>; |
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exit-latency-us = <700>; |
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min-residency-us = <2500>; |
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local-timer-stop; |
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arm,psci-suspend-param = <0x00010002>; |
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}; |
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CLUSTER_PD: cluster_pd { |
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compatible = "arm,idle-state"; |
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entry-latency-us = <1000>; |
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exit-latency-us = <1000>; |
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min-residency-us = <3000>; |
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local-timer-stop; |
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arm,psci-suspend-param = <0x01010003>; |
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}; |
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}; |
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gic: interrupt-controller@12001000 { |
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compatible = "arm,gic-400"; |
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reg = <0 0x12001000 0 0x1000>, |
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<0 0x12002000 0 0x2000>, |
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<0 0x12004000 0 0x2000>, |
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<0 0x12006000 0 0x2000>; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
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| IRQ_TYPE_LEVEL_HIGH)>; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
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| IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
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| IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
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| IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
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| IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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pmu { |
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compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; |
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-affinity = <&CPU0>, |
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<&CPU1>, |
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<&CPU2>, |
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<&CPU3>, |
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<&CPU4>, |
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<&CPU5>, |
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<&CPU6>, |
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<&CPU7>; |
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}; |
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soc { |
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pmu_gate: pmu-gate { |
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compatible = "sprd,sc9860-pmu-gate"; |
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sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ |
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clocks = <&ext_26m>; |
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#clock-cells = <1>; |
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}; |
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pll: pll { |
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compatible = "sprd,sc9860-pll"; |
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sprd,syscon = <&ana_regs>; /* 0x40400000 */ |
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clocks = <&pmu_gate 0>; |
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#clock-cells = <1>; |
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}; |
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ap_clk: clock-controller@20000000 { |
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compatible = "sprd,sc9860-ap-clk"; |
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reg = <0 0x20000000 0 0x400>; |
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clocks = <&ext_26m>, <&pll 0>, |
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<&pmu_gate 0>; |
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#clock-cells = <1>; |
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}; |
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aon_prediv: aon-prediv { |
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compatible = "sprd,sc9860-aon-prediv"; |
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reg = <0 0x402d0000 0 0x400>; |
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clocks = <&ext_26m>, <&pll 0>, |
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<&pmu_gate 0>; |
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#clock-cells = <1>; |
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}; |
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apahb_gate: apahb-gate { |
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compatible = "sprd,sc9860-apahb-gate"; |
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sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ |
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clocks = <&aon_prediv 0>; |
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#clock-cells = <1>; |
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}; |
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aon_gate: aon-gate { |
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compatible = "sprd,sc9860-aon-gate"; |
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sprd,syscon = <&aon_regs>; /* 0x402e0000 */ |
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clocks = <&aon_prediv 0>; |
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#clock-cells = <1>; |
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}; |
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aonsecure_clk: clock-controller@40880000 { |
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compatible = "sprd,sc9860-aonsecure-clk"; |
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reg = <0 0x40880000 0 0x400>; |
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clocks = <&ext_26m>, <&pll 0>; |
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#clock-cells = <1>; |
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}; |
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agcp_gate: agcp-gate { |
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compatible = "sprd,sc9860-agcp-gate"; |
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sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ |
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clocks = <&aon_prediv 0>; |
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#clock-cells = <1>; |
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}; |
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gpu_clk: clock-controller@60200000 { |
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compatible = "sprd,sc9860-gpu-clk"; |
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reg = <0 0x60200000 0 0x400>; |
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clocks = <&pll 0>; |
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#clock-cells = <1>; |
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}; |
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vsp_clk: clock-controller@61000000 { |
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compatible = "sprd,sc9860-vsp-clk"; |
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reg = <0 0x61000000 0 0x400>; |
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clocks = <&ext_26m>, <&pll 0>; |
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#clock-cells = <1>; |
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}; |
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vsp_gate: vsp-gate { |
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compatible = "sprd,sc9860-vsp-gate"; |
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sprd,syscon = <&vsp_regs>; /* 0x61100000 */ |
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clocks = <&vsp_clk 0>; |
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#clock-cells = <1>; |
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}; |
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cam_clk: clock-controller@62000000 { |
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compatible = "sprd,sc9860-cam-clk"; |
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reg = <0 0x62000000 0 0x4000>; |
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clocks = <&ext_26m>, <&pll 0>; |
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#clock-cells = <1>; |
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}; |
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cam_gate: cam-gate { |
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compatible = "sprd,sc9860-cam-gate"; |
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sprd,syscon = <&cam_regs>; /* 0x62100000 */ |
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clocks = <&cam_clk 0>; |
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#clock-cells = <1>; |
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}; |
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disp_clk: clock-controller@63000000 { |
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compatible = "sprd,sc9860-disp-clk"; |
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reg = <0 0x63000000 0 0x400>; |
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clocks = <&ext_26m>, <&pll 0>; |
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#clock-cells = <1>; |
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}; |
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disp_gate: disp-gate { |
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compatible = "sprd,sc9860-disp-gate"; |
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sprd,syscon = <&disp_regs>; /* 0x63100000 */ |
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clocks = <&disp_clk 0>; |
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#clock-cells = <1>; |
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}; |
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apapb_gate: apapb-gate { |
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compatible = "sprd,sc9860-apapb-gate"; |
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sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ |
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clocks = <&ap_clk 0>; |
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#clock-cells = <1>; |
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}; |
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funnel@10001000 { /* SoC Funnel */ |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x10001000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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soc_funnel_out_port: endpoint { |
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remote-endpoint = <&etb_in>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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soc_funnel_in_port0: endpoint { |
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remote-endpoint = |
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<&main_funnel_out_port>; |
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}; |
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}; |
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port@4 { |
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reg = <4>; |
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soc_funnel_in_port1: endpoint { |
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remote-endpoint = |
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<&stm_out_port>; |
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}; |
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}; |
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}; |
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}; |
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etb@10003000 { |
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compatible = "arm,coresight-tmc", "arm,primecell"; |
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reg = <0 0x10003000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etb_in: endpoint { |
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remote-endpoint = |
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<&soc_funnel_out_port>; |
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}; |
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}; |
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}; |
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}; |
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stm@10006000 { |
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compatible = "arm,coresight-stm", "arm,primecell"; |
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reg = <0 0x10006000 0 0x1000>, |
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<0 0x01000000 0 0x180000>; |
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reg-names = "stm-base", "stm-stimulus-base"; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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stm_out_port: endpoint { |
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remote-endpoint = |
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<&soc_funnel_in_port1>; |
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}; |
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}; |
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}; |
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}; |
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funnel@11001000 { /* Cluster0 Funnel */ |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x11001000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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cluster0_funnel_out_port: endpoint { |
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remote-endpoint = |
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<&cluster0_etf_in>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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cluster0_funnel_in_port0: endpoint { |
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remote-endpoint = <&etm0_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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cluster0_funnel_in_port1: endpoint { |
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remote-endpoint = <&etm1_out>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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cluster0_funnel_in_port2: endpoint { |
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remote-endpoint = <&etm2_out>; |
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}; |
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}; |
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port@4 { |
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reg = <4>; |
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cluster0_funnel_in_port3: endpoint { |
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remote-endpoint = <&etm3_out>; |
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}; |
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}; |
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}; |
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}; |
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funnel@11002000 { /* Cluster1 Funnel */ |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x11002000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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cluster1_funnel_out_port: endpoint { |
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remote-endpoint = |
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<&cluster1_etf_in>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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cluster1_funnel_in_port0: endpoint { |
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remote-endpoint = <&etm4_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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cluster1_funnel_in_port1: endpoint { |
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remote-endpoint = <&etm5_out>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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cluster1_funnel_in_port2: endpoint { |
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remote-endpoint = <&etm6_out>; |
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}; |
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}; |
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port@3 { |
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reg = <3>; |
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cluster1_funnel_in_port3: endpoint { |
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remote-endpoint = <&etm7_out>; |
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}; |
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}; |
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}; |
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}; |
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etf@11003000 { /* ETF on Cluster0 */ |
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compatible = "arm,coresight-tmc", "arm,primecell"; |
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reg = <0 0x11003000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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cluster0_etf_out: endpoint { |
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remote-endpoint = |
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<&main_funnel_in_port0>; |
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}; |
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}; |
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}; |
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in-ports { |
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port { |
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cluster0_etf_in: endpoint { |
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remote-endpoint = |
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<&cluster0_funnel_out_port>; |
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}; |
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}; |
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}; |
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}; |
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etf@11004000 { /* ETF on Cluster1 */ |
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compatible = "arm,coresight-tmc", "arm,primecell"; |
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reg = <0 0x11004000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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cluster1_etf_out: endpoint { |
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remote-endpoint = |
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<&main_funnel_in_port1>; |
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}; |
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}; |
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}; |
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in-ports { |
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port { |
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cluster1_etf_in: endpoint { |
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remote-endpoint = |
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<&cluster1_funnel_out_port>; |
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}; |
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}; |
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}; |
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}; |
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funnel@11005000 { /* Main Funnel */ |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x11005000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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main_funnel_out_port: endpoint { |
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remote-endpoint = |
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<&soc_funnel_in_port0>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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main_funnel_in_port0: endpoint { |
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remote-endpoint = |
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<&cluster0_etf_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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main_funnel_in_port1: endpoint { |
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remote-endpoint = |
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<&cluster1_etf_out>; |
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}; |
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}; |
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}; |
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}; |
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etm@11440000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x11440000 0 0x1000>; |
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cpu = <&CPU0>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm0_out: endpoint { |
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remote-endpoint = |
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<&cluster0_funnel_in_port0>; |
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}; |
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}; |
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}; |
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}; |
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etm@11540000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x11540000 0 0x1000>; |
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cpu = <&CPU1>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm1_out: endpoint { |
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remote-endpoint = |
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<&cluster0_funnel_in_port1>; |
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}; |
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}; |
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}; |
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}; |
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etm@11640000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x11640000 0 0x1000>; |
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cpu = <&CPU2>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm2_out: endpoint { |
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remote-endpoint = |
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<&cluster0_funnel_in_port2>; |
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}; |
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}; |
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}; |
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}; |
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etm@11740000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x11740000 0 0x1000>; |
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cpu = <&CPU3>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm3_out: endpoint { |
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remote-endpoint = |
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<&cluster0_funnel_in_port3>; |
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}; |
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}; |
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}; |
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}; |
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etm@11840000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x11840000 0 0x1000>; |
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cpu = <&CPU4>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm4_out: endpoint { |
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remote-endpoint = |
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<&cluster1_funnel_in_port0>; |
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}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@11940000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x11940000 0 0x1000>; |
|
cpu = <&CPU5>; |
|
clocks = <&ext_26m>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
etm5_out: endpoint { |
|
remote-endpoint = |
|
<&cluster1_funnel_in_port1>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@11a40000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x11a40000 0 0x1000>; |
|
cpu = <&CPU6>; |
|
clocks = <&ext_26m>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
etm6_out: endpoint { |
|
remote-endpoint = |
|
<&cluster1_funnel_in_port2>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@11b40000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x11b40000 0 0x1000>; |
|
cpu = <&CPU7>; |
|
clocks = <&ext_26m>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
etm7_out: endpoint { |
|
remote-endpoint = |
|
<&cluster1_funnel_in_port3>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
gpio-keys { |
|
compatible = "gpio-keys"; |
|
|
|
key-volumedown { |
|
label = "Volume Down Key"; |
|
linux,code = <KEY_VOLUMEDOWN>; |
|
gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; |
|
debounce-interval = <2>; |
|
wakeup-source; |
|
}; |
|
|
|
key-volumeup { |
|
label = "Volume Up Key"; |
|
linux,code = <KEY_VOLUMEUP>; |
|
gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; |
|
debounce-interval = <2>; |
|
wakeup-source; |
|
}; |
|
|
|
key-power { |
|
label = "Power Key"; |
|
linux,code = <KEY_POWER>; |
|
gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; |
|
debounce-interval = <2>; |
|
wakeup-source; |
|
}; |
|
}; |
|
}; |
|
};
|
|
|