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316 lines
8.7 KiB
316 lines
8.7 KiB
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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/* |
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* Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts |
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* |
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* Copyright (C) 2021 Renesas Electronics Corp. |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/clock/r9a07g044-cpg.h> |
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/ { |
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compatible = "renesas,r9a07g044"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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/* External CAN clock - to be overridden by boards that provide it */ |
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can_clk: can { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <0>; |
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}; |
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/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ |
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extal_clk: extal { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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/* This value must be overridden by the board */ |
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clock-frequency = <0>; |
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}; |
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psci { |
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compatible = "arm,psci-1.0", "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&cpu0>; |
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}; |
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core1 { |
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cpu = <&cpu1>; |
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}; |
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}; |
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}; |
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cpu0: cpu@0 { |
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compatible = "arm,cortex-a55"; |
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reg = <0>; |
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device_type = "cpu"; |
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next-level-cache = <&L3_CA55>; |
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enable-method = "psci"; |
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}; |
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cpu1: cpu@100 { |
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compatible = "arm,cortex-a55"; |
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reg = <0x100>; |
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device_type = "cpu"; |
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next-level-cache = <&L3_CA55>; |
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enable-method = "psci"; |
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}; |
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L3_CA55: cache-controller-0 { |
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compatible = "cache"; |
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cache-unified; |
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cache-size = <0x40000>; |
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}; |
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}; |
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soc: soc { |
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compatible = "simple-bus"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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scif0: serial@1004b800 { |
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compatible = "renesas,scif-r9a07g044"; |
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reg = <0 0x1004b800 0 0x400>; |
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interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "eri", "rxi", "txi", |
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"bri", "dri", "tei"; |
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clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; |
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clock-names = "fck"; |
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power-domains = <&cpg>; |
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resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; |
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status = "disabled"; |
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}; |
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canfd: can@10050000 { |
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compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; |
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reg = <0 0x10050000 0 0x8000>; |
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interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "g_err", "g_recc", |
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"ch0_err", "ch0_rec", "ch0_trx", |
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"ch1_err", "ch1_rec", "ch1_trx"; |
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clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>, |
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<&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>, |
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<&can_clk>; |
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clock-names = "fck", "canfd", "can_clk"; |
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assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>; |
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assigned-clock-rates = <50000000>; |
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resets = <&cpg R9A07G044_CANFD_RSTP_N>, |
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<&cpg R9A07G044_CANFD_RSTC_N>; |
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reset-names = "rstp_n", "rstc_n"; |
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power-domains = <&cpg>; |
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status = "disabled"; |
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channel0 { |
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status = "disabled"; |
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}; |
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channel1 { |
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status = "disabled"; |
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}; |
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}; |
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i2c0: i2c@10058000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; |
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reg = <0 0x10058000 0 0x400>; |
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interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "tei", "ri", "ti", "spi", "sti", |
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"naki", "ali", "tmoi"; |
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clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; |
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clock-frequency = <100000>; |
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resets = <&cpg R9A07G044_I2C0_MRST>; |
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power-domains = <&cpg>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@10058400 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; |
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reg = <0 0x10058400 0 0x400>; |
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "tei", "ri", "ti", "spi", "sti", |
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"naki", "ali", "tmoi"; |
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clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; |
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clock-frequency = <100000>; |
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resets = <&cpg R9A07G044_I2C1_MRST>; |
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power-domains = <&cpg>; |
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status = "disabled"; |
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}; |
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i2c2: i2c@10058800 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; |
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reg = <0 0x10058800 0 0x400>; |
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interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "tei", "ri", "ti", "spi", "sti", |
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"naki", "ali", "tmoi"; |
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clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; |
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clock-frequency = <100000>; |
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resets = <&cpg R9A07G044_I2C2_MRST>; |
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power-domains = <&cpg>; |
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status = "disabled"; |
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}; |
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i2c3: i2c@10058c00 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; |
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reg = <0 0x10058c00 0 0x400>; |
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interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "tei", "ri", "ti", "spi", "sti", |
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"naki", "ali", "tmoi"; |
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clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; |
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clock-frequency = <100000>; |
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resets = <&cpg R9A07G044_I2C3_MRST>; |
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power-domains = <&cpg>; |
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status = "disabled"; |
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}; |
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adc: adc@10059000 { |
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compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; |
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reg = <0 0x10059000 0 0x400>; |
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interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; |
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clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, |
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<&cpg CPG_MOD R9A07G044_ADC_PCLK>; |
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clock-names = "adclk", "pclk"; |
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resets = <&cpg R9A07G044_ADC_PRESETN>, |
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<&cpg R9A07G044_ADC_ADRST_N>; |
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reset-names = "presetn", "adrst-n"; |
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power-domains = <&cpg>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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channel@0 { |
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reg = <0>; |
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}; |
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channel@1 { |
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reg = <1>; |
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}; |
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channel@2 { |
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reg = <2>; |
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}; |
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channel@3 { |
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reg = <3>; |
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}; |
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channel@4 { |
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reg = <4>; |
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}; |
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channel@5 { |
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reg = <5>; |
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}; |
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channel@6 { |
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reg = <6>; |
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}; |
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channel@7 { |
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reg = <7>; |
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}; |
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}; |
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cpg: clock-controller@11010000 { |
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compatible = "renesas,r9a07g044-cpg"; |
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reg = <0 0x11010000 0 0x10000>; |
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clocks = <&extal_clk>; |
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clock-names = "extal"; |
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#clock-cells = <2>; |
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#reset-cells = <1>; |
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#power-domain-cells = <0>; |
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}; |
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sysc: system-controller@11020000 { |
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compatible = "renesas,r9a07g044-sysc"; |
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reg = <0 0x11020000 0 0x10000>; |
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "lpm_int", "ca55stbydone_int", |
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"cm33stbyr_int", "ca55_deny"; |
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status = "disabled"; |
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}; |
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pinctrl: pin-controller@11030000 { |
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compatible = "renesas,r9a07g044-pinctrl"; |
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reg = <0 0x11030000 0 0x10000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pinctrl 0 0 392>; |
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clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; |
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power-domains = <&cpg>; |
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resets = <&cpg R9A07G044_GPIO_RSTN>, |
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<&cpg R9A07G044_GPIO_PORT_RESETN>, |
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<&cpg R9A07G044_GPIO_SPARE_RESETN>; |
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}; |
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gic: interrupt-controller@11900000 { |
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compatible = "arm,gic-v3"; |
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#interrupt-cells = <3>; |
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#address-cells = <0>; |
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interrupt-controller; |
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reg = <0x0 0x11900000 0 0x40000>, |
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<0x0 0x11940000 0 0x60000>; |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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};
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