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54 lines
1.2 KiB
54 lines
1.2 KiB
// SPDX-License-Identifier: (GPL-2.0 or MIT) |
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/* |
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* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) with R-Car H3e-2G |
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* |
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* Copyright (C) 2021 Glider bv |
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* |
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* Based on r8a77951-ulcb.dts |
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* |
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* Copyright (C) 2016 Renesas Electronics Corp. |
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* Copyright (C) 2016 Cogent Embedded, Inc. |
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*/ |
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/dts-v1/; |
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#include "r8a779m1.dtsi" |
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#include "ulcb.dtsi" |
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/ { |
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model = "Renesas H3ULCB board based on r8a779m1"; |
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compatible = "renesas,h3ulcb", "renesas,r8a779m1", "renesas,r8a7795"; |
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memory@48000000 { |
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device_type = "memory"; |
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/* first 128MB is reserved for secure area. */ |
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reg = <0x0 0x48000000 0x0 0x38000000>; |
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}; |
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memory@500000000 { |
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device_type = "memory"; |
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reg = <0x5 0x00000000 0x0 0x40000000>; |
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}; |
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memory@600000000 { |
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device_type = "memory"; |
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reg = <0x6 0x00000000 0x0 0x40000000>; |
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}; |
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memory@700000000 { |
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device_type = "memory"; |
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reg = <0x7 0x00000000 0x0 0x40000000>; |
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}; |
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}; |
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&du { |
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clocks = <&cpg CPG_MOD 724>, |
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<&cpg CPG_MOD 723>, |
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<&cpg CPG_MOD 722>, |
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<&cpg CPG_MOD 721>, |
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<&versaclock5 1>, |
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<&versaclock5 3>, |
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<&versaclock5 4>, |
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<&versaclock5 2>; |
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clock-names = "du.0", "du.1", "du.2", "du.3", |
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"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; |
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};
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