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2054 lines
54 KiB
2054 lines
54 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <dt-bindings/clock/tegra210-car.h> |
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#include <dt-bindings/gpio/tegra-gpio.h> |
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#include <dt-bindings/memory/tegra210-mc.h> |
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#include <dt-bindings/pinctrl/pinctrl-tegra.h> |
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#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> |
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#include <dt-bindings/reset/tegra210-car.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/thermal/tegra124-soctherm.h> |
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#include <dt-bindings/soc/tegra-pmc.h> |
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/ { |
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compatible = "nvidia,tegra210"; |
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interrupt-parent = <&lic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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pcie@1003000 { |
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compatible = "nvidia,tegra210-pcie"; |
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device_type = "pci"; |
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reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ |
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<0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ |
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<0x0 0x02000000 0x0 0x10000000>; /* configuration space */ |
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reg-names = "pads", "afi", "cs"; |
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ |
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ |
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interrupt-names = "intr", "msi"; |
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#interrupt-cells = <1>; |
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interrupt-map-mask = <0 0 0 0>; |
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interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
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bus-range = <0x00 0xff>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ |
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<0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ |
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<0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ |
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<0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ |
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<0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ |
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clocks = <&tegra_car TEGRA210_CLK_PCIE>, |
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<&tegra_car TEGRA210_CLK_AFI>, |
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<&tegra_car TEGRA210_CLK_PLL_E>, |
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<&tegra_car TEGRA210_CLK_CML0>; |
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clock-names = "pex", "afi", "pll_e", "cml"; |
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resets = <&tegra_car 70>, |
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<&tegra_car 72>, |
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<&tegra_car 74>; |
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reset-names = "pex", "afi", "pcie_x"; |
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pinctrl-names = "default", "idle"; |
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pinctrl-0 = <&pex_dpd_disable>; |
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pinctrl-1 = <&pex_dpd_enable>; |
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status = "disabled"; |
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pci@1,0 { |
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device_type = "pci"; |
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assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; |
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reg = <0x000800 0 0 0 0>; |
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bus-range = <0x00 0xff>; |
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status = "disabled"; |
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|
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges; |
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nvidia,num-lanes = <4>; |
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}; |
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pci@2,0 { |
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device_type = "pci"; |
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assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; |
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reg = <0x001000 0 0 0 0>; |
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bus-range = <0x00 0xff>; |
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status = "disabled"; |
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|
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges; |
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|
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nvidia,num-lanes = <1>; |
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}; |
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}; |
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host1x@50000000 { |
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compatible = "nvidia,tegra210-host1x"; |
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reg = <0x0 0x50000000 0x0 0x00034000>; |
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
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interrupt-names = "syncpt", "host1x"; |
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clocks = <&tegra_car TEGRA210_CLK_HOST1X>; |
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clock-names = "host1x"; |
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resets = <&tegra_car 28>; |
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reset-names = "host1x"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; |
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iommus = <&mc TEGRA_SWGROUP_HC>; |
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dpaux1: dpaux@54040000 { |
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compatible = "nvidia,tegra210-dpaux"; |
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reg = <0x0 0x54040000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, |
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<&tegra_car TEGRA210_CLK_PLL_DP>; |
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clock-names = "dpaux", "parent"; |
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resets = <&tegra_car 207>; |
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reset-names = "dpaux"; |
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power-domains = <&pd_sor>; |
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status = "disabled"; |
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state_dpaux1_aux: pinmux-aux { |
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groups = "dpaux-io"; |
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function = "aux"; |
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}; |
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state_dpaux1_i2c: pinmux-i2c { |
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groups = "dpaux-io"; |
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function = "i2c"; |
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}; |
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state_dpaux1_off: pinmux-off { |
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groups = "dpaux-io"; |
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function = "off"; |
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}; |
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i2c-bus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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vi@54080000 { |
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compatible = "nvidia,tegra210-vi"; |
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reg = <0x0 0x54080000 0x0 0x700>; |
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; |
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; |
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clocks = <&tegra_car TEGRA210_CLK_VI>; |
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power-domains = <&pd_venc>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x0 0x54080000 0x2000>; |
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csi@838 { |
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compatible = "nvidia,tegra210-csi"; |
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reg = <0x838 0x1300>; |
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status = "disabled"; |
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assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, |
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<&tegra_car TEGRA210_CLK_CILCD>, |
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<&tegra_car TEGRA210_CLK_CILE>, |
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<&tegra_car TEGRA210_CLK_CSI_TPG>; |
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, |
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<&tegra_car TEGRA210_CLK_PLL_P>, |
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<&tegra_car TEGRA210_CLK_PLL_P>; |
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assigned-clock-rates = <102000000>, |
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<102000000>, |
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<102000000>, |
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<972000000>; |
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clocks = <&tegra_car TEGRA210_CLK_CSI>, |
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<&tegra_car TEGRA210_CLK_CILAB>, |
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<&tegra_car TEGRA210_CLK_CILCD>, |
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<&tegra_car TEGRA210_CLK_CILE>, |
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<&tegra_car TEGRA210_CLK_CSI_TPG>; |
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clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; |
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power-domains = <&pd_sor>; |
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}; |
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}; |
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tsec@54100000 { |
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compatible = "nvidia,tegra210-tsec"; |
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reg = <0x0 0x54100000 0x0 0x00040000>; |
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}; |
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dc@54200000 { |
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compatible = "nvidia,tegra210-dc"; |
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reg = <0x0 0x54200000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_DISP1>; |
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clock-names = "dc"; |
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resets = <&tegra_car 27>; |
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reset-names = "dc"; |
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iommus = <&mc TEGRA_SWGROUP_DC>; |
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nvidia,outputs = <&dsia &dsib &sor0 &sor1>; |
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nvidia,head = <0>; |
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}; |
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dc@54240000 { |
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compatible = "nvidia,tegra210-dc"; |
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reg = <0x0 0x54240000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_DISP2>; |
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clock-names = "dc"; |
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resets = <&tegra_car 26>; |
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reset-names = "dc"; |
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iommus = <&mc TEGRA_SWGROUP_DCB>; |
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nvidia,outputs = <&dsia &dsib &sor0 &sor1>; |
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nvidia,head = <1>; |
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}; |
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dsia: dsi@54300000 { |
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compatible = "nvidia,tegra210-dsi"; |
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reg = <0x0 0x54300000 0x0 0x00040000>; |
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clocks = <&tegra_car TEGRA210_CLK_DSIA>, |
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<&tegra_car TEGRA210_CLK_DSIALP>, |
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<&tegra_car TEGRA210_CLK_PLL_D_OUT0>; |
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clock-names = "dsi", "lp", "parent"; |
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resets = <&tegra_car 48>; |
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reset-names = "dsi"; |
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power-domains = <&pd_sor>; |
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nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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vic@54340000 { |
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compatible = "nvidia,tegra210-vic"; |
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reg = <0x0 0x54340000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_VIC03>; |
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clock-names = "vic"; |
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resets = <&tegra_car 178>; |
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reset-names = "vic"; |
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iommus = <&mc TEGRA_SWGROUP_VIC>; |
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power-domains = <&pd_vic>; |
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}; |
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nvjpg@54380000 { |
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compatible = "nvidia,tegra210-nvjpg"; |
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reg = <0x0 0x54380000 0x0 0x00040000>; |
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status = "disabled"; |
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}; |
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dsib: dsi@54400000 { |
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compatible = "nvidia,tegra210-dsi"; |
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reg = <0x0 0x54400000 0x0 0x00040000>; |
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clocks = <&tegra_car TEGRA210_CLK_DSIB>, |
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<&tegra_car TEGRA210_CLK_DSIBLP>, |
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<&tegra_car TEGRA210_CLK_PLL_D_OUT0>; |
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clock-names = "dsi", "lp", "parent"; |
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resets = <&tegra_car 82>; |
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reset-names = "dsi"; |
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power-domains = <&pd_sor>; |
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nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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nvdec@54480000 { |
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compatible = "nvidia,tegra210-nvdec"; |
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reg = <0x0 0x54480000 0x0 0x00040000>; |
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status = "disabled"; |
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}; |
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nvenc@544c0000 { |
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compatible = "nvidia,tegra210-nvenc"; |
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reg = <0x0 0x544c0000 0x0 0x00040000>; |
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status = "disabled"; |
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}; |
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tsec@54500000 { |
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compatible = "nvidia,tegra210-tsec"; |
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reg = <0x0 0x54500000 0x0 0x00040000>; |
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status = "disabled"; |
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}; |
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sor0: sor@54540000 { |
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compatible = "nvidia,tegra210-sor"; |
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reg = <0x0 0x54540000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_SOR0>, |
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<&tegra_car TEGRA210_CLK_SOR0_OUT>, |
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<&tegra_car TEGRA210_CLK_PLL_D_OUT0>, |
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<&tegra_car TEGRA210_CLK_PLL_DP>, |
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<&tegra_car TEGRA210_CLK_SOR_SAFE>; |
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clock-names = "sor", "out", "parent", "dp", "safe"; |
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resets = <&tegra_car 182>; |
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reset-names = "sor"; |
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pinctrl-0 = <&state_dpaux_aux>; |
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pinctrl-1 = <&state_dpaux_i2c>; |
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pinctrl-2 = <&state_dpaux_off>; |
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pinctrl-names = "aux", "i2c", "off"; |
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power-domains = <&pd_sor>; |
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status = "disabled"; |
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}; |
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sor1: sor@54580000 { |
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compatible = "nvidia,tegra210-sor1"; |
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reg = <0x0 0x54580000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_SOR1>, |
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<&tegra_car TEGRA210_CLK_SOR1_OUT>, |
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<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, |
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<&tegra_car TEGRA210_CLK_PLL_DP>, |
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<&tegra_car TEGRA210_CLK_SOR_SAFE>; |
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clock-names = "sor", "out", "parent", "dp", "safe"; |
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resets = <&tegra_car 183>; |
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reset-names = "sor"; |
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pinctrl-0 = <&state_dpaux1_aux>; |
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pinctrl-1 = <&state_dpaux1_i2c>; |
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pinctrl-2 = <&state_dpaux1_off>; |
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pinctrl-names = "aux", "i2c", "off"; |
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power-domains = <&pd_sor>; |
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status = "disabled"; |
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}; |
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dpaux: dpaux@545c0000 { |
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compatible = "nvidia,tegra210-dpaux"; |
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reg = <0x0 0x545c0000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_DPAUX>, |
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<&tegra_car TEGRA210_CLK_PLL_DP>; |
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clock-names = "dpaux", "parent"; |
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resets = <&tegra_car 181>; |
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reset-names = "dpaux"; |
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power-domains = <&pd_sor>; |
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status = "disabled"; |
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state_dpaux_aux: pinmux-aux { |
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groups = "dpaux-io"; |
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function = "aux"; |
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}; |
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state_dpaux_i2c: pinmux-i2c { |
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groups = "dpaux-io"; |
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function = "i2c"; |
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}; |
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state_dpaux_off: pinmux-off { |
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groups = "dpaux-io"; |
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function = "off"; |
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}; |
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i2c-bus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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isp@54600000 { |
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compatible = "nvidia,tegra210-isp"; |
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reg = <0x0 0x54600000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_ISPA>; |
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resets = <&tegra_car 23>; |
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reset-names = "isp"; |
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status = "disabled"; |
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}; |
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isp@54680000 { |
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compatible = "nvidia,tegra210-isp"; |
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reg = <0x0 0x54680000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_ISPB>; |
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resets = <&tegra_car 3>; |
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reset-names = "isp"; |
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status = "disabled"; |
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}; |
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i2c@546c0000 { |
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compatible = "nvidia,tegra210-i2c-vi"; |
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reg = <0x0 0x546c0000 0x0 0x00040000>; |
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, |
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<&tegra_car TEGRA210_CLK_I2CSLOW>; |
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clock-names = "div-clk", "slow"; |
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resets = <&tegra_car 208>; |
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reset-names = "i2c"; |
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power-domains = <&pd_venc>; |
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status = "disabled"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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gic: interrupt-controller@50041000 { |
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compatible = "arm,gic-400"; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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reg = <0x0 0x50041000 0x0 0x1000>, |
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<0x0 0x50042000 0x0 0x2000>, |
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<0x0 0x50044000 0x0 0x2000>, |
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<0x0 0x50046000 0x0 0x2000>; |
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interrupts = <GIC_PPI 9 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
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interrupt-parent = <&gic>; |
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}; |
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gpu@57000000 { |
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compatible = "nvidia,gm20b"; |
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reg = <0x0 0x57000000 0x0 0x01000000>, |
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<0x0 0x58000000 0x0 0x01000000>; |
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "stall", "nonstall"; |
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clocks = <&tegra_car TEGRA210_CLK_GPU>, |
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<&tegra_car TEGRA210_CLK_PLL_P_OUT5>, |
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<&tegra_car TEGRA210_CLK_PLL_G_REF>; |
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clock-names = "gpu", "pwr", "ref"; |
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resets = <&tegra_car 184>; |
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reset-names = "gpu"; |
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|
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iommus = <&mc TEGRA_SWGROUP_GPU>; |
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|
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status = "disabled"; |
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}; |
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|
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lic: interrupt-controller@60004000 { |
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compatible = "nvidia,tegra210-ictlr"; |
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reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ |
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<0x0 0x60004100 0x0 0x40>, /* secondary controller */ |
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<0x0 0x60004200 0x0 0x40>, /* tertiary controller */ |
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<0x0 0x60004300 0x0 0x40>, /* quaternary controller */ |
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<0x0 0x60004400 0x0 0x40>, /* quinary controller */ |
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<0x0 0x60004500 0x0 0x40>; /* senary controller */ |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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interrupt-parent = <&gic>; |
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}; |
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|
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timer@60005000 { |
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compatible = "nvidia,tegra210-timer"; |
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reg = <0x0 0x60005000 0x0 0x400>; |
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&tegra_car TEGRA210_CLK_TIMER>; |
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clock-names = "timer"; |
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}; |
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|
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tegra_car: clock@60006000 { |
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compatible = "nvidia,tegra210-car"; |
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reg = <0x0 0x60006000 0x0 0x1000>; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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}; |
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|
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flow-controller@60007000 { |
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compatible = "nvidia,tegra210-flowctrl"; |
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reg = <0x0 0x60007000 0x0 0x1000>; |
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}; |
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|
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gpio: gpio@6000d000 { |
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compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; |
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reg = <0x0 0x6000d000 0x0 0x1000>; |
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
|
#gpio-cells = <2>; |
|
gpio-controller; |
|
#interrupt-cells = <2>; |
|
interrupt-controller; |
|
}; |
|
|
|
apbdma: dma@60020000 { |
|
compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; |
|
reg = <0x0 0x60020000 0x0 0x1400>; |
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_APBDMA>; |
|
clock-names = "dma"; |
|
resets = <&tegra_car 34>; |
|
reset-names = "dma"; |
|
#dma-cells = <1>; |
|
}; |
|
|
|
apbmisc@70000800 { |
|
compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; |
|
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ |
|
<0x0 0x70000008 0x0 0x04>; /* Strapping options */ |
|
}; |
|
|
|
pinmux: pinmux@700008d4 { |
|
compatible = "nvidia,tegra210-pinmux"; |
|
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ |
|
<0x0 0x70003000 0x0 0x294>; /* Mux registers */ |
|
sdmmc1_3v3_drv: sdmmc1-3v3-drv { |
|
sdmmc1 { |
|
nvidia,pins = "drive_sdmmc1"; |
|
nvidia,pull-down-strength = <0x8>; |
|
nvidia,pull-up-strength = <0x8>; |
|
}; |
|
}; |
|
sdmmc1_1v8_drv: sdmmc1-1v8-drv { |
|
sdmmc1 { |
|
nvidia,pins = "drive_sdmmc1"; |
|
nvidia,pull-down-strength = <0x4>; |
|
nvidia,pull-up-strength = <0x3>; |
|
}; |
|
}; |
|
sdmmc2_1v8_drv: sdmmc2-1v8-drv { |
|
sdmmc2 { |
|
nvidia,pins = "drive_sdmmc2"; |
|
nvidia,pull-down-strength = <0x10>; |
|
nvidia,pull-up-strength = <0x10>; |
|
}; |
|
}; |
|
sdmmc3_3v3_drv: sdmmc3-3v3-drv { |
|
sdmmc3 { |
|
nvidia,pins = "drive_sdmmc3"; |
|
nvidia,pull-down-strength = <0x8>; |
|
nvidia,pull-up-strength = <0x8>; |
|
}; |
|
}; |
|
sdmmc3_1v8_drv: sdmmc3-1v8-drv { |
|
sdmmc3 { |
|
nvidia,pins = "drive_sdmmc3"; |
|
nvidia,pull-down-strength = <0x4>; |
|
nvidia,pull-up-strength = <0x3>; |
|
}; |
|
}; |
|
sdmmc4_1v8_drv: sdmmc4-1v8-drv { |
|
sdmmc4 { |
|
nvidia,pins = "drive_sdmmc4"; |
|
nvidia,pull-down-strength = <0x10>; |
|
nvidia,pull-up-strength = <0x10>; |
|
}; |
|
}; |
|
}; |
|
|
|
/* |
|
* There are two serial driver i.e. 8250 based simple serial |
|
* driver and APB DMA based serial driver for higher baudrate |
|
* and performance. To enable the 8250 based driver, the compatible |
|
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable |
|
* the APB DMA based serial driver, the compatible is |
|
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". |
|
*/ |
|
uarta: serial@70006000 { |
|
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; |
|
reg = <0x0 0x70006000 0x0 0x40>; |
|
reg-shift = <2>; |
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_UARTA>; |
|
clock-names = "serial"; |
|
resets = <&tegra_car 6>; |
|
reset-names = "serial"; |
|
dmas = <&apbdma 8>, <&apbdma 8>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
uartb: serial@70006040 { |
|
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; |
|
reg = <0x0 0x70006040 0x0 0x40>; |
|
reg-shift = <2>; |
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_UARTB>; |
|
clock-names = "serial"; |
|
resets = <&tegra_car 7>; |
|
reset-names = "serial"; |
|
dmas = <&apbdma 9>, <&apbdma 9>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
uartc: serial@70006200 { |
|
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; |
|
reg = <0x0 0x70006200 0x0 0x40>; |
|
reg-shift = <2>; |
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_UARTC>; |
|
clock-names = "serial"; |
|
resets = <&tegra_car 55>; |
|
reset-names = "serial"; |
|
dmas = <&apbdma 10>, <&apbdma 10>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
uartd: serial@70006300 { |
|
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; |
|
reg = <0x0 0x70006300 0x0 0x40>; |
|
reg-shift = <2>; |
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_UARTD>; |
|
clock-names = "serial"; |
|
resets = <&tegra_car 65>; |
|
reset-names = "serial"; |
|
dmas = <&apbdma 19>, <&apbdma 19>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
pwm: pwm@7000a000 { |
|
compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; |
|
reg = <0x0 0x7000a000 0x0 0x100>; |
|
#pwm-cells = <2>; |
|
clocks = <&tegra_car TEGRA210_CLK_PWM>; |
|
clock-names = "pwm"; |
|
resets = <&tegra_car 17>; |
|
reset-names = "pwm"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c@7000c000 { |
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; |
|
reg = <0x0 0x7000c000 0x0 0x100>; |
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2C1>; |
|
clock-names = "div-clk"; |
|
resets = <&tegra_car 12>; |
|
reset-names = "i2c"; |
|
dmas = <&apbdma 21>, <&apbdma 21>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c@7000c400 { |
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; |
|
reg = <0x0 0x7000c400 0x0 0x100>; |
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2C2>; |
|
clock-names = "div-clk"; |
|
resets = <&tegra_car 54>; |
|
reset-names = "i2c"; |
|
dmas = <&apbdma 22>, <&apbdma 22>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c@7000c500 { |
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; |
|
reg = <0x0 0x7000c500 0x0 0x100>; |
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2C3>; |
|
clock-names = "div-clk"; |
|
resets = <&tegra_car 67>; |
|
reset-names = "i2c"; |
|
dmas = <&apbdma 23>, <&apbdma 23>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c@7000c700 { |
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; |
|
reg = <0x0 0x7000c700 0x0 0x100>; |
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2C4>; |
|
clock-names = "div-clk"; |
|
resets = <&tegra_car 103>; |
|
reset-names = "i2c"; |
|
dmas = <&apbdma 26>, <&apbdma 26>; |
|
dma-names = "rx", "tx"; |
|
pinctrl-0 = <&state_dpaux1_i2c>; |
|
pinctrl-1 = <&state_dpaux1_off>; |
|
pinctrl-names = "default", "idle"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c@7000d000 { |
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; |
|
reg = <0x0 0x7000d000 0x0 0x100>; |
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2C5>; |
|
clock-names = "div-clk"; |
|
resets = <&tegra_car 47>; |
|
reset-names = "i2c"; |
|
dmas = <&apbdma 24>, <&apbdma 24>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c@7000d100 { |
|
compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; |
|
reg = <0x0 0x7000d100 0x0 0x100>; |
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2C6>; |
|
clock-names = "div-clk"; |
|
resets = <&tegra_car 166>; |
|
reset-names = "i2c"; |
|
dmas = <&apbdma 30>, <&apbdma 30>; |
|
dma-names = "rx", "tx"; |
|
pinctrl-0 = <&state_dpaux_i2c>; |
|
pinctrl-1 = <&state_dpaux_off>; |
|
pinctrl-names = "default", "idle"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi@7000d400 { |
|
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; |
|
reg = <0x0 0x7000d400 0x0 0x200>; |
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_SBC1>; |
|
clock-names = "spi"; |
|
resets = <&tegra_car 41>; |
|
reset-names = "spi"; |
|
dmas = <&apbdma 15>, <&apbdma 15>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi@7000d600 { |
|
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; |
|
reg = <0x0 0x7000d600 0x0 0x200>; |
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_SBC2>; |
|
clock-names = "spi"; |
|
resets = <&tegra_car 44>; |
|
reset-names = "spi"; |
|
dmas = <&apbdma 16>, <&apbdma 16>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi@7000d800 { |
|
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; |
|
reg = <0x0 0x7000d800 0x0 0x200>; |
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_SBC3>; |
|
clock-names = "spi"; |
|
resets = <&tegra_car 46>; |
|
reset-names = "spi"; |
|
dmas = <&apbdma 17>, <&apbdma 17>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi@7000da00 { |
|
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; |
|
reg = <0x0 0x7000da00 0x0 0x200>; |
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_SBC4>; |
|
clock-names = "spi"; |
|
resets = <&tegra_car 68>; |
|
reset-names = "spi"; |
|
dmas = <&apbdma 18>, <&apbdma 18>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
rtc@7000e000 { |
|
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; |
|
reg = <0x0 0x7000e000 0x0 0x100>; |
|
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-parent = <&tegra_pmc>; |
|
clocks = <&tegra_car TEGRA210_CLK_RTC>; |
|
clock-names = "rtc"; |
|
}; |
|
|
|
tegra_pmc: pmc@7000e400 { |
|
compatible = "nvidia,tegra210-pmc"; |
|
reg = <0x0 0x7000e400 0x0 0x400>; |
|
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; |
|
clock-names = "pclk", "clk32k_in"; |
|
#clock-cells = <1>; |
|
#interrupt-cells = <2>; |
|
interrupt-controller; |
|
|
|
powergates { |
|
pd_audio: aud { |
|
clocks = <&tegra_car TEGRA210_CLK_APE>, |
|
<&tegra_car TEGRA210_CLK_APB2APE>; |
|
resets = <&tegra_car 198>; |
|
#power-domain-cells = <0>; |
|
}; |
|
|
|
pd_sor: sor { |
|
clocks = <&tegra_car TEGRA210_CLK_SOR0>, |
|
<&tegra_car TEGRA210_CLK_SOR1>, |
|
<&tegra_car TEGRA210_CLK_CILAB>, |
|
<&tegra_car TEGRA210_CLK_CILCD>, |
|
<&tegra_car TEGRA210_CLK_CILE>, |
|
<&tegra_car TEGRA210_CLK_DSIA>, |
|
<&tegra_car TEGRA210_CLK_DSIB>, |
|
<&tegra_car TEGRA210_CLK_DPAUX>, |
|
<&tegra_car TEGRA210_CLK_DPAUX1>, |
|
<&tegra_car TEGRA210_CLK_MIPI_CAL>; |
|
resets = <&tegra_car TEGRA210_CLK_SOR0>, |
|
<&tegra_car TEGRA210_CLK_SOR1>, |
|
<&tegra_car TEGRA210_CLK_DSIA>, |
|
<&tegra_car TEGRA210_CLK_DSIB>, |
|
<&tegra_car TEGRA210_CLK_DPAUX>, |
|
<&tegra_car TEGRA210_CLK_DPAUX1>, |
|
<&tegra_car TEGRA210_CLK_MIPI_CAL>; |
|
#power-domain-cells = <0>; |
|
}; |
|
|
|
pd_xusbss: xusba { |
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; |
|
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; |
|
#power-domain-cells = <0>; |
|
}; |
|
|
|
pd_xusbdev: xusbb { |
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; |
|
resets = <&tegra_car 95>; |
|
#power-domain-cells = <0>; |
|
}; |
|
|
|
pd_xusbhost: xusbc { |
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; |
|
resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; |
|
#power-domain-cells = <0>; |
|
}; |
|
|
|
pd_vic: vic { |
|
clocks = <&tegra_car TEGRA210_CLK_VIC03>; |
|
clock-names = "vic"; |
|
resets = <&tegra_car 178>; |
|
reset-names = "vic"; |
|
#power-domain-cells = <0>; |
|
}; |
|
|
|
pd_venc: venc { |
|
clocks = <&tegra_car TEGRA210_CLK_VI>, |
|
<&tegra_car TEGRA210_CLK_CSI>; |
|
resets = <&mc TEGRA210_MC_RESET_VI>, |
|
<&tegra_car 20>, |
|
<&tegra_car 52>; |
|
#power-domain-cells = <0>; |
|
}; |
|
}; |
|
|
|
sdmmc1_3v3: sdmmc1-3v3 { |
|
pins = "sdmmc1"; |
|
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; |
|
}; |
|
|
|
sdmmc1_1v8: sdmmc1-1v8 { |
|
pins = "sdmmc1"; |
|
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; |
|
}; |
|
|
|
sdmmc3_3v3: sdmmc3-3v3 { |
|
pins = "sdmmc3"; |
|
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; |
|
}; |
|
|
|
sdmmc3_1v8: sdmmc3-1v8 { |
|
pins = "sdmmc3"; |
|
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; |
|
}; |
|
|
|
pex_dpd_disable: pex_en { |
|
pex-dpd-disable { |
|
pins = "pex-bias", "pex-clk1", "pex-clk2"; |
|
low-power-disable; |
|
}; |
|
}; |
|
|
|
pex_dpd_enable: pex_dis { |
|
pex-dpd-enable { |
|
pins = "pex-bias", "pex-clk1", "pex-clk2"; |
|
low-power-enable; |
|
}; |
|
}; |
|
}; |
|
|
|
fuse@7000f800 { |
|
compatible = "nvidia,tegra210-efuse"; |
|
reg = <0x0 0x7000f800 0x0 0x400>; |
|
clocks = <&tegra_car TEGRA210_CLK_FUSE>; |
|
clock-names = "fuse"; |
|
resets = <&tegra_car 39>; |
|
reset-names = "fuse"; |
|
}; |
|
|
|
mc: memory-controller@70019000 { |
|
compatible = "nvidia,tegra210-mc"; |
|
reg = <0x0 0x70019000 0x0 0x1000>; |
|
clocks = <&tegra_car TEGRA210_CLK_MC>; |
|
clock-names = "mc"; |
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
#iommu-cells = <1>; |
|
#reset-cells = <1>; |
|
}; |
|
|
|
emc: external-memory-controller@7001b000 { |
|
compatible = "nvidia,tegra210-emc"; |
|
reg = <0x0 0x7001b000 0x0 0x1000>, |
|
<0x0 0x7001e000 0x0 0x1000>, |
|
<0x0 0x7001f000 0x0 0x1000>; |
|
clocks = <&tegra_car TEGRA210_CLK_EMC>; |
|
clock-names = "emc"; |
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
|
nvidia,memory-controller = <&mc>; |
|
#cooling-cells = <2>; |
|
}; |
|
|
|
sata@70020000 { |
|
compatible = "nvidia,tegra210-ahci"; |
|
reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ |
|
<0x0 0x70020000 0x0 0x7000>, /* SATA */ |
|
<0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ |
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_SATA>, |
|
<&tegra_car TEGRA210_CLK_SATA_OOB>; |
|
clock-names = "sata", "sata-oob"; |
|
resets = <&tegra_car 124>, |
|
<&tegra_car 129>, |
|
<&tegra_car 123>; |
|
reset-names = "sata", "sata-cold", "sata-oob"; |
|
status = "disabled"; |
|
}; |
|
|
|
hda@70030000 { |
|
compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; |
|
reg = <0x0 0x70030000 0x0 0x10000>; |
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_HDA>, |
|
<&tegra_car TEGRA210_CLK_HDA2HDMI>, |
|
<&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; |
|
clock-names = "hda", "hda2hdmi", "hda2codec_2x"; |
|
resets = <&tegra_car 125>, /* hda */ |
|
<&tegra_car 128>, /* hda2hdmi */ |
|
<&tegra_car 111>; /* hda2codec_2x */ |
|
reset-names = "hda", "hda2hdmi", "hda2codec_2x"; |
|
power-domains = <&pd_sor>; |
|
status = "disabled"; |
|
}; |
|
|
|
usb@70090000 { |
|
compatible = "nvidia,tegra210-xusb"; |
|
reg = <0x0 0x70090000 0x0 0x8000>, |
|
<0x0 0x70098000 0x0 0x1000>, |
|
<0x0 0x70099000 0x0 0x1000>; |
|
reg-names = "hcd", "fpci", "ipfs"; |
|
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, |
|
<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, |
|
<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, |
|
<&tegra_car TEGRA210_CLK_XUSB_SS>, |
|
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, |
|
<&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, |
|
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, |
|
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, |
|
<&tegra_car TEGRA210_CLK_PLL_U_480M>, |
|
<&tegra_car TEGRA210_CLK_CLK_M>, |
|
<&tegra_car TEGRA210_CLK_PLL_E>; |
|
clock-names = "xusb_host", "xusb_host_src", |
|
"xusb_falcon_src", "xusb_ss", |
|
"xusb_ss_src", "xusb_ss_div2", |
|
"xusb_hs_src", "xusb_fs_src", |
|
"pll_u_480m", "clk_m", "pll_e"; |
|
resets = <&tegra_car 89>, <&tegra_car 156>, |
|
<&tegra_car 143>; |
|
reset-names = "xusb_host", "xusb_ss", "xusb_src"; |
|
power-domains = <&pd_xusbhost>, <&pd_xusbss>; |
|
power-domain-names = "xusb_host", "xusb_ss"; |
|
|
|
nvidia,xusb-padctl = <&padctl>; |
|
|
|
status = "disabled"; |
|
}; |
|
|
|
padctl: padctl@7009f000 { |
|
compatible = "nvidia,tegra210-xusb-padctl"; |
|
reg = <0x0 0x7009f000 0x0 0x1000>; |
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
|
resets = <&tegra_car 142>; |
|
reset-names = "padctl"; |
|
nvidia,pmc = <&tegra_pmc>; |
|
|
|
status = "disabled"; |
|
|
|
pads { |
|
usb2 { |
|
clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; |
|
clock-names = "trk"; |
|
status = "disabled"; |
|
|
|
lanes { |
|
usb2-0 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
usb2-1 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
usb2-2 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
usb2-3 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
}; |
|
}; |
|
|
|
hsic { |
|
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; |
|
clock-names = "trk"; |
|
status = "disabled"; |
|
|
|
lanes { |
|
hsic-0 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
hsic-1 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
}; |
|
}; |
|
|
|
pcie { |
|
clocks = <&tegra_car TEGRA210_CLK_PLL_E>; |
|
clock-names = "pll"; |
|
resets = <&tegra_car 205>; |
|
reset-names = "phy"; |
|
status = "disabled"; |
|
|
|
lanes { |
|
pcie-0 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
pcie-1 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
pcie-2 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
pcie-3 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
pcie-4 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
pcie-5 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
|
|
pcie-6 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
}; |
|
}; |
|
|
|
sata { |
|
clocks = <&tegra_car TEGRA210_CLK_PLL_E>; |
|
clock-names = "pll"; |
|
resets = <&tegra_car 204>; |
|
reset-names = "phy"; |
|
status = "disabled"; |
|
|
|
lanes { |
|
sata-0 { |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
ports { |
|
usb2-0 { |
|
status = "disabled"; |
|
}; |
|
|
|
usb2-1 { |
|
status = "disabled"; |
|
}; |
|
|
|
usb2-2 { |
|
status = "disabled"; |
|
}; |
|
|
|
usb2-3 { |
|
status = "disabled"; |
|
}; |
|
|
|
hsic-0 { |
|
status = "disabled"; |
|
}; |
|
|
|
usb3-0 { |
|
status = "disabled"; |
|
}; |
|
|
|
usb3-1 { |
|
status = "disabled"; |
|
}; |
|
|
|
usb3-2 { |
|
status = "disabled"; |
|
}; |
|
|
|
usb3-3 { |
|
status = "disabled"; |
|
}; |
|
}; |
|
}; |
|
|
|
mmc@700b0000 { |
|
compatible = "nvidia,tegra210-sdhci"; |
|
reg = <0x0 0x700b0000 0x0 0x200>; |
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, |
|
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; |
|
clock-names = "sdhci", "tmclk"; |
|
resets = <&tegra_car 14>; |
|
reset-names = "sdhci"; |
|
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", |
|
"sdmmc-3v3-drv", "sdmmc-1v8-drv"; |
|
pinctrl-0 = <&sdmmc1_3v3>; |
|
pinctrl-1 = <&sdmmc1_1v8>; |
|
pinctrl-2 = <&sdmmc1_3v3_drv>; |
|
pinctrl-3 = <&sdmmc1_1v8_drv>; |
|
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; |
|
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; |
|
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; |
|
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; |
|
nvidia,default-tap = <0x2>; |
|
nvidia,default-trim = <0x4>; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, |
|
<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, |
|
<&tegra_car TEGRA210_CLK_PLL_C4>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; |
|
assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; |
|
status = "disabled"; |
|
}; |
|
|
|
mmc@700b0200 { |
|
compatible = "nvidia,tegra210-sdhci"; |
|
reg = <0x0 0x700b0200 0x0 0x200>; |
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, |
|
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; |
|
clock-names = "sdhci", "tmclk"; |
|
resets = <&tegra_car 9>; |
|
reset-names = "sdhci"; |
|
pinctrl-names = "sdmmc-1v8-drv"; |
|
pinctrl-0 = <&sdmmc2_1v8_drv>; |
|
nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; |
|
nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; |
|
nvidia,default-tap = <0x8>; |
|
nvidia,default-trim = <0x0>; |
|
status = "disabled"; |
|
}; |
|
|
|
mmc@700b0400 { |
|
compatible = "nvidia,tegra210-sdhci"; |
|
reg = <0x0 0x700b0400 0x0 0x200>; |
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, |
|
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; |
|
clock-names = "sdhci", "tmclk"; |
|
resets = <&tegra_car 69>; |
|
reset-names = "sdhci"; |
|
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", |
|
"sdmmc-3v3-drv", "sdmmc-1v8-drv"; |
|
pinctrl-0 = <&sdmmc3_3v3>; |
|
pinctrl-1 = <&sdmmc3_1v8>; |
|
pinctrl-2 = <&sdmmc3_3v3_drv>; |
|
pinctrl-3 = <&sdmmc3_1v8_drv>; |
|
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; |
|
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; |
|
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; |
|
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; |
|
nvidia,default-tap = <0x3>; |
|
nvidia,default-trim = <0x3>; |
|
status = "disabled"; |
|
}; |
|
|
|
mmc@700b0600 { |
|
compatible = "nvidia,tegra210-sdhci"; |
|
reg = <0x0 0x700b0600 0x0 0x200>; |
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, |
|
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; |
|
clock-names = "sdhci", "tmclk"; |
|
resets = <&tegra_car 15>; |
|
reset-names = "sdhci"; |
|
pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; |
|
pinctrl-0 = <&sdmmc4_1v8_drv>; |
|
pinctrl-1 = <&sdmmc4_1v8_drv>; |
|
nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; |
|
nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; |
|
nvidia,default-tap = <0x8>; |
|
nvidia,default-trim = <0x0>; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, |
|
<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; |
|
nvidia,dqs-trim = <40>; |
|
mmc-hs400-1_8v; |
|
status = "disabled"; |
|
}; |
|
|
|
usb@700d0000 { |
|
compatible = "nvidia,tegra210-xudc"; |
|
reg = <0x0 0x700d0000 0x0 0x8000>, |
|
<0x0 0x700d8000 0x0 0x1000>, |
|
<0x0 0x700d9000 0x0 0x1000>; |
|
reg-names = "base", "fpci", "ipfs"; |
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, |
|
<&tegra_car TEGRA210_CLK_XUSB_SS>, |
|
<&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, |
|
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, |
|
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; |
|
clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; |
|
power-domains = <&pd_xusbdev>, <&pd_xusbss>; |
|
power-domain-names = "dev", "ss"; |
|
nvidia,xusb-padctl = <&padctl>; |
|
status = "disabled"; |
|
}; |
|
|
|
soctherm: thermal-sensor@700e2000 { |
|
compatible = "nvidia,tegra210-soctherm"; |
|
reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ |
|
<0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ |
|
reg-names = "soctherm-reg", "car-reg"; |
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "thermal", "edp"; |
|
clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, |
|
<&tegra_car TEGRA210_CLK_SOC_THERM>; |
|
clock-names = "tsensor", "soctherm"; |
|
resets = <&tegra_car 78>; |
|
reset-names = "soctherm"; |
|
#thermal-sensor-cells = <1>; |
|
|
|
throttle-cfgs { |
|
throttle_heavy: heavy { |
|
nvidia,priority = <100>; |
|
nvidia,cpu-throt-percent = <85>; |
|
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; |
|
|
|
#cooling-cells = <2>; |
|
}; |
|
}; |
|
}; |
|
|
|
mipi: mipi@700e3000 { |
|
compatible = "nvidia,tegra210-mipi"; |
|
reg = <0x0 0x700e3000 0x0 0x100>; |
|
clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; |
|
clock-names = "mipi-cal"; |
|
power-domains = <&pd_sor>; |
|
#nvidia,mipi-calibrate-cells = <1>; |
|
}; |
|
|
|
dfll: clock@70110000 { |
|
compatible = "nvidia,tegra210-dfll"; |
|
reg = <0 0x70110000 0 0x100>, /* DFLL control */ |
|
<0 0x70110000 0 0x100>, /* I2C output control */ |
|
<0 0x70110100 0 0x100>, /* Integrated I2C controller */ |
|
<0 0x70110200 0 0x100>; /* Look-up table RAM */ |
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, |
|
<&tegra_car TEGRA210_CLK_DFLL_REF>, |
|
<&tegra_car TEGRA210_CLK_I2C5>; |
|
clock-names = "soc", "ref", "i2c"; |
|
resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; |
|
reset-names = "dvco"; |
|
#clock-cells = <0>; |
|
clock-output-names = "dfllCPU_out"; |
|
status = "disabled"; |
|
}; |
|
|
|
aconnect@702c0000 { |
|
compatible = "nvidia,tegra210-aconnect"; |
|
clocks = <&tegra_car TEGRA210_CLK_APE>, |
|
<&tegra_car TEGRA210_CLK_APB2APE>; |
|
clock-names = "ape", "apb2ape"; |
|
power-domains = <&pd_audio>; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; |
|
status = "disabled"; |
|
|
|
adma: dma-controller@702e2000 { |
|
compatible = "nvidia,tegra210-adma"; |
|
reg = <0x702e2000 0x2000>; |
|
interrupt-parent = <&agic>; |
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
|
#dma-cells = <1>; |
|
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; |
|
clock-names = "d_audio"; |
|
status = "disabled"; |
|
}; |
|
|
|
agic: interrupt-controller@702f9000 { |
|
compatible = "nvidia,tegra210-agic"; |
|
#interrupt-cells = <3>; |
|
interrupt-controller; |
|
reg = <0x702f9000 0x1000>, |
|
<0x702fa000 0x2000>; |
|
interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
|
clocks = <&tegra_car TEGRA210_CLK_APE>; |
|
clock-names = "clk"; |
|
status = "disabled"; |
|
}; |
|
|
|
tegra_ahub: ahub@702d0800 { |
|
compatible = "nvidia,tegra210-ahub"; |
|
reg = <0x702d0800 0x800>; |
|
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; |
|
clock-names = "ahub"; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
ranges = <0x702d0000 0x702d0000 0x0000e400>; |
|
status = "disabled"; |
|
|
|
tegra_admaif: admaif@702d0000 { |
|
compatible = "nvidia,tegra210-admaif"; |
|
reg = <0x702d0000 0x800>; |
|
dmas = <&adma 1>, <&adma 1>, |
|
<&adma 2>, <&adma 2>, |
|
<&adma 3>, <&adma 3>, |
|
<&adma 4>, <&adma 4>, |
|
<&adma 5>, <&adma 5>, |
|
<&adma 6>, <&adma 6>, |
|
<&adma 7>, <&adma 7>, |
|
<&adma 8>, <&adma 8>, |
|
<&adma 9>, <&adma 9>, |
|
<&adma 10>, <&adma 10>; |
|
dma-names = "rx1", "tx1", |
|
"rx2", "tx2", |
|
"rx3", "tx3", |
|
"rx4", "tx4", |
|
"rx5", "tx5", |
|
"rx6", "tx6", |
|
"rx7", "tx7", |
|
"rx8", "tx8", |
|
"rx9", "tx9", |
|
"rx10", "tx10"; |
|
status = "disabled"; |
|
|
|
ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
admaif1_port: port@0 { |
|
reg = <0>; |
|
|
|
admaif1_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif1_ep>; |
|
}; |
|
}; |
|
|
|
admaif2_port: port@1 { |
|
reg = <1>; |
|
|
|
admaif2_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif2_ep>; |
|
}; |
|
}; |
|
|
|
admaif3_port: port@2 { |
|
reg = <2>; |
|
|
|
admaif3_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif3_ep>; |
|
}; |
|
}; |
|
|
|
admaif4_port: port@3 { |
|
reg = <3>; |
|
|
|
admaif4_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif4_ep>; |
|
}; |
|
}; |
|
|
|
admaif5_port: port@4 { |
|
reg = <4>; |
|
|
|
admaif5_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif5_ep>; |
|
}; |
|
}; |
|
|
|
admaif6_port: port@5 { |
|
reg = <5>; |
|
|
|
admaif6_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif6_ep>; |
|
}; |
|
}; |
|
|
|
admaif7_port: port@6 { |
|
reg = <6>; |
|
|
|
admaif7_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif7_ep>; |
|
}; |
|
}; |
|
|
|
admaif8_port: port@7 { |
|
reg = <7>; |
|
|
|
admaif8_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif8_ep>; |
|
}; |
|
}; |
|
|
|
admaif9_port: port@8 { |
|
reg = <8>; |
|
|
|
admaif9_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif9_ep>; |
|
}; |
|
}; |
|
|
|
admaif10_port: port@9 { |
|
reg = <9>; |
|
|
|
admaif10_ep: endpoint { |
|
remote-endpoint = <&xbar_admaif10_ep>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
tegra_i2s1: i2s@702d1000 { |
|
compatible = "nvidia,tegra210-i2s"; |
|
reg = <0x702d1000 0x100>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2S0>, |
|
<&tegra_car TEGRA210_CLK_I2S0_SYNC>; |
|
clock-names = "i2s", "sync_input"; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
assigned-clock-rates = <1536000>; |
|
sound-name-prefix = "I2S1"; |
|
status = "disabled"; |
|
}; |
|
|
|
tegra_i2s2: i2s@702d1100 { |
|
compatible = "nvidia,tegra210-i2s"; |
|
reg = <0x702d1100 0x100>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2S1>, |
|
<&tegra_car TEGRA210_CLK_I2S1_SYNC>; |
|
clock-names = "i2s", "sync_input"; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
assigned-clock-rates = <1536000>; |
|
sound-name-prefix = "I2S2"; |
|
status = "disabled"; |
|
}; |
|
|
|
tegra_i2s3: i2s@702d1200 { |
|
compatible = "nvidia,tegra210-i2s"; |
|
reg = <0x702d1200 0x100>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2S2>, |
|
<&tegra_car TEGRA210_CLK_I2S2_SYNC>; |
|
clock-names = "i2s", "sync_input"; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
assigned-clock-rates = <1536000>; |
|
sound-name-prefix = "I2S3"; |
|
status = "disabled"; |
|
}; |
|
|
|
tegra_i2s4: i2s@702d1300 { |
|
compatible = "nvidia,tegra210-i2s"; |
|
reg = <0x702d1300 0x100>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2S3>, |
|
<&tegra_car TEGRA210_CLK_I2S3_SYNC>; |
|
clock-names = "i2s", "sync_input"; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
assigned-clock-rates = <1536000>; |
|
sound-name-prefix = "I2S4"; |
|
status = "disabled"; |
|
}; |
|
|
|
tegra_i2s5: i2s@702d1400 { |
|
compatible = "nvidia,tegra210-i2s"; |
|
reg = <0x702d1400 0x100>; |
|
clocks = <&tegra_car TEGRA210_CLK_I2S4>, |
|
<&tegra_car TEGRA210_CLK_I2S4_SYNC>; |
|
clock-names = "i2s", "sync_input"; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
assigned-clock-rates = <1536000>; |
|
sound-name-prefix = "I2S5"; |
|
status = "disabled"; |
|
}; |
|
|
|
tegra_dmic1: dmic@702d4000 { |
|
compatible = "nvidia,tegra210-dmic"; |
|
reg = <0x702d4000 0x100>; |
|
clocks = <&tegra_car TEGRA210_CLK_DMIC1>; |
|
clock-names = "dmic"; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
assigned-clock-rates = <3072000>; |
|
sound-name-prefix = "DMIC1"; |
|
status = "disabled"; |
|
}; |
|
|
|
tegra_dmic2: dmic@702d4100 { |
|
compatible = "nvidia,tegra210-dmic"; |
|
reg = <0x702d4100 0x100>; |
|
clocks = <&tegra_car TEGRA210_CLK_DMIC2>; |
|
clock-names = "dmic"; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
assigned-clock-rates = <3072000>; |
|
sound-name-prefix = "DMIC2"; |
|
status = "disabled"; |
|
}; |
|
|
|
tegra_dmic3: dmic@702d4200 { |
|
compatible = "nvidia,tegra210-dmic"; |
|
reg = <0x702d4200 0x100>; |
|
clocks = <&tegra_car TEGRA210_CLK_DMIC3>; |
|
clock-names = "dmic"; |
|
assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; |
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
assigned-clock-rates = <3072000>; |
|
sound-name-prefix = "DMIC3"; |
|
status = "disabled"; |
|
}; |
|
|
|
ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0x0>; |
|
|
|
xbar_admaif1_ep: endpoint { |
|
remote-endpoint = <&admaif1_ep>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <0x1>; |
|
|
|
xbar_admaif2_ep: endpoint { |
|
remote-endpoint = <&admaif2_ep>; |
|
}; |
|
}; |
|
|
|
port@2 { |
|
reg = <0x2>; |
|
|
|
xbar_admaif3_ep: endpoint { |
|
remote-endpoint = <&admaif3_ep>; |
|
}; |
|
}; |
|
|
|
port@3 { |
|
reg = <0x3>; |
|
|
|
xbar_admaif4_ep: endpoint { |
|
remote-endpoint = <&admaif4_ep>; |
|
}; |
|
}; |
|
|
|
port@4 { |
|
reg = <0x4>; |
|
xbar_admaif5_ep: endpoint { |
|
remote-endpoint = <&admaif5_ep>; |
|
}; |
|
}; |
|
port@5 { |
|
reg = <0x5>; |
|
|
|
xbar_admaif6_ep: endpoint { |
|
remote-endpoint = <&admaif6_ep>; |
|
}; |
|
}; |
|
|
|
port@6 { |
|
reg = <0x6>; |
|
|
|
xbar_admaif7_ep: endpoint { |
|
remote-endpoint = <&admaif7_ep>; |
|
}; |
|
}; |
|
|
|
port@7 { |
|
reg = <0x7>; |
|
|
|
xbar_admaif8_ep: endpoint { |
|
remote-endpoint = <&admaif8_ep>; |
|
}; |
|
}; |
|
|
|
port@8 { |
|
reg = <0x8>; |
|
|
|
xbar_admaif9_ep: endpoint { |
|
remote-endpoint = <&admaif9_ep>; |
|
}; |
|
}; |
|
|
|
port@9 { |
|
reg = <0x9>; |
|
|
|
xbar_admaif10_ep: endpoint { |
|
remote-endpoint = <&admaif10_ep>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
spi@70410000 { |
|
compatible = "nvidia,tegra210-qspi"; |
|
reg = <0x0 0x70410000 0x0 0x1000>; |
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_QSPI>, |
|
<&tegra_car TEGRA210_CLK_QSPI_PM>; |
|
clock-names = "qspi", "qspi_out"; |
|
resets = <&tegra_car 211>; |
|
reset-names = "qspi"; |
|
dmas = <&apbdma 5>, <&apbdma 5>; |
|
dma-names = "rx", "tx"; |
|
status = "disabled"; |
|
}; |
|
|
|
usb@7d000000 { |
|
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
|
reg = <0x0 0x7d000000 0x0 0x4000>; |
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
|
phy_type = "utmi"; |
|
clocks = <&tegra_car TEGRA210_CLK_USBD>; |
|
clock-names = "usb"; |
|
resets = <&tegra_car 22>; |
|
reset-names = "usb"; |
|
nvidia,phy = <&phy1>; |
|
status = "disabled"; |
|
}; |
|
|
|
phy1: usb-phy@7d000000 { |
|
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; |
|
reg = <0x0 0x7d000000 0x0 0x4000>, |
|
<0x0 0x7d000000 0x0 0x4000>; |
|
phy_type = "utmi"; |
|
clocks = <&tegra_car TEGRA210_CLK_USBD>, |
|
<&tegra_car TEGRA210_CLK_PLL_U>, |
|
<&tegra_car TEGRA210_CLK_USBD>; |
|
clock-names = "reg", "pll_u", "utmi-pads"; |
|
resets = <&tegra_car 22>, <&tegra_car 22>; |
|
reset-names = "usb", "utmi-pads"; |
|
nvidia,hssync-start-delay = <0>; |
|
nvidia,idle-wait-delay = <17>; |
|
nvidia,elastic-limit = <16>; |
|
nvidia,term-range-adj = <6>; |
|
nvidia,xcvr-setup = <9>; |
|
nvidia,xcvr-lsfslew = <0>; |
|
nvidia,xcvr-lsrslew = <3>; |
|
nvidia,hssquelch-level = <2>; |
|
nvidia,hsdiscon-level = <5>; |
|
nvidia,xcvr-hsslew = <12>; |
|
nvidia,has-utmi-pad-registers; |
|
status = "disabled"; |
|
}; |
|
|
|
usb@7d004000 { |
|
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
|
reg = <0x0 0x7d004000 0x0 0x4000>; |
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
|
phy_type = "utmi"; |
|
clocks = <&tegra_car TEGRA210_CLK_USB2>; |
|
clock-names = "usb"; |
|
resets = <&tegra_car 58>; |
|
reset-names = "usb"; |
|
nvidia,phy = <&phy2>; |
|
status = "disabled"; |
|
}; |
|
|
|
phy2: usb-phy@7d004000 { |
|
compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; |
|
reg = <0x0 0x7d004000 0x0 0x4000>, |
|
<0x0 0x7d000000 0x0 0x4000>; |
|
phy_type = "utmi"; |
|
clocks = <&tegra_car TEGRA210_CLK_USB2>, |
|
<&tegra_car TEGRA210_CLK_PLL_U>, |
|
<&tegra_car TEGRA210_CLK_USBD>; |
|
clock-names = "reg", "pll_u", "utmi-pads"; |
|
resets = <&tegra_car 58>, <&tegra_car 22>; |
|
reset-names = "usb", "utmi-pads"; |
|
nvidia,hssync-start-delay = <0>; |
|
nvidia,idle-wait-delay = <17>; |
|
nvidia,elastic-limit = <16>; |
|
nvidia,term-range-adj = <6>; |
|
nvidia,xcvr-setup = <9>; |
|
nvidia,xcvr-lsfslew = <0>; |
|
nvidia,xcvr-lsrslew = <3>; |
|
nvidia,hssquelch-level = <2>; |
|
nvidia,hsdiscon-level = <5>; |
|
nvidia,xcvr-hsslew = <12>; |
|
status = "disabled"; |
|
}; |
|
|
|
cpus { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
cpu@0 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a57"; |
|
reg = <0>; |
|
clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, |
|
<&tegra_car TEGRA210_CLK_PLL_X>, |
|
<&tegra_car TEGRA210_CLK_PLL_P_OUT4>, |
|
<&dfll>; |
|
clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; |
|
clock-latency = <300000>; |
|
cpu-idle-states = <&CPU_SLEEP>; |
|
next-level-cache = <&L2>; |
|
}; |
|
|
|
cpu@1 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a57"; |
|
reg = <1>; |
|
cpu-idle-states = <&CPU_SLEEP>; |
|
next-level-cache = <&L2>; |
|
}; |
|
|
|
cpu@2 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a57"; |
|
reg = <2>; |
|
cpu-idle-states = <&CPU_SLEEP>; |
|
next-level-cache = <&L2>; |
|
}; |
|
|
|
cpu@3 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a57"; |
|
reg = <3>; |
|
cpu-idle-states = <&CPU_SLEEP>; |
|
next-level-cache = <&L2>; |
|
}; |
|
|
|
idle-states { |
|
entry-method = "psci"; |
|
|
|
CPU_SLEEP: cpu-sleep { |
|
compatible = "arm,idle-state"; |
|
arm,psci-suspend-param = <0x40000007>; |
|
entry-latency-us = <100>; |
|
exit-latency-us = <30>; |
|
min-residency-us = <1000>; |
|
wakeup-latency-us = <130>; |
|
idle-state-name = "cpu-sleep"; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
L2: l2-cache { |
|
compatible = "cache"; |
|
}; |
|
}; |
|
|
|
pmu { |
|
compatible = "arm,armv8-pmuv3"; |
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} |
|
&{/cpus/cpu@2} &{/cpus/cpu@3}>; |
|
}; |
|
|
|
sound { |
|
status = "disabled"; |
|
|
|
clocks = <&tegra_car TEGRA210_CLK_PLL_A>, |
|
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
clock-names = "pll_a", "plla_out0"; |
|
|
|
assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, |
|
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>, |
|
<&tegra_car TEGRA210_CLK_EXTERN1>; |
|
assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; |
|
assigned-clock-rates = <368640000>, <49152000>, <12288000>; |
|
}; |
|
|
|
thermal-zones { |
|
cpu { |
|
polling-delay-passive = <1000>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = |
|
<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; |
|
|
|
trips { |
|
cpu-shutdown-trip { |
|
temperature = <102500>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
|
|
cpu_throttle_trip: throttle-trip { |
|
temperature = <98500>; |
|
hysteresis = <1000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu_throttle_trip>; |
|
cooling-device = <&throttle_heavy 1 1>; |
|
}; |
|
}; |
|
}; |
|
|
|
mem { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = |
|
<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; |
|
|
|
trips { |
|
dram_nominal: mem-nominal-trip { |
|
temperature = <50000>; |
|
hysteresis = <1000>; |
|
type = "passive"; |
|
}; |
|
|
|
dram_throttle: mem-throttle-trip { |
|
temperature = <70000>; |
|
hysteresis = <1000>; |
|
type = "active"; |
|
}; |
|
|
|
mem-hot-trip { |
|
temperature = <100000>; |
|
hysteresis = <1000>; |
|
type = "hot"; |
|
}; |
|
|
|
mem-shutdown-trip { |
|
temperature = <103000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
dram-passive { |
|
cooling-device = <&emc 0 0>; |
|
trip = <&dram_nominal>; |
|
}; |
|
|
|
dram-active { |
|
cooling-device = <&emc 1 1>; |
|
trip = <&dram_throttle>; |
|
}; |
|
}; |
|
}; |
|
|
|
gpu { |
|
polling-delay-passive = <1000>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = |
|
<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; |
|
|
|
trips { |
|
gpu-shutdown-trip { |
|
temperature = <103000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
|
|
gpu_throttle_trip: throttle-trip { |
|
temperature = <100000>; |
|
hysteresis = <1000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&gpu_throttle_trip>; |
|
cooling-device = <&throttle_heavy 1 1>; |
|
}; |
|
}; |
|
}; |
|
|
|
pllx { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = |
|
<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; |
|
|
|
trips { |
|
pllx-shutdown-trip { |
|
temperature = <103000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
|
|
pllx-throttle-trip { |
|
temperature = <100000>; |
|
hysteresis = <1000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
/* |
|
* There are currently no cooling maps, |
|
* because there are no cooling devices. |
|
*/ |
|
}; |
|
}; |
|
}; |
|
|
|
timer { |
|
compatible = "arm,armv8-timer"; |
|
interrupts = <GIC_PPI 13 |
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
|
<GIC_PPI 14 |
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
|
<GIC_PPI 11 |
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
|
<GIC_PPI 10 |
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
|
interrupt-parent = <&gic>; |
|
arm,no-tick-in-suspend; |
|
}; |
|
};
|
|
|