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752 lines
15 KiB
752 lines
15 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. |
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*/ |
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|
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/dts-v1/; |
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#include "sparx5_pcb_common.dtsi" |
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|
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/{ |
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gpio-restart { |
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compatible = "gpio-restart"; |
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gpios = <&gpio 37 GPIO_ACTIVE_LOW>; |
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priority = <200>; |
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}; |
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leds { |
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compatible = "gpio-leds"; |
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led@0 { |
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label = "eth60:yellow"; |
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gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>; |
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default-state = "off"; |
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}; |
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led@1 { |
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label = "eth60:green"; |
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gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>; |
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default-state = "off"; |
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}; |
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led@2 { |
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label = "eth61:yellow"; |
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gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>; |
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default-state = "off"; |
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}; |
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led@3 { |
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label = "eth61:green"; |
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gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>; |
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default-state = "off"; |
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}; |
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led@4 { |
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label = "eth62:yellow"; |
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gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>; |
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default-state = "off"; |
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}; |
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led@5 { |
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label = "eth62:green"; |
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gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>; |
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default-state = "off"; |
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}; |
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led@6 { |
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label = "eth63:yellow"; |
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gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>; |
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default-state = "off"; |
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}; |
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led@7 { |
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label = "eth63:green"; |
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gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>; |
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default-state = "off"; |
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}; |
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}; |
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}; |
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&gpio { |
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i2cmux_pins_i: i2cmux-pins-i { |
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pins = "GPIO_35", "GPIO_36", |
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"GPIO_50", "GPIO_51"; |
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function = "twi_scl_m"; |
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output-low; |
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}; |
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i2cmux_s29: i2cmux-0 { |
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pins = "GPIO_35"; |
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function = "twi_scl_m"; |
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output-high; |
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}; |
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i2cmux_s30: i2cmux-1 { |
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pins = "GPIO_36"; |
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function = "twi_scl_m"; |
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output-high; |
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}; |
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i2cmux_s31: i2cmux-2 { |
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pins = "GPIO_50"; |
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function = "twi_scl_m"; |
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output-high; |
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}; |
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i2cmux_s32: i2cmux-3 { |
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pins = "GPIO_51"; |
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function = "twi_scl_m"; |
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output-high; |
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}; |
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}; |
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&spi0 { |
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status = "okay"; |
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spi-flash@0 { |
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compatible = "jedec,spi-nor"; |
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spi-max-frequency = <8000000>; |
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reg = <0>; |
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}; |
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}; |
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&spi0 { |
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status = "okay"; |
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spi@0 { |
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compatible = "spi-mux"; |
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mux-controls = <&mux>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0>; /* CS0 */ |
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spi-flash@9 { |
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compatible = "jedec,spi-nor"; |
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spi-max-frequency = <8000000>; |
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reg = <0x9>; /* SPI */ |
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}; |
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}; |
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}; |
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&sgpio1 { |
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status = "okay"; |
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microchip,sgpio-port-ranges = <24 31>; |
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gpio@0 { |
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ngpios = <64>; |
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}; |
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gpio@1 { |
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ngpios = <64>; |
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}; |
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}; |
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&sgpio2 { |
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status = "okay"; |
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microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; |
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}; |
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&axi { |
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i2c0_imux: i2c0-imux@0 { |
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compatible = "i2c-mux-pinctrl"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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i2c-parent = <&i2c0>; |
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}; |
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}; |
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&i2c0_imux { |
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pinctrl-names = |
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"i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", |
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"idle"; |
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pinctrl-0 = <&i2cmux_s29>; |
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pinctrl-1 = <&i2cmux_s30>; |
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pinctrl-2 = <&i2cmux_s31>; |
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pinctrl-3 = <&i2cmux_s32>; |
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pinctrl-4 = <&i2cmux_pins_i>; |
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i2c_sfp1: i2c_sfp1 { |
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reg = <0x0>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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i2c_sfp2: i2c_sfp2 { |
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reg = <0x1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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i2c_sfp3: i2c_sfp3 { |
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reg = <0x2>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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i2c_sfp4: i2c_sfp4 { |
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reg = <0x3>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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&axi { |
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sfp_eth60: sfp-eth60 { |
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compatible = "sff,sfp"; |
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i2c-bus = <&i2c_sfp1>; |
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tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; |
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rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>; |
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los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; |
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mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; |
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tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; |
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}; |
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sfp_eth61: sfp-eth61 { |
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compatible = "sff,sfp"; |
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i2c-bus = <&i2c_sfp2>; |
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tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; |
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rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>; |
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los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; |
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mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; |
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tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; |
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}; |
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sfp_eth62: sfp-eth62 { |
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compatible = "sff,sfp"; |
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i2c-bus = <&i2c_sfp3>; |
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tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; |
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rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>; |
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los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; |
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mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; |
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tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; |
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}; |
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sfp_eth63: sfp-eth63 { |
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compatible = "sff,sfp"; |
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i2c-bus = <&i2c_sfp4>; |
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tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; |
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rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>; |
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los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; |
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mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; |
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tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; |
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}; |
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}; |
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&mdio0 { |
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status = "ok"; |
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phy0: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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phy1: ethernet-phy@1 { |
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reg = <1>; |
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}; |
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phy2: ethernet-phy@2 { |
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reg = <2>; |
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}; |
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phy3: ethernet-phy@3 { |
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reg = <3>; |
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}; |
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phy4: ethernet-phy@4 { |
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reg = <4>; |
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}; |
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phy5: ethernet-phy@5 { |
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reg = <5>; |
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}; |
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phy6: ethernet-phy@6 { |
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reg = <6>; |
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}; |
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phy7: ethernet-phy@7 { |
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reg = <7>; |
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}; |
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phy8: ethernet-phy@8 { |
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reg = <8>; |
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}; |
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phy9: ethernet-phy@9 { |
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reg = <9>; |
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}; |
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phy10: ethernet-phy@10 { |
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reg = <10>; |
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}; |
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phy11: ethernet-phy@11 { |
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reg = <11>; |
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}; |
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phy12: ethernet-phy@12 { |
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reg = <12>; |
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}; |
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phy13: ethernet-phy@13 { |
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reg = <13>; |
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}; |
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phy14: ethernet-phy@14 { |
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reg = <14>; |
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}; |
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phy15: ethernet-phy@15 { |
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reg = <15>; |
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}; |
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phy16: ethernet-phy@16 { |
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reg = <16>; |
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}; |
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phy17: ethernet-phy@17 { |
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reg = <17>; |
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}; |
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phy18: ethernet-phy@18 { |
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reg = <18>; |
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}; |
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phy19: ethernet-phy@19 { |
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reg = <19>; |
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}; |
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phy20: ethernet-phy@20 { |
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reg = <20>; |
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}; |
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phy21: ethernet-phy@21 { |
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reg = <21>; |
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}; |
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phy22: ethernet-phy@22 { |
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reg = <22>; |
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}; |
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phy23: ethernet-phy@23 { |
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reg = <23>; |
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}; |
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}; |
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&mdio1 { |
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status = "ok"; |
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phy24: ethernet-phy@24 { |
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reg = <0>; |
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}; |
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phy25: ethernet-phy@25 { |
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reg = <1>; |
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}; |
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phy26: ethernet-phy@26 { |
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reg = <2>; |
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}; |
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phy27: ethernet-phy@27 { |
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reg = <3>; |
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}; |
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phy28: ethernet-phy@28 { |
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reg = <4>; |
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}; |
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phy29: ethernet-phy@29 { |
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reg = <5>; |
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}; |
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phy30: ethernet-phy@30 { |
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reg = <6>; |
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}; |
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phy31: ethernet-phy@31 { |
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reg = <7>; |
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}; |
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phy32: ethernet-phy@32 { |
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reg = <8>; |
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}; |
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phy33: ethernet-phy@33 { |
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reg = <9>; |
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}; |
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phy34: ethernet-phy@34 { |
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reg = <10>; |
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}; |
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phy35: ethernet-phy@35 { |
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reg = <11>; |
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}; |
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phy36: ethernet-phy@36 { |
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reg = <12>; |
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}; |
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phy37: ethernet-phy@37 { |
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reg = <13>; |
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}; |
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phy38: ethernet-phy@38 { |
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reg = <14>; |
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}; |
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phy39: ethernet-phy@39 { |
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reg = <15>; |
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}; |
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phy40: ethernet-phy@40 { |
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reg = <16>; |
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}; |
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phy41: ethernet-phy@41 { |
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reg = <17>; |
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}; |
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phy42: ethernet-phy@42 { |
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reg = <18>; |
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}; |
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phy43: ethernet-phy@43 { |
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reg = <19>; |
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}; |
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phy44: ethernet-phy@44 { |
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reg = <20>; |
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}; |
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phy45: ethernet-phy@45 { |
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reg = <21>; |
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}; |
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phy46: ethernet-phy@46 { |
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reg = <22>; |
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}; |
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phy47: ethernet-phy@47 { |
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reg = <23>; |
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}; |
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}; |
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&mdio3 { |
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status = "ok"; |
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phy64: ethernet-phy@64 { |
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reg = <28>; |
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}; |
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}; |
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&switch { |
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ethernet-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port0: port@0 { |
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reg = <0>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 13>; |
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phy-handle = <&phy0>; |
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phy-mode = "qsgmii"; |
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}; |
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port1: port@1 { |
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reg = <1>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 13>; |
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phy-handle = <&phy1>; |
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phy-mode = "qsgmii"; |
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}; |
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port2: port@2 { |
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reg = <2>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 13>; |
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phy-handle = <&phy2>; |
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phy-mode = "qsgmii"; |
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}; |
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port3: port@3 { |
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reg = <3>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 13>; |
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phy-handle = <&phy3>; |
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phy-mode = "qsgmii"; |
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}; |
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port4: port@4 { |
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reg = <4>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 14>; |
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phy-handle = <&phy4>; |
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phy-mode = "qsgmii"; |
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}; |
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port5: port@5 { |
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reg = <5>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 14>; |
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phy-handle = <&phy5>; |
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phy-mode = "qsgmii"; |
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}; |
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port6: port@6 { |
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reg = <6>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 14>; |
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phy-handle = <&phy6>; |
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phy-mode = "qsgmii"; |
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}; |
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port7: port@7 { |
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reg = <7>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 14>; |
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phy-handle = <&phy7>; |
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phy-mode = "qsgmii"; |
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}; |
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port8: port@8 { |
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reg = <8>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 15>; |
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phy-handle = <&phy8>; |
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phy-mode = "qsgmii"; |
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}; |
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port9: port@9 { |
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reg = <9>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 15>; |
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phy-handle = <&phy9>; |
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phy-mode = "qsgmii"; |
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}; |
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port10: port@10 { |
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reg = <10>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 15>; |
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phy-handle = <&phy10>; |
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phy-mode = "qsgmii"; |
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}; |
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port11: port@11 { |
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reg = <11>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 15>; |
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phy-handle = <&phy11>; |
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phy-mode = "qsgmii"; |
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}; |
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port12: port@12 { |
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reg = <12>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 16>; |
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phy-handle = <&phy12>; |
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phy-mode = "qsgmii"; |
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}; |
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port13: port@13 { |
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reg = <13>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 16>; |
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phy-handle = <&phy13>; |
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phy-mode = "qsgmii"; |
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}; |
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port14: port@14 { |
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reg = <14>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 16>; |
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phy-handle = <&phy14>; |
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phy-mode = "qsgmii"; |
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}; |
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port15: port@15 { |
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reg = <15>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 16>; |
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phy-handle = <&phy15>; |
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phy-mode = "qsgmii"; |
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}; |
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port16: port@16 { |
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reg = <16>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 17>; |
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phy-handle = <&phy16>; |
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phy-mode = "qsgmii"; |
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}; |
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port17: port@17 { |
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reg = <17>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 17>; |
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phy-handle = <&phy17>; |
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phy-mode = "qsgmii"; |
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}; |
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port18: port@18 { |
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reg = <18>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 17>; |
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phy-handle = <&phy18>; |
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phy-mode = "qsgmii"; |
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}; |
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port19: port@19 { |
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reg = <19>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 17>; |
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phy-handle = <&phy19>; |
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phy-mode = "qsgmii"; |
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}; |
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port20: port@20 { |
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reg = <20>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 18>; |
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phy-handle = <&phy20>; |
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phy-mode = "qsgmii"; |
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}; |
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port21: port@21 { |
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reg = <21>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 18>; |
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phy-handle = <&phy21>; |
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phy-mode = "qsgmii"; |
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}; |
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port22: port@22 { |
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reg = <22>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 18>; |
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phy-handle = <&phy22>; |
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phy-mode = "qsgmii"; |
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}; |
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port23: port@23 { |
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reg = <23>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 18>; |
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phy-handle = <&phy23>; |
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phy-mode = "qsgmii"; |
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}; |
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port24: port@24 { |
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reg = <24>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 19>; |
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phy-handle = <&phy24>; |
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phy-mode = "qsgmii"; |
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}; |
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port25: port@25 { |
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reg = <25>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 19>; |
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phy-handle = <&phy25>; |
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phy-mode = "qsgmii"; |
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}; |
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port26: port@26 { |
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reg = <26>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 19>; |
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phy-handle = <&phy26>; |
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phy-mode = "qsgmii"; |
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}; |
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port27: port@27 { |
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reg = <27>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 19>; |
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phy-handle = <&phy27>; |
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phy-mode = "qsgmii"; |
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}; |
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port28: port@28 { |
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reg = <28>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 20>; |
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phy-handle = <&phy28>; |
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phy-mode = "qsgmii"; |
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}; |
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port29: port@29 { |
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reg = <29>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 20>; |
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phy-handle = <&phy29>; |
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phy-mode = "qsgmii"; |
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}; |
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port30: port@30 { |
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reg = <30>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 20>; |
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phy-handle = <&phy30>; |
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phy-mode = "qsgmii"; |
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}; |
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port31: port@31 { |
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reg = <31>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 20>; |
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phy-handle = <&phy31>; |
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phy-mode = "qsgmii"; |
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}; |
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port32: port@32 { |
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reg = <32>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 21>; |
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phy-handle = <&phy32>; |
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phy-mode = "qsgmii"; |
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}; |
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port33: port@33 { |
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reg = <33>; |
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microchip,bandwidth = <1000>; |
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phys = <&serdes 21>; |
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phy-handle = <&phy33>; |
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phy-mode = "qsgmii"; |
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}; |
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port34: port@34 { |
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reg = <34>; |
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microchip,bandwidth = <1000>; |
|
phys = <&serdes 21>; |
|
phy-handle = <&phy34>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port35: port@35 { |
|
reg = <35>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 21>; |
|
phy-handle = <&phy35>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port36: port@36 { |
|
reg = <36>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 22>; |
|
phy-handle = <&phy36>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port37: port@37 { |
|
reg = <37>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 22>; |
|
phy-handle = <&phy37>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port38: port@38 { |
|
reg = <38>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 22>; |
|
phy-handle = <&phy38>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port39: port@39 { |
|
reg = <39>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 22>; |
|
phy-handle = <&phy39>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port40: port@40 { |
|
reg = <40>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 23>; |
|
phy-handle = <&phy40>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port41: port@41 { |
|
reg = <41>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 23>; |
|
phy-handle = <&phy41>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port42: port@42 { |
|
reg = <42>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 23>; |
|
phy-handle = <&phy42>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port43: port@43 { |
|
reg = <43>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 23>; |
|
phy-handle = <&phy43>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port44: port@44 { |
|
reg = <44>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 24>; |
|
phy-handle = <&phy44>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port45: port@45 { |
|
reg = <45>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 24>; |
|
phy-handle = <&phy45>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port46: port@46 { |
|
reg = <46>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 24>; |
|
phy-handle = <&phy46>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
port47: port@47 { |
|
reg = <47>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 24>; |
|
phy-handle = <&phy47>; |
|
phy-mode = "qsgmii"; |
|
}; |
|
/* Then the 25G interfaces */ |
|
port60: port@60 { |
|
reg = <60>; |
|
microchip,bandwidth = <25000>; |
|
phys = <&serdes 29>; |
|
phy-mode = "10gbase-r"; |
|
sfp = <&sfp_eth60>; |
|
managed = "in-band-status"; |
|
}; |
|
port61: port@61 { |
|
reg = <61>; |
|
microchip,bandwidth = <25000>; |
|
phys = <&serdes 30>; |
|
phy-mode = "10gbase-r"; |
|
sfp = <&sfp_eth61>; |
|
managed = "in-band-status"; |
|
}; |
|
port62: port@62 { |
|
reg = <62>; |
|
microchip,bandwidth = <25000>; |
|
phys = <&serdes 31>; |
|
phy-mode = "10gbase-r"; |
|
sfp = <&sfp_eth62>; |
|
managed = "in-band-status"; |
|
}; |
|
port63: port@63 { |
|
reg = <63>; |
|
microchip,bandwidth = <25000>; |
|
phys = <&serdes 32>; |
|
phy-mode = "10gbase-r"; |
|
sfp = <&sfp_eth63>; |
|
managed = "in-band-status"; |
|
}; |
|
/* Finally the Management interface */ |
|
port64: port@64 { |
|
reg = <64>; |
|
microchip,bandwidth = <1000>; |
|
phys = <&serdes 0>; |
|
phy-handle = <&phy64>; |
|
phy-mode = "sgmii"; |
|
}; |
|
}; |
|
};
|
|
|