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182 lines
4.7 KiB
182 lines
4.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2020 MediaTek Inc. |
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* Copyright (c) 2020 BayLibre, SAS. |
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* Author: Fabien Parent <[email protected]> |
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*/ |
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#include <dt-bindings/clock/mt8167-clk.h> |
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#include <dt-bindings/memory/mt8167-larb-port.h> |
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#include <dt-bindings/power/mt8167-power.h> |
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#include "mt8167-pinfunc.h" |
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#include "mt8516.dtsi" |
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/ { |
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compatible = "mediatek,mt8167"; |
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soc { |
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topckgen: topckgen@10000000 { |
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compatible = "mediatek,mt8167-topckgen", "syscon"; |
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reg = <0 0x10000000 0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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infracfg: infracfg@10001000 { |
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compatible = "mediatek,mt8167-infracfg", "syscon"; |
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reg = <0 0x10001000 0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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apmixedsys: apmixedsys@10018000 { |
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compatible = "mediatek,mt8167-apmixedsys", "syscon"; |
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reg = <0 0x10018000 0 0x710>; |
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#clock-cells = <1>; |
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}; |
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scpsys: syscon@10006000 { |
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compatible = "syscon", "simple-mfd"; |
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reg = <0 0x10006000 0 0x1000>; |
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#power-domain-cells = <1>; |
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spm: power-controller { |
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compatible = "mediatek,mt8167-power-controller"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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#power-domain-cells = <1>; |
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/* power domains of the SoC */ |
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power-domain@MT8167_POWER_DOMAIN_MM { |
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reg = <MT8167_POWER_DOMAIN_MM>; |
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clocks = <&topckgen CLK_TOP_SMI_MM>; |
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clock-names = "mm"; |
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#power-domain-cells = <0>; |
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mediatek,infracfg = <&infracfg>; |
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}; |
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power-domain@MT8167_POWER_DOMAIN_VDEC { |
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reg = <MT8167_POWER_DOMAIN_VDEC>; |
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clocks = <&topckgen CLK_TOP_SMI_MM>, |
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<&topckgen CLK_TOP_RG_VDEC>; |
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clock-names = "mm", "vdec"; |
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#power-domain-cells = <0>; |
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}; |
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power-domain@MT8167_POWER_DOMAIN_ISP { |
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reg = <MT8167_POWER_DOMAIN_ISP>; |
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clocks = <&topckgen CLK_TOP_SMI_MM>; |
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clock-names = "mm"; |
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#power-domain-cells = <0>; |
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}; |
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power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { |
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reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>; |
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clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, |
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<&topckgen CLK_TOP_RG_SLOW_MFG>; |
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clock-names = "axi_mfg", "mfg"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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#power-domain-cells = <1>; |
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mediatek,infracfg = <&infracfg>; |
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power-domain@MT8167_POWER_DOMAIN_MFG_2D { |
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reg = <MT8167_POWER_DOMAIN_MFG_2D>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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#power-domain-cells = <1>; |
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power-domain@MT8167_POWER_DOMAIN_MFG { |
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reg = <MT8167_POWER_DOMAIN_MFG>; |
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#power-domain-cells = <0>; |
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mediatek,infracfg = <&infracfg>; |
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}; |
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}; |
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}; |
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power-domain@MT8167_POWER_DOMAIN_CONN { |
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reg = <MT8167_POWER_DOMAIN_CONN>; |
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#power-domain-cells = <0>; |
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mediatek,infracfg = <&infracfg>; |
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}; |
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}; |
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}; |
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imgsys: syscon@15000000 { |
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compatible = "mediatek,mt8167-imgsys", "syscon"; |
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reg = <0 0x15000000 0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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vdecsys: syscon@16000000 { |
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compatible = "mediatek,mt8167-vdecsys", "syscon"; |
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reg = <0 0x16000000 0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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pio: pinctrl@1000b000 { |
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compatible = "mediatek,mt8167-pinctrl"; |
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reg = <0 0x1000b000 0 0x1000>; |
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mediatek,pctl-regmap = <&syscfg_pctl>; |
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pins-are-numbered; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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mmsys: mmsys@14000000 { |
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compatible = "mediatek,mt8167-mmsys", "syscon"; |
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reg = <0 0x14000000 0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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smi_common: smi@14017000 { |
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compatible = "mediatek,mt8167-smi-common"; |
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reg = <0 0x14017000 0 0x1000>; |
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clocks = <&mmsys CLK_MM_SMI_COMMON>, |
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<&mmsys CLK_MM_SMI_COMMON>; |
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clock-names = "apb", "smi"; |
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power-domains = <&spm MT8167_POWER_DOMAIN_MM>; |
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}; |
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larb0: larb@14016000 { |
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compatible = "mediatek,mt8167-smi-larb"; |
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reg = <0 0x14016000 0 0x1000>; |
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mediatek,smi = <&smi_common>; |
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clocks = <&mmsys CLK_MM_SMI_LARB0>, |
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<&mmsys CLK_MM_SMI_LARB0>; |
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clock-names = "apb", "smi"; |
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power-domains = <&spm MT8167_POWER_DOMAIN_MM>; |
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}; |
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larb1: larb@15001000 { |
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compatible = "mediatek,mt8167-smi-larb"; |
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reg = <0 0x15001000 0 0x1000>; |
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mediatek,smi = <&smi_common>; |
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clocks = <&imgsys CLK_IMG_LARB1_SMI>, |
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<&imgsys CLK_IMG_LARB1_SMI>; |
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clock-names = "apb", "smi"; |
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power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; |
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}; |
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larb2: larb@16010000 { |
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compatible = "mediatek,mt8167-smi-larb"; |
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reg = <0 0x16010000 0 0x1000>; |
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mediatek,smi = <&smi_common>; |
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clocks = <&vdecsys CLK_VDEC_CKEN>, |
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<&vdecsys CLK_VDEC_LARB1_CKEN>; |
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clock-names = "apb", "smi"; |
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power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; |
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}; |
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iommu: m4u@10203000 { |
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compatible = "mediatek,mt8167-m4u"; |
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reg = <0 0x10203000 0 0x1000>; |
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mediatek,larbs = <&larb0 &larb1 &larb2>; |
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>; |
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#iommu-cells = <1>; |
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}; |
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}; |
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};
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