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206 lines
4.2 KiB
206 lines
4.2 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Copyright (C) 2020 Marvell International Ltd. |
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* |
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* Device tree for the CN9131-DB board. |
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*/ |
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#include "cn9130-db.dtsi" |
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/ { |
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compatible = "marvell,cn9131", "marvell,cn9130", |
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"marvell,armada-ap807-quad", "marvell,armada-ap807"; |
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aliases { |
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gpio3 = &cp1_gpio1; |
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gpio4 = &cp1_gpio2; |
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ethernet3 = &cp1_eth0; |
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ethernet4 = &cp1_eth1; |
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}; |
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cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { |
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compatible = "regulator-fixed"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cp1_xhci0_vbus_pins>; |
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regulator-name = "cp1-xhci0-vbus"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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enable-active-high; |
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gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>; |
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}; |
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cp1_usb3_0_phy0: cp1_usb3_phy0 { |
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compatible = "usb-nop-xceiv"; |
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vcc-supply = <&cp1_reg_usb3_vbus0>; |
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}; |
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cp1_sfp_eth1: sfp-eth1 { |
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compatible = "sff,sfp"; |
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i2c-bus = <&cp1_i2c0>; |
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los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; |
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mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; |
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tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>; |
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tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cp1_sfp_pins>; |
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/* |
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* SFP cages are unconnected on early PCBs because of an the I2C |
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* lanes not being connected. Prevent the port for being |
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* unusable by disabling the SFP node. |
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*/ |
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status = "disabled"; |
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}; |
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}; |
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/* |
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* Instantiate the first slave CP115 |
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*/ |
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#define CP11X_NAME cp1 |
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#define CP11X_BASE f4000000 |
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#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) |
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#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 |
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#define CP11X_PCIE0_BASE f4600000 |
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#define CP11X_PCIE1_BASE f4620000 |
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#define CP11X_PCIE2_BASE f4640000 |
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#include "armada-cp115.dtsi" |
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#undef CP11X_NAME |
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#undef CP11X_BASE |
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#undef CP11X_PCIEx_MEM_BASE |
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#undef CP11X_PCIEx_MEM_SIZE |
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#undef CP11X_PCIE0_BASE |
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#undef CP11X_PCIE1_BASE |
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#undef CP11X_PCIE2_BASE |
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&cp1_crypto { |
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status = "disabled"; |
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}; |
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&cp1_ethernet { |
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status = "okay"; |
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}; |
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/* CON50 */ |
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&cp1_eth0 { |
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status = "okay"; |
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phy-mode = "10gbase-r"; |
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/* Generic PHY, providing serdes lanes */ |
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phys = <&cp1_comphy4 0>; |
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managed = "in-band-status"; |
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sfp = <&cp1_sfp_eth1>; |
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}; |
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&cp1_gpio1 { |
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status = "okay"; |
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}; |
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&cp1_gpio2 { |
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status = "okay"; |
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}; |
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&cp1_i2c0 { |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cp1_i2c0_pins>; |
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clock-frequency = <100000>; |
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}; |
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/* CON40 */ |
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&cp1_pcie0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cp1_pcie_reset_pins>; |
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num-lanes = <2>; |
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num-viewport = <8>; |
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marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>; |
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status = "okay"; |
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/* Generic PHY, providing serdes lanes */ |
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phys = <&cp1_comphy0 0 |
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&cp1_comphy1 0>; |
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}; |
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&cp1_sata0 { |
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status = "okay"; |
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/* CON32 */ |
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sata-port@1 { |
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/* Generic PHY, providing serdes lanes */ |
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phys = <&cp1_comphy5 1>; |
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}; |
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}; |
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/* U24 */ |
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&cp1_spi1 { |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cp1_spi0_pins>; |
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reg = <0x700680 0x50>; |
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spi-flash@0 { |
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#address-cells = <0x1>; |
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#size-cells = <0x1>; |
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compatible = "jedec,spi-nor"; |
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reg = <0x0>; |
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/* On-board MUX does not allow higher frequencies */ |
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spi-max-frequency = <40000000>; |
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partitions { |
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compatible = "fixed-partitions"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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partition@0 { |
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label = "U-Boot-1"; |
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reg = <0x0 0x200000>; |
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}; |
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partition@400000 { |
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label = "Filesystem-1"; |
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reg = <0x200000 0xe00000>; |
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}; |
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}; |
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}; |
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}; |
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&cp1_syscon0 { |
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cp1_pinctrl: pinctrl { |
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compatible = "marvell,cp115-standalone-pinctrl"; |
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cp1_i2c0_pins: cp1-i2c-pins-0 { |
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marvell,pins = "mpp37", "mpp38"; |
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marvell,function = "i2c0"; |
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}; |
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cp1_spi0_pins: cp1-spi-pins-0 { |
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marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; |
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marvell,function = "spi1"; |
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}; |
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cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { |
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marvell,pins = "mpp3"; |
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marvell,function = "gpio"; |
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}; |
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cp1_sfp_pins: sfp-pins { |
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marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11"; |
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marvell,function = "gpio"; |
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}; |
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cp1_pcie_reset_pins: cp1-pcie-reset-pins { |
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marvell,pins = "mpp0"; |
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marvell,function = "gpio"; |
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}; |
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}; |
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}; |
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/* CON58 */ |
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&cp1_utmi { |
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status = "okay"; |
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}; |
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&cp1_usb3_1 { |
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status = "okay"; |
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usb-phy = <&cp1_usb3_0_phy0>; |
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/* Generic PHY, providing serdes lanes */ |
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phys = <&cp1_comphy3 1>, <&cp1_utmi1>; |
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phy-names = "usb", "utmi"; |
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dr_mode = "host"; |
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};
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