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864 lines
15 KiB
864 lines
15 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Device Tree file for CZ.NIC Turris Mox Board |
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* 2019 by Marek Behún <[email protected]> |
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*/ |
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/dts-v1/; |
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#include <dt-bindings/bus/moxtet.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/input/input.h> |
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#include "armada-372x.dtsi" |
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/ { |
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model = "CZ.NIC Turris Mox Board"; |
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compatible = "cznic,turris-mox", "marvell,armada3720", |
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"marvell,armada3710"; |
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aliases { |
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spi0 = &spi0; |
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ethernet1 = ð1; |
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mmc0 = &sdhci0; |
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mmc1 = &sdhci1; |
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}; |
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory@0 { |
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device_type = "memory"; |
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reg = <0x00000000 0x00000000 0x00000000 0x20000000>; |
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}; |
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leds { |
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compatible = "gpio-leds"; |
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red { |
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label = "mox:red:activity"; |
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gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; |
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linux,default-trigger = "default-on"; |
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}; |
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}; |
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gpio-keys { |
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compatible = "gpio-keys"; |
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reset { |
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label = "reset"; |
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linux,code = <KEY_RESTART>; |
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gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; |
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debounce-interval = <60>; |
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}; |
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}; |
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exp_usb3_vbus: usb3-vbus { |
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compatible = "regulator-fixed"; |
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regulator-name = "usb3-vbus"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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enable-active-high; |
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regulator-always-on; |
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gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; |
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}; |
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vsdc_reg: vsdc-reg { |
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compatible = "regulator-gpio"; |
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regulator-name = "vsdc"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; |
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gpios-states = <0>; |
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states = <1800000 0x1 |
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3300000 0x0>; |
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enable-active-high; |
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}; |
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vsdio_reg: vsdio-reg { |
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compatible = "regulator-gpio"; |
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regulator-name = "vsdio"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; |
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gpios-states = <0>; |
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states = <1800000 0x1 |
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3300000 0x0>; |
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enable-active-high; |
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}; |
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sdhci1_pwrseq: sdhci1-pwrseq { |
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compatible = "mmc-pwrseq-simple"; |
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reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; |
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status = "okay"; |
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}; |
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sfp: sfp { |
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compatible = "sff,sfp"; |
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i2c-bus = <&i2c0>; |
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los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; |
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tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; |
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mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; |
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tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; |
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rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; |
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maximum-power-milliwatt = <3000>; |
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/* enabled by U-Boot if SFP module is present */ |
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status = "disabled"; |
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}; |
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firmware { |
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armada-3700-rwtm { |
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compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; |
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}; |
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}; |
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}; |
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&i2c0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&i2c1_pins>; |
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clock-frequency = <100000>; |
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/delete-property/ mrvl,i2c-fast-mode; |
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status = "okay"; |
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rtc@6f { |
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compatible = "microchip,mcp7940x"; |
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reg = <0x6f>; |
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}; |
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}; |
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&pcie0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; |
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status = "okay"; |
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reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; |
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/* |
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* U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property |
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* contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and |
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* 2 size cells and also expects that the second range starts at 16 MB offset. If these |
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* conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address |
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* space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window |
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* for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. |
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* This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in |
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* U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): |
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* https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 |
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* https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf |
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* https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 |
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*/ |
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ |
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0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ |
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/* enabled by U-Boot if PCIe module is present */ |
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status = "disabled"; |
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}; |
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&uart0 { |
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status = "okay"; |
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}; |
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ð0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&rgmii_pins>; |
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phy-mode = "rgmii-id"; |
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phy-handle = <&phy1>; |
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status = "okay"; |
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}; |
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ð1 { |
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phy-mode = "2500base-x"; |
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managed = "in-band-status"; |
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phys = <&comphy0 1>; |
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}; |
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&sdhci0 { |
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wp-inverted; |
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bus-width = <4>; |
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cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; |
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vqmmc-supply = <&vsdc_reg>; |
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marvell,pad-type = "sd"; |
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status = "okay"; |
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}; |
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&sdhci1 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&sdio_pins>; |
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non-removable; |
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bus-width = <4>; |
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marvell,pad-type = "sd"; |
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vqmmc-supply = <&vsdio_reg>; |
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mmc-pwrseq = <&sdhci1_pwrseq>; |
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/* forbid SDR104 for FCC purposes */ |
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sdhci-caps-mask = <0x2 0x0>; |
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status = "okay"; |
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}; |
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&spi0 { |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; |
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assigned-clocks = <&nb_periph_clk 7>; |
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assigned-clock-parents = <&tbg 1>; |
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assigned-clock-rates = <20000000>; |
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spi-flash@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "jedec,spi-nor"; |
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reg = <0>; |
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spi-max-frequency = <20000000>; |
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partitions { |
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compatible = "fixed-partitions"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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partition@0 { |
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label = "secure-firmware"; |
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reg = <0x0 0x20000>; |
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}; |
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partition@20000 { |
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label = "a53-firmware"; |
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reg = <0x20000 0x160000>; |
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}; |
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partition@180000 { |
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label = "u-boot-env"; |
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reg = <0x180000 0x10000>; |
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}; |
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partition@190000 { |
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label = "Rescue system"; |
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reg = <0x190000 0x660000>; |
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}; |
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partition@7f0000 { |
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label = "dtb"; |
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reg = <0x7f0000 0x10000>; |
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}; |
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}; |
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}; |
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moxtet: moxtet@1 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "cznic,moxtet"; |
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reg = <1>; |
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reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; |
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spi-max-frequency = <10000000>; |
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spi-cpol; |
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spi-cpha; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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interrupt-parent = <&gpiosb>; |
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interrupts = <5 IRQ_TYPE_EDGE_FALLING>; |
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status = "okay"; |
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moxtet_sfp: gpio@0 { |
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compatible = "cznic,moxtet-gpio"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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reg = <0>; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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&usb2 { |
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status = "okay"; |
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}; |
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&comphy2 { |
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connector { |
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compatible = "usb-a-connector"; |
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phy-supply = <&exp_usb3_vbus>; |
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}; |
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}; |
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&usb3 { |
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status = "okay"; |
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phys = <&comphy2 0>; |
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}; |
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&mdio { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&smi_pins>; |
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status = "okay"; |
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phy1: ethernet-phy@1 { |
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reg = <1>; |
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}; |
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/* switch nodes are enabled by U-Boot if modules are present */ |
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switch0@10 { |
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compatible = "marvell,mv88e6190"; |
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reg = <0x10 0>; |
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dsa,member = <0 0>; |
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interrupt-parent = <&moxtet>; |
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interrupts = <MOXTET_IRQ_PERIDOT(0)>; |
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status = "disabled"; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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switch0phy1: switch0phy1@1 { |
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reg = <0x1>; |
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}; |
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switch0phy2: switch0phy2@2 { |
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reg = <0x2>; |
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}; |
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switch0phy3: switch0phy3@3 { |
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reg = <0x3>; |
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}; |
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switch0phy4: switch0phy4@4 { |
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reg = <0x4>; |
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}; |
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switch0phy5: switch0phy5@5 { |
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reg = <0x5>; |
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}; |
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switch0phy6: switch0phy6@6 { |
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reg = <0x6>; |
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}; |
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switch0phy7: switch0phy7@7 { |
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reg = <0x7>; |
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}; |
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switch0phy8: switch0phy8@8 { |
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reg = <0x8>; |
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}; |
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}; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@1 { |
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reg = <0x1>; |
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label = "lan1"; |
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phy-handle = <&switch0phy1>; |
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}; |
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port@2 { |
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reg = <0x2>; |
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label = "lan2"; |
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phy-handle = <&switch0phy2>; |
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}; |
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port@3 { |
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reg = <0x3>; |
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label = "lan3"; |
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phy-handle = <&switch0phy3>; |
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}; |
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port@4 { |
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reg = <0x4>; |
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label = "lan4"; |
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phy-handle = <&switch0phy4>; |
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}; |
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port@5 { |
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reg = <0x5>; |
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label = "lan5"; |
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phy-handle = <&switch0phy5>; |
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}; |
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port@6 { |
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reg = <0x6>; |
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label = "lan6"; |
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phy-handle = <&switch0phy6>; |
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}; |
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port@7 { |
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reg = <0x7>; |
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label = "lan7"; |
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phy-handle = <&switch0phy7>; |
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}; |
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port@8 { |
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reg = <0x8>; |
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label = "lan8"; |
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phy-handle = <&switch0phy8>; |
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}; |
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port@9 { |
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reg = <0x9>; |
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label = "cpu"; |
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ethernet = <ð1>; |
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phy-mode = "2500base-x"; |
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managed = "in-band-status"; |
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}; |
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switch0port10: port@a { |
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reg = <0xa>; |
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label = "dsa"; |
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phy-mode = "2500base-x"; |
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managed = "in-band-status"; |
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link = <&switch1port9 &switch2port9>; |
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status = "disabled"; |
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}; |
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port-sfp@a { |
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reg = <0xa>; |
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label = "sfp"; |
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sfp = <&sfp>; |
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phy-mode = "sgmii"; |
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managed = "in-band-status"; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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switch0@2 { |
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compatible = "marvell,mv88e6085"; |
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reg = <0x2 0>; |
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dsa,member = <0 0>; |
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interrupt-parent = <&moxtet>; |
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interrupts = <MOXTET_IRQ_TOPAZ>; |
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status = "disabled"; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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switch0phy1_topaz: switch0phy1@11 { |
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reg = <0x11>; |
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}; |
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switch0phy2_topaz: switch0phy2@12 { |
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reg = <0x12>; |
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}; |
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switch0phy3_topaz: switch0phy3@13 { |
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reg = <0x13>; |
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}; |
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switch0phy4_topaz: switch0phy4@14 { |
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reg = <0x14>; |
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}; |
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}; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@1 { |
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reg = <0x1>; |
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label = "lan1"; |
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phy-handle = <&switch0phy1_topaz>; |
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}; |
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port@2 { |
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reg = <0x2>; |
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label = "lan2"; |
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phy-handle = <&switch0phy2_topaz>; |
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}; |
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port@3 { |
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reg = <0x3>; |
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label = "lan3"; |
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phy-handle = <&switch0phy3_topaz>; |
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}; |
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port@4 { |
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reg = <0x4>; |
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label = "lan4"; |
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phy-handle = <&switch0phy4_topaz>; |
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}; |
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port@5 { |
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reg = <0x5>; |
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label = "cpu"; |
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phy-mode = "2500base-x"; |
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managed = "in-band-status"; |
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ethernet = <ð1>; |
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}; |
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}; |
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}; |
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switch1@11 { |
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compatible = "marvell,mv88e6190"; |
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reg = <0x11 0>; |
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dsa,member = <0 1>; |
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interrupt-parent = <&moxtet>; |
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interrupts = <MOXTET_IRQ_PERIDOT(1)>; |
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status = "disabled"; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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switch1phy1: switch1phy1@1 { |
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reg = <0x1>; |
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}; |
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switch1phy2: switch1phy2@2 { |
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reg = <0x2>; |
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}; |
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switch1phy3: switch1phy3@3 { |
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reg = <0x3>; |
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}; |
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switch1phy4: switch1phy4@4 { |
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reg = <0x4>; |
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}; |
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switch1phy5: switch1phy5@5 { |
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reg = <0x5>; |
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}; |
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switch1phy6: switch1phy6@6 { |
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reg = <0x6>; |
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}; |
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switch1phy7: switch1phy7@7 { |
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reg = <0x7>; |
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}; |
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switch1phy8: switch1phy8@8 { |
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reg = <0x8>; |
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}; |
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}; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@1 { |
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reg = <0x1>; |
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label = "lan9"; |
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phy-handle = <&switch1phy1>; |
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}; |
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port@2 { |
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reg = <0x2>; |
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label = "lan10"; |
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phy-handle = <&switch1phy2>; |
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}; |
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port@3 { |
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reg = <0x3>; |
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label = "lan11"; |
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phy-handle = <&switch1phy3>; |
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}; |
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port@4 { |
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reg = <0x4>; |
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label = "lan12"; |
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phy-handle = <&switch1phy4>; |
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}; |
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port@5 { |
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reg = <0x5>; |
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label = "lan13"; |
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phy-handle = <&switch1phy5>; |
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}; |
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port@6 { |
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reg = <0x6>; |
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label = "lan14"; |
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phy-handle = <&switch1phy6>; |
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}; |
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port@7 { |
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reg = <0x7>; |
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label = "lan15"; |
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phy-handle = <&switch1phy7>; |
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}; |
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port@8 { |
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reg = <0x8>; |
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label = "lan16"; |
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phy-handle = <&switch1phy8>; |
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}; |
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switch1port9: port@9 { |
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reg = <0x9>; |
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label = "dsa"; |
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phy-mode = "2500base-x"; |
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managed = "in-band-status"; |
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link = <&switch0port10>; |
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}; |
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switch1port10: port@a { |
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reg = <0xa>; |
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label = "dsa"; |
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phy-mode = "2500base-x"; |
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managed = "in-band-status"; |
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link = <&switch2port9>; |
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status = "disabled"; |
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}; |
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port-sfp@a { |
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reg = <0xa>; |
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label = "sfp"; |
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sfp = <&sfp>; |
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phy-mode = "sgmii"; |
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managed = "in-band-status"; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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switch1@2 { |
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compatible = "marvell,mv88e6085"; |
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reg = <0x2 0>; |
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dsa,member = <0 1>; |
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interrupt-parent = <&moxtet>; |
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interrupts = <MOXTET_IRQ_TOPAZ>; |
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status = "disabled"; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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switch1phy1_topaz: switch1phy1@11 { |
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reg = <0x11>; |
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}; |
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switch1phy2_topaz: switch1phy2@12 { |
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reg = <0x12>; |
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}; |
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switch1phy3_topaz: switch1phy3@13 { |
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reg = <0x13>; |
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}; |
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switch1phy4_topaz: switch1phy4@14 { |
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reg = <0x14>; |
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}; |
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}; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@1 { |
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reg = <0x1>; |
|
label = "lan9"; |
|
phy-handle = <&switch1phy1_topaz>; |
|
}; |
|
|
|
port@2 { |
|
reg = <0x2>; |
|
label = "lan10"; |
|
phy-handle = <&switch1phy2_topaz>; |
|
}; |
|
|
|
port@3 { |
|
reg = <0x3>; |
|
label = "lan11"; |
|
phy-handle = <&switch1phy3_topaz>; |
|
}; |
|
|
|
port@4 { |
|
reg = <0x4>; |
|
label = "lan12"; |
|
phy-handle = <&switch1phy4_topaz>; |
|
}; |
|
|
|
port@5 { |
|
reg = <0x5>; |
|
label = "dsa"; |
|
phy-mode = "2500base-x"; |
|
managed = "in-band-status"; |
|
link = <&switch0port10>; |
|
}; |
|
}; |
|
}; |
|
|
|
switch2@12 { |
|
compatible = "marvell,mv88e6190"; |
|
reg = <0x12 0>; |
|
dsa,member = <0 2>; |
|
interrupt-parent = <&moxtet>; |
|
interrupts = <MOXTET_IRQ_PERIDOT(2)>; |
|
status = "disabled"; |
|
|
|
mdio { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
switch2phy1: switch2phy1@1 { |
|
reg = <0x1>; |
|
}; |
|
|
|
switch2phy2: switch2phy2@2 { |
|
reg = <0x2>; |
|
}; |
|
|
|
switch2phy3: switch2phy3@3 { |
|
reg = <0x3>; |
|
}; |
|
|
|
switch2phy4: switch2phy4@4 { |
|
reg = <0x4>; |
|
}; |
|
|
|
switch2phy5: switch2phy5@5 { |
|
reg = <0x5>; |
|
}; |
|
|
|
switch2phy6: switch2phy6@6 { |
|
reg = <0x6>; |
|
}; |
|
|
|
switch2phy7: switch2phy7@7 { |
|
reg = <0x7>; |
|
}; |
|
|
|
switch2phy8: switch2phy8@8 { |
|
reg = <0x8>; |
|
}; |
|
}; |
|
|
|
ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@1 { |
|
reg = <0x1>; |
|
label = "lan17"; |
|
phy-handle = <&switch2phy1>; |
|
}; |
|
|
|
port@2 { |
|
reg = <0x2>; |
|
label = "lan18"; |
|
phy-handle = <&switch2phy2>; |
|
}; |
|
|
|
port@3 { |
|
reg = <0x3>; |
|
label = "lan19"; |
|
phy-handle = <&switch2phy3>; |
|
}; |
|
|
|
port@4 { |
|
reg = <0x4>; |
|
label = "lan20"; |
|
phy-handle = <&switch2phy4>; |
|
}; |
|
|
|
port@5 { |
|
reg = <0x5>; |
|
label = "lan21"; |
|
phy-handle = <&switch2phy5>; |
|
}; |
|
|
|
port@6 { |
|
reg = <0x6>; |
|
label = "lan22"; |
|
phy-handle = <&switch2phy6>; |
|
}; |
|
|
|
port@7 { |
|
reg = <0x7>; |
|
label = "lan23"; |
|
phy-handle = <&switch2phy7>; |
|
}; |
|
|
|
port@8 { |
|
reg = <0x8>; |
|
label = "lan24"; |
|
phy-handle = <&switch2phy8>; |
|
}; |
|
|
|
switch2port9: port@9 { |
|
reg = <0x9>; |
|
label = "dsa"; |
|
phy-mode = "2500base-x"; |
|
managed = "in-band-status"; |
|
link = <&switch1port10 &switch0port10>; |
|
}; |
|
|
|
port-sfp@a { |
|
reg = <0xa>; |
|
label = "sfp"; |
|
sfp = <&sfp>; |
|
phy-mode = "sgmii"; |
|
managed = "in-band-status"; |
|
status = "disabled"; |
|
}; |
|
}; |
|
}; |
|
|
|
switch2@2 { |
|
compatible = "marvell,mv88e6085"; |
|
reg = <0x2 0>; |
|
dsa,member = <0 2>; |
|
interrupt-parent = <&moxtet>; |
|
interrupts = <MOXTET_IRQ_TOPAZ>; |
|
status = "disabled"; |
|
|
|
mdio { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
switch2phy1_topaz: switch2phy1@11 { |
|
reg = <0x11>; |
|
}; |
|
|
|
switch2phy2_topaz: switch2phy2@12 { |
|
reg = <0x12>; |
|
}; |
|
|
|
switch2phy3_topaz: switch2phy3@13 { |
|
reg = <0x13>; |
|
}; |
|
|
|
switch2phy4_topaz: switch2phy4@14 { |
|
reg = <0x14>; |
|
}; |
|
}; |
|
|
|
ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@1 { |
|
reg = <0x1>; |
|
label = "lan17"; |
|
phy-handle = <&switch2phy1_topaz>; |
|
}; |
|
|
|
port@2 { |
|
reg = <0x2>; |
|
label = "lan18"; |
|
phy-handle = <&switch2phy2_topaz>; |
|
}; |
|
|
|
port@3 { |
|
reg = <0x3>; |
|
label = "lan19"; |
|
phy-handle = <&switch2phy3_topaz>; |
|
}; |
|
|
|
port@4 { |
|
reg = <0x4>; |
|
label = "lan20"; |
|
phy-handle = <&switch2phy4_topaz>; |
|
}; |
|
|
|
port@5 { |
|
reg = <0x5>; |
|
label = "dsa"; |
|
phy-mode = "2500base-x"; |
|
managed = "in-band-status"; |
|
link = <&switch1port10 &switch0port10>; |
|
}; |
|
}; |
|
}; |
|
};
|
|
|