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178 lines
3.5 KiB
178 lines
3.5 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2018-2019 NXP |
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* Dong Aisheng <[email protected]> |
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*/ |
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#include <dt-bindings/clock/imx8-lpcg.h> |
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#include <dt-bindings/firmware/imx/rsrc.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/pinctrl/pads-imx8qm.h> |
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/ { |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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aliases { |
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mmc0 = &usdhc1; |
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mmc1 = &usdhc2; |
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mmc2 = &usdhc3; |
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serial0 = &lpuart0; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&A53_0>; |
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}; |
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core1 { |
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cpu = <&A53_1>; |
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}; |
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core2 { |
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cpu = <&A53_2>; |
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}; |
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core3 { |
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cpu = <&A53_3>; |
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}; |
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}; |
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cluster1 { |
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core0 { |
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cpu = <&A72_0>; |
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}; |
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core1 { |
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cpu = <&A72_1>; |
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}; |
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}; |
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}; |
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A53_0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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next-level-cache = <&A53_L2>; |
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}; |
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A53_1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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next-level-cache = <&A53_L2>; |
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}; |
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A53_2: cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0x0 0x2>; |
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enable-method = "psci"; |
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next-level-cache = <&A53_L2>; |
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}; |
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A53_3: cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0x0 0x3>; |
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enable-method = "psci"; |
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next-level-cache = <&A53_L2>; |
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}; |
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A72_0: cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72", "arm,armv8"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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next-level-cache = <&A72_L2>; |
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}; |
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A72_1: cpu@101 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72", "arm,armv8"; |
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reg = <0x0 0x101>; |
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enable-method = "psci"; |
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next-level-cache = <&A72_L2>; |
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}; |
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A53_L2: l2-cache0 { |
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compatible = "cache"; |
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}; |
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A72_L2: l2-cache1 { |
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compatible = "cache"; |
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}; |
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}; |
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gic: interrupt-controller@51a00000 { |
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compatible = "arm,gic-v3"; |
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ |
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<0x0 0x51b00000 0 0xC0000>, /* GICR */ |
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<0x0 0x52000000 0 0x2000>, /* GICC */ |
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<0x0 0x52010000 0 0x1000>, /* GICH */ |
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<0x0 0x52020000 0 0x20000>; /* GICV */ |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-parent = <&gic>; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ |
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}; |
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scu { |
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compatible = "fsl,imx-scu"; |
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mbox-names = "tx0", |
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"rx0", |
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"gip3"; |
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mboxes = <&lsio_mu1 0 0 |
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&lsio_mu1 1 0 |
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&lsio_mu1 3 3>; |
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pd: imx8qx-pd { |
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compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; |
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#power-domain-cells = <1>; |
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}; |
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clk: clock-controller { |
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compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; |
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#clock-cells = <2>; |
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}; |
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iomuxc: pinctrl { |
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compatible = "fsl,imx8qm-iomuxc"; |
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}; |
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}; |
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/* sorted in register address */ |
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#include "imx8-ss-img.dtsi" |
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#include "imx8-ss-dma.dtsi" |
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#include "imx8-ss-conn.dtsi" |
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#include "imx8-ss-lsio.dtsi" |
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}; |
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#include "imx8qm-ss-img.dtsi" |
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#include "imx8qm-ss-dma.dtsi" |
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#include "imx8qm-ss-conn.dtsi" |
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#include "imx8qm-ss-lsio.dtsi"
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