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202 lines
5.8 KiB
202 lines
5.8 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2018-2019 NXP |
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* Dong Aisheng <[email protected]> |
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*/ |
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#include <dt-bindings/clock/imx8-lpcg.h> |
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#include <dt-bindings/firmware/imx/rsrc.h> |
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dma_subsys: bus@5a000000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; |
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dma_ipg_clk: clock-dma-ipg { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <120000000>; |
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clock-output-names = "dma_ipg_clk"; |
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}; |
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lpuart0: serial@5a060000 { |
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reg = <0x5a060000 0x1000>; |
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, |
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<&uart0_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "ipg", "baud"; |
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power-domains = <&pd IMX_SC_R_UART_0>; |
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status = "disabled"; |
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}; |
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lpuart1: serial@5a070000 { |
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reg = <0x5a070000 0x1000>; |
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, |
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<&uart1_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "ipg", "baud"; |
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power-domains = <&pd IMX_SC_R_UART_1>; |
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status = "disabled"; |
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}; |
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lpuart2: serial@5a080000 { |
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reg = <0x5a080000 0x1000>; |
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, |
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<&uart2_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "ipg", "baud"; |
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power-domains = <&pd IMX_SC_R_UART_2>; |
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status = "disabled"; |
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}; |
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lpuart3: serial@5a090000 { |
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reg = <0x5a090000 0x1000>; |
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, |
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<&uart3_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "ipg", "baud"; |
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power-domains = <&pd IMX_SC_R_UART_3>; |
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status = "disabled"; |
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}; |
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uart0_lpcg: clock-controller@5a460000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5a460000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, |
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<&dma_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; |
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clock-output-names = "uart0_lpcg_baud_clk", |
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"uart0_lpcg_ipg_clk"; |
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power-domains = <&pd IMX_SC_R_UART_0>; |
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}; |
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uart1_lpcg: clock-controller@5a470000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5a470000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, |
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<&dma_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; |
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clock-output-names = "uart1_lpcg_baud_clk", |
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"uart1_lpcg_ipg_clk"; |
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power-domains = <&pd IMX_SC_R_UART_1>; |
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}; |
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uart2_lpcg: clock-controller@5a480000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5a480000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, |
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<&dma_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; |
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clock-output-names = "uart2_lpcg_baud_clk", |
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"uart2_lpcg_ipg_clk"; |
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power-domains = <&pd IMX_SC_R_UART_2>; |
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}; |
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uart3_lpcg: clock-controller@5a490000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5a490000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, |
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<&dma_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; |
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clock-output-names = "uart3_lpcg_baud_clk", |
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"uart3_lpcg_ipg_clk"; |
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power-domains = <&pd IMX_SC_R_UART_3>; |
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}; |
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i2c0: i2c@5a800000 { |
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reg = <0x5a800000 0x4000>; |
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "per"; |
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assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; |
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assigned-clock-rates = <24000000>; |
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power-domains = <&pd IMX_SC_R_I2C_0>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@5a810000 { |
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reg = <0x5a810000 0x4000>; |
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "per"; |
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assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; |
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assigned-clock-rates = <24000000>; |
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power-domains = <&pd IMX_SC_R_I2C_1>; |
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status = "disabled"; |
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}; |
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i2c2: i2c@5a820000 { |
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reg = <0x5a820000 0x4000>; |
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "per"; |
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assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; |
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assigned-clock-rates = <24000000>; |
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power-domains = <&pd IMX_SC_R_I2C_2>; |
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status = "disabled"; |
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}; |
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i2c3: i2c@5a830000 { |
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reg = <0x5a830000 0x4000>; |
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "per"; |
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assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; |
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assigned-clock-rates = <24000000>; |
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power-domains = <&pd IMX_SC_R_I2C_3>; |
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status = "disabled"; |
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}; |
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i2c0_lpcg: clock-controller@5ac00000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5ac00000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, |
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<&dma_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; |
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clock-output-names = "i2c0_lpcg_clk", |
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"i2c0_lpcg_ipg_clk"; |
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power-domains = <&pd IMX_SC_R_I2C_0>; |
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}; |
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i2c1_lpcg: clock-controller@5ac10000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5ac10000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, |
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<&dma_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; |
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clock-output-names = "i2c1_lpcg_clk", |
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"i2c1_lpcg_ipg_clk"; |
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power-domains = <&pd IMX_SC_R_I2C_1>; |
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}; |
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i2c2_lpcg: clock-controller@5ac20000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5ac20000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, |
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<&dma_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; |
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clock-output-names = "i2c2_lpcg_clk", |
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"i2c2_lpcg_ipg_clk"; |
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power-domains = <&pd IMX_SC_R_I2C_2>; |
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}; |
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i2c3_lpcg: clock-controller@5ac30000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5ac30000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, |
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<&dma_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; |
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clock-output-names = "i2c3_lpcg_clk", |
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"i2c3_lpcg_ipg_clk"; |
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power-domains = <&pd IMX_SC_R_I2C_3>; |
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}; |
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};
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