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198 lines
5.9 KiB
198 lines
5.9 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2018-2019 NXP |
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* Dong Aisheng <[email protected]> |
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*/ |
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#include <dt-bindings/clock/imx8-lpcg.h> |
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#include <dt-bindings/firmware/imx/rsrc.h> |
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conn_subsys: bus@5b000000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; |
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conn_axi_clk: clock-conn-axi { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <333333333>; |
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clock-output-names = "conn_axi_clk"; |
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}; |
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conn_ahb_clk: clock-conn-ahb { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <166666666>; |
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clock-output-names = "conn_ahb_clk"; |
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}; |
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conn_ipg_clk: clock-conn-ipg { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <83333333>; |
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clock-output-names = "conn_ipg_clk"; |
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}; |
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usdhc1: mmc@5b010000 { |
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; |
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reg = <0x5b010000 0x10000>; |
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clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, |
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<&sdhc0_lpcg IMX_LPCG_CLK_5>, |
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<&sdhc0_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "ipg", "per", "ahb"; |
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power-domains = <&pd IMX_SC_R_SDHC_0>; |
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status = "disabled"; |
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}; |
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usdhc2: mmc@5b020000 { |
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; |
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reg = <0x5b020000 0x10000>; |
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clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, |
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<&sdhc1_lpcg IMX_LPCG_CLK_5>, |
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<&sdhc1_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "ipg", "per", "ahb"; |
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power-domains = <&pd IMX_SC_R_SDHC_1>; |
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fsl,tuning-start-tap = <20>; |
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fsl,tuning-step= <2>; |
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status = "disabled"; |
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}; |
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usdhc3: mmc@5b030000 { |
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; |
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reg = <0x5b030000 0x10000>; |
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clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, |
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<&sdhc2_lpcg IMX_LPCG_CLK_5>, |
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<&sdhc2_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "ipg", "per", "ahb"; |
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power-domains = <&pd IMX_SC_R_SDHC_2>; |
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status = "disabled"; |
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}; |
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fec1: ethernet@5b040000 { |
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reg = <0x5b040000 0x10000>; |
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, |
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<&enet0_lpcg IMX_LPCG_CLK_2>, |
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<&enet0_lpcg IMX_LPCG_CLK_3>, |
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<&enet0_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; |
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assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, |
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; |
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assigned-clock-rates = <250000000>, <125000000>; |
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fsl,num-tx-queues=<3>; |
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fsl,num-rx-queues=<3>; |
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power-domains = <&pd IMX_SC_R_ENET_0>; |
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status = "disabled"; |
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}; |
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fec2: ethernet@5b050000 { |
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reg = <0x5b050000 0x10000>; |
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, |
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<&enet1_lpcg IMX_LPCG_CLK_2>, |
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<&enet1_lpcg IMX_LPCG_CLK_3>, |
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<&enet1_lpcg IMX_LPCG_CLK_0>; |
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; |
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assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, |
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<&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; |
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assigned-clock-rates = <250000000>, <125000000>; |
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fsl,num-tx-queues=<3>; |
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fsl,num-rx-queues=<3>; |
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power-domains = <&pd IMX_SC_R_ENET_1>; |
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status = "disabled"; |
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}; |
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/* LPCG clocks */ |
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sdhc0_lpcg: clock-controller@5b200000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5b200000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, |
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<&conn_ipg_clk>, <&conn_axi_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, |
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<IMX_LPCG_CLK_5>; |
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clock-output-names = "sdhc0_lpcg_per_clk", |
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"sdhc0_lpcg_ipg_clk", |
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"sdhc0_lpcg_ahb_clk"; |
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power-domains = <&pd IMX_SC_R_SDHC_0>; |
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}; |
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sdhc1_lpcg: clock-controller@5b210000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5b210000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, |
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<&conn_ipg_clk>, <&conn_axi_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, |
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<IMX_LPCG_CLK_5>; |
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clock-output-names = "sdhc1_lpcg_per_clk", |
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"sdhc1_lpcg_ipg_clk", |
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"sdhc1_lpcg_ahb_clk"; |
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power-domains = <&pd IMX_SC_R_SDHC_1>; |
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}; |
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sdhc2_lpcg: clock-controller@5b220000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5b220000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, |
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<&conn_ipg_clk>, <&conn_axi_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, |
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<IMX_LPCG_CLK_5>; |
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clock-output-names = "sdhc2_lpcg_per_clk", |
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"sdhc2_lpcg_ipg_clk", |
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"sdhc2_lpcg_ahb_clk"; |
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power-domains = <&pd IMX_SC_R_SDHC_2>; |
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}; |
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enet0_lpcg: clock-controller@5b230000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5b230000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, |
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<&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, |
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<&conn_axi_clk>, |
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, |
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<&conn_ipg_clk>, |
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<&conn_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, |
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; |
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clock-output-names = "enet0_lpcg_timer_clk", |
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"enet0_lpcg_txc_sampling_clk", |
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"enet0_lpcg_ahb_clk", |
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"enet0_lpcg_rgmii_txc_clk", |
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"enet0_lpcg_ipg_clk", |
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"enet0_lpcg_ipg_s_clk"; |
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power-domains = <&pd IMX_SC_R_ENET_0>; |
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}; |
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enet1_lpcg: clock-controller@5b240000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5b240000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, |
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<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, |
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<&conn_axi_clk>, |
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<&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, |
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<&conn_ipg_clk>, |
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<&conn_ipg_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, |
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, |
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; |
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clock-output-names = "enet1_lpcg_timer_clk", |
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"enet1_lpcg_txc_sampling_clk", |
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"enet1_lpcg_ahb_clk", |
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"enet1_lpcg_rgmii_txc_clk", |
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"enet1_lpcg_ipg_clk", |
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"enet1_lpcg_ipg_s_clk"; |
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power-domains = <&pd IMX_SC_R_ENET_1>; |
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}; |
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};
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