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219 lines
3.7 KiB
219 lines
3.7 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Device Tree Include file for Freescale Layerscape-1043A family SoC. |
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* |
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* Copyright 2014-2015 Freescale Semiconductor, Inc. |
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* Copyright 2018 NXP |
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* |
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* Mingkai Hu <[email protected]> |
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*/ |
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/dts-v1/; |
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#include "fsl-ls1043a.dtsi" |
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/ { |
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model = "LS1043A RDB Board"; |
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compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; |
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aliases { |
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serial0 = &duart0; |
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serial1 = &duart1; |
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serial2 = &duart2; |
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serial3 = &duart3; |
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}; |
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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}; |
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&i2c0 { |
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status = "okay"; |
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ina220@40 { |
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compatible = "ti,ina220"; |
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reg = <0x40>; |
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shunt-resistor = <1000>; |
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}; |
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adt7461a@4c { |
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compatible = "adi,adt7461"; |
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reg = <0x4c>; |
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}; |
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eeprom@52 { |
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compatible = "atmel,24c512"; |
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reg = <0x52>; |
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}; |
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eeprom@53 { |
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compatible = "atmel,24c512"; |
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reg = <0x53>; |
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}; |
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rtc@68 { |
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compatible = "pericom,pt7c4338"; |
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reg = <0x68>; |
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}; |
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}; |
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&ifc { |
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status = "okay"; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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/* NOR, NAND Flashes and FPGA on board */ |
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ranges = <0x0 0x0 0x0 0x60000000 0x08000000 |
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0x1 0x0 0x0 0x7e800000 0x00010000 |
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0x2 0x0 0x0 0x7fb00000 0x00000100>; |
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nor@0,0 { |
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compatible = "cfi-flash"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x0 0x0 0x8000000>; |
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big-endian; |
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bank-width = <2>; |
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device-width = <1>; |
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}; |
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nand@1,0 { |
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compatible = "fsl,ifc-nand"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x1 0x0 0x10000>; |
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}; |
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cpld: board-control@2,0 { |
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compatible = "fsl,ls1043ardb-cpld"; |
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reg = <0x2 0x0 0x0000100>; |
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}; |
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}; |
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&dspi0 { |
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bus-num = <0>; |
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status = "okay"; |
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flash@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ |
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reg = <0>; |
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spi-max-frequency = <1000000>; /* input clock */ |
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}; |
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slic@2 { |
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compatible = "maxim,ds26522"; |
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reg = <2>; |
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spi-max-frequency = <2000000>; |
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fsl,spi-cs-sck-delay = <100>; |
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fsl,spi-sck-cs-delay = <50>; |
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}; |
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slic@3 { |
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compatible = "maxim,ds26522"; |
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reg = <3>; |
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spi-max-frequency = <2000000>; |
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fsl,spi-cs-sck-delay = <100>; |
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fsl,spi-sck-cs-delay = <50>; |
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}; |
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}; |
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&duart0 { |
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status = "okay"; |
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}; |
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&duart1 { |
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status = "okay"; |
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}; |
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#include "fsl-ls1043-post.dtsi" |
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&fman0 { |
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ethernet@e0000 { |
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phy-handle = <&qsgmii_phy1>; |
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phy-connection-type = "qsgmii"; |
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}; |
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ethernet@e2000 { |
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phy-handle = <&qsgmii_phy2>; |
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phy-connection-type = "qsgmii"; |
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}; |
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ethernet@e4000 { |
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phy-handle = <&rgmii_phy1>; |
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phy-connection-type = "rgmii-id"; |
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}; |
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ethernet@e6000 { |
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phy-handle = <&rgmii_phy2>; |
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phy-connection-type = "rgmii-id"; |
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}; |
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ethernet@e8000 { |
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phy-handle = <&qsgmii_phy3>; |
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phy-connection-type = "qsgmii"; |
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}; |
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ethernet@ea000 { |
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phy-handle = <&qsgmii_phy4>; |
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phy-connection-type = "qsgmii"; |
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}; |
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ethernet@f0000 { /* 10GEC1 */ |
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phy-handle = <&aqr105_phy>; |
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phy-connection-type = "xgmii"; |
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}; |
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mdio@fc000 { |
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rgmii_phy1: ethernet-phy@1 { |
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reg = <0x1>; |
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}; |
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rgmii_phy2: ethernet-phy@2 { |
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reg = <0x2>; |
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}; |
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qsgmii_phy1: ethernet-phy@4 { |
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reg = <0x4>; |
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}; |
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qsgmii_phy2: ethernet-phy@5 { |
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reg = <0x5>; |
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}; |
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qsgmii_phy3: ethernet-phy@6 { |
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reg = <0x6>; |
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}; |
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qsgmii_phy4: ethernet-phy@7 { |
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reg = <0x7>; |
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}; |
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}; |
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mdio@fd000 { |
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aqr105_phy: ethernet-phy@1 { |
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compatible = "ethernet-phy-ieee802.3-c45"; |
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interrupts = <0 132 4>; |
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reg = <0x1>; |
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}; |
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}; |
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}; |
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&uqe { |
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ucc_hdlc: ucc@2000 { |
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compatible = "fsl,ucc-hdlc"; |
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rx-clock-name = "clk8"; |
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tx-clock-name = "clk9"; |
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fsl,rx-sync-clock = "rsync_pin"; |
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fsl,tx-sync-clock = "tsync_pin"; |
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fsl,tx-timeslot-mask = <0xfffffffe>; |
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fsl,rx-timeslot-mask = <0xfffffffe>; |
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fsl,tdm-framer-type = "e1"; |
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fsl,tdm-id = <0>; |
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fsl,siram-entry-id = <0>; |
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fsl,tdm-interface; |
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}; |
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}; |
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&usb0 { |
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status = "okay"; |
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}; |
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&usb1 { |
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status = "okay"; |
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};
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