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925 lines
17 KiB
925 lines
17 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Copyright (c) 2016 Endless Computers, Inc. |
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* Author: Carlo Caione <[email protected]> |
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*/ |
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|
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#include "meson-gx.dtsi" |
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#include <dt-bindings/clock/gxbb-clkc.h> |
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#include <dt-bindings/clock/gxbb-aoclkc.h> |
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#include <dt-bindings/gpio/meson-gxl-gpio.h> |
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#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> |
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/ { |
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compatible = "amlogic,meson-gxl"; |
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soc { |
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usb: usb@d0078080 { |
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compatible = "amlogic,meson-gxl-usb-ctrl"; |
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reg = <0x0 0xd0078080 0x0 0x20>; |
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; |
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clock-names = "usb_ctrl", "ddr"; |
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resets = <&reset RESET_USB_OTG>; |
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dr_mode = "otg"; |
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phys = <&usb2_phy0>, <&usb2_phy1>; |
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phy-names = "usb2-phy0", "usb2-phy1"; |
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dwc2: usb@c9100000 { |
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compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; |
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reg = <0x0 0xc9100000 0x0 0x40000>; |
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clkc CLKID_USB1>; |
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clock-names = "otg"; |
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phys = <&usb2_phy1>; |
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dr_mode = "peripheral"; |
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g-rx-fifo-size = <192>; |
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g-np-tx-fifo-size = <128>; |
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g-tx-fifo-size = <128 128 16 16 16>; |
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}; |
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dwc3: usb@c9000000 { |
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compatible = "snps,dwc3"; |
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reg = <0x0 0xc9000000 0x0 0x100000>; |
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
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dr_mode = "host"; |
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maximum-speed = "high-speed"; |
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snps,dis_u2_susphy_quirk; |
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}; |
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}; |
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acodec: audio-controller@c8832000 { |
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compatible = "amlogic,t9015"; |
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reg = <0x0 0xc8832000 0x0 0x14>; |
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#sound-dai-cells = <0>; |
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sound-name-prefix = "ACODEC"; |
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clocks = <&clkc CLKID_ACODEC>; |
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clock-names = "pclk"; |
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resets = <&reset RESET_ACODEC>; |
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status = "disabled"; |
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}; |
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crypto: crypto@c883e000 { |
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compatible = "amlogic,gxl-crypto"; |
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reg = <0x0 0xc883e000 0x0 0x36>; |
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interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; |
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clocks = <&clkc CLKID_BLKMV>; |
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clock-names = "blkmv"; |
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status = "okay"; |
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}; |
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}; |
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}; |
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&aiu { |
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compatible = "amlogic,aiu-gxl", "amlogic,aiu"; |
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clocks = <&clkc CLKID_AIU_GLUE>, |
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<&clkc CLKID_I2S_OUT>, |
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<&clkc CLKID_AOCLK_GATE>, |
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<&clkc CLKID_CTS_AMCLK>, |
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<&clkc CLKID_MIXER_IFACE>, |
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<&clkc CLKID_IEC958>, |
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<&clkc CLKID_IEC958_GATE>, |
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<&clkc CLKID_CTS_MCLK_I958>, |
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<&clkc CLKID_CTS_I958>; |
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clock-names = "pclk", |
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"i2s_pclk", |
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"i2s_aoclk", |
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"i2s_mclk", |
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"i2s_mixer", |
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"spdif_pclk", |
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"spdif_aoclk", |
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"spdif_mclk", |
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"spdif_mclk_sel"; |
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resets = <&reset RESET_AIU>; |
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}; |
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&apb { |
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usb2_phy0: phy@78000 { |
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compatible = "amlogic,meson-gxl-usb2-phy"; |
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#phy-cells = <0>; |
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reg = <0x0 0x78000 0x0 0x20>; |
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clocks = <&clkc CLKID_USB>; |
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clock-names = "phy"; |
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resets = <&reset RESET_USB_OTG>; |
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reset-names = "phy"; |
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status = "okay"; |
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}; |
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usb2_phy1: phy@78020 { |
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compatible = "amlogic,meson-gxl-usb2-phy"; |
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#phy-cells = <0>; |
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reg = <0x0 0x78020 0x0 0x20>; |
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clocks = <&clkc CLKID_USB>; |
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clock-names = "phy"; |
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resets = <&reset RESET_USB_OTG>; |
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reset-names = "phy"; |
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status = "okay"; |
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}; |
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}; |
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&efuse { |
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clocks = <&clkc CLKID_EFUSE>; |
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}; |
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ðmac { |
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clocks = <&clkc CLKID_ETH>, |
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<&clkc CLKID_FCLK_DIV2>, |
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<&clkc CLKID_MPLL2>, |
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<&clkc CLKID_FCLK_DIV2>; |
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clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; |
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mdio0: mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dwmac-mdio"; |
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}; |
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}; |
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&aobus { |
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pinctrl_aobus: pinctrl@14 { |
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compatible = "amlogic,meson-gxl-aobus-pinctrl"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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gpio_ao: bank@14 { |
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reg = <0x0 0x00014 0x0 0x8>, |
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<0x0 0x0002c 0x0 0x4>, |
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<0x0 0x00024 0x0 0x8>; |
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reg-names = "mux", "pull", "gpio"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pinctrl_aobus 0 0 14>; |
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}; |
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uart_ao_a_pins: uart_ao_a { |
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mux { |
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groups = "uart_tx_ao_a", "uart_rx_ao_a"; |
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function = "uart_ao"; |
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bias-disable; |
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}; |
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}; |
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uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { |
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mux { |
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groups = "uart_cts_ao_a", |
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"uart_rts_ao_a"; |
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function = "uart_ao"; |
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bias-disable; |
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}; |
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}; |
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uart_ao_b_pins: uart_ao_b { |
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mux { |
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groups = "uart_tx_ao_b", "uart_rx_ao_b"; |
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function = "uart_ao_b"; |
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bias-disable; |
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}; |
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}; |
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uart_ao_b_0_1_pins: uart_ao_b_0_1 { |
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mux { |
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groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; |
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function = "uart_ao_b"; |
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bias-disable; |
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}; |
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}; |
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uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { |
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mux { |
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groups = "uart_cts_ao_b", |
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"uart_rts_ao_b"; |
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function = "uart_ao_b"; |
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bias-disable; |
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}; |
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}; |
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remote_input_ao_pins: remote_input_ao { |
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mux { |
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groups = "remote_input_ao"; |
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function = "remote_input_ao"; |
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bias-disable; |
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}; |
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}; |
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i2c_ao_pins: i2c_ao { |
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mux { |
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groups = "i2c_sck_ao", |
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"i2c_sda_ao"; |
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function = "i2c_ao"; |
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bias-disable; |
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}; |
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}; |
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pwm_ao_a_3_pins: pwm_ao_a_3 { |
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mux { |
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groups = "pwm_ao_a_3"; |
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function = "pwm_ao_a"; |
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bias-disable; |
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}; |
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}; |
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pwm_ao_a_8_pins: pwm_ao_a_8 { |
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mux { |
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groups = "pwm_ao_a_8"; |
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function = "pwm_ao_a"; |
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bias-disable; |
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}; |
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}; |
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pwm_ao_b_pins: pwm_ao_b { |
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mux { |
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groups = "pwm_ao_b"; |
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function = "pwm_ao_b"; |
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bias-disable; |
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}; |
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}; |
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pwm_ao_b_6_pins: pwm_ao_b_6 { |
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mux { |
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groups = "pwm_ao_b_6"; |
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function = "pwm_ao_b"; |
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bias-disable; |
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}; |
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}; |
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i2s_out_ch23_ao_pins: i2s_out_ch23_ao { |
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mux { |
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groups = "i2s_out_ch23_ao"; |
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function = "i2s_out_ao"; |
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bias-disable; |
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}; |
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}; |
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i2s_out_ch45_ao_pins: i2s_out_ch45_ao { |
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mux { |
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groups = "i2s_out_ch45_ao"; |
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function = "i2s_out_ao"; |
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bias-disable; |
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}; |
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}; |
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spdif_out_ao_6_pins: spdif_out_ao_6 { |
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mux { |
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groups = "spdif_out_ao_6"; |
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function = "spdif_out_ao"; |
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bias-disable; |
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}; |
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}; |
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spdif_out_ao_9_pins: spdif_out_ao_9 { |
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mux { |
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groups = "spdif_out_ao_9"; |
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function = "spdif_out_ao"; |
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bias-disable; |
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}; |
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}; |
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ao_cec_pins: ao_cec { |
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mux { |
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groups = "ao_cec"; |
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function = "cec_ao"; |
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bias-disable; |
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}; |
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}; |
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ee_cec_pins: ee_cec { |
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mux { |
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groups = "ee_cec"; |
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function = "cec_ao"; |
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bias-disable; |
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}; |
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}; |
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}; |
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}; |
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&cec_AO { |
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clocks = <&clkc_AO CLKID_AO_CEC_32K>; |
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clock-names = "core"; |
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}; |
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&clkc_AO { |
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compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; |
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clocks = <&xtal>, <&clkc CLKID_CLK81>; |
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clock-names = "xtal", "mpeg-clk"; |
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}; |
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&gpio_intc { |
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compatible = "amlogic,meson-gpio-intc", |
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"amlogic,meson-gxl-gpio-intc"; |
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status = "okay"; |
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}; |
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&hdmi_tx { |
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compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; |
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resets = <&reset RESET_HDMITX_CAPB3>, |
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<&reset RESET_HDMI_SYSTEM_RESET>, |
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<&reset RESET_HDMI_TX>; |
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reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; |
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clocks = <&clkc CLKID_HDMI_PCLK>, |
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<&clkc CLKID_CLK81>, |
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<&clkc CLKID_GCLK_VENCI_INT0>; |
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clock-names = "isfr", "iahb", "venci"; |
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}; |
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&sysctrl { |
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clkc: clock-controller { |
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compatible = "amlogic,gxl-clkc"; |
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#clock-cells = <1>; |
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clocks = <&xtal>; |
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clock-names = "xtal"; |
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}; |
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}; |
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&hwrng { |
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clocks = <&clkc CLKID_RNG0>; |
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clock-names = "core"; |
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}; |
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&i2c_A { |
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clocks = <&clkc CLKID_I2C>; |
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}; |
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&i2c_AO { |
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clocks = <&clkc CLKID_AO_I2C>; |
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}; |
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&i2c_B { |
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clocks = <&clkc CLKID_I2C>; |
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}; |
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&i2c_C { |
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clocks = <&clkc CLKID_I2C>; |
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}; |
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&periphs { |
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pinctrl_periphs: pinctrl@4b0 { |
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compatible = "amlogic,meson-gxl-periphs-pinctrl"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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gpio: bank@4b0 { |
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reg = <0x0 0x004b0 0x0 0x28>, |
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<0x0 0x004e8 0x0 0x14>, |
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<0x0 0x00520 0x0 0x14>, |
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<0x0 0x00430 0x0 0x40>; |
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reg-names = "mux", "pull", "pull-enable", "gpio"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pinctrl_periphs 0 0 100>; |
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}; |
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emmc_pins: emmc { |
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mux-0 { |
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groups = "emmc_nand_d07", |
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"emmc_cmd"; |
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function = "emmc"; |
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bias-pull-up; |
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}; |
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mux-1 { |
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groups = "emmc_clk"; |
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function = "emmc"; |
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bias-disable; |
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}; |
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}; |
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emmc_ds_pins: emmc-ds { |
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mux { |
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groups = "emmc_ds"; |
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function = "emmc"; |
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bias-pull-down; |
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}; |
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}; |
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emmc_clk_gate_pins: emmc_clk_gate { |
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mux { |
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groups = "BOOT_8"; |
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function = "gpio_periphs"; |
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bias-pull-down; |
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}; |
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}; |
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nor_pins: nor { |
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mux { |
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groups = "nor_d", |
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"nor_q", |
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"nor_c", |
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"nor_cs"; |
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function = "nor"; |
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bias-disable; |
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}; |
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}; |
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spi_pins: spi-pins { |
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mux { |
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groups = "spi_miso", |
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"spi_mosi", |
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"spi_sclk"; |
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function = "spi"; |
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bias-disable; |
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}; |
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}; |
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spi_ss0_pins: spi-ss0 { |
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mux { |
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groups = "spi_ss0"; |
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function = "spi"; |
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bias-disable; |
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}; |
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}; |
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sdcard_pins: sdcard { |
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mux-0 { |
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groups = "sdcard_d0", |
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"sdcard_d1", |
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"sdcard_d2", |
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"sdcard_d3", |
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"sdcard_cmd"; |
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function = "sdcard"; |
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bias-pull-up; |
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}; |
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mux-1 { |
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groups = "sdcard_clk"; |
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function = "sdcard"; |
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bias-disable; |
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}; |
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}; |
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sdcard_clk_gate_pins: sdcard_clk_gate { |
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mux { |
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groups = "CARD_2"; |
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function = "gpio_periphs"; |
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bias-pull-down; |
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}; |
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}; |
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sdio_pins: sdio { |
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mux-0 { |
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groups = "sdio_d0", |
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"sdio_d1", |
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"sdio_d2", |
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"sdio_d3", |
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"sdio_cmd"; |
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function = "sdio"; |
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bias-pull-up; |
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}; |
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mux-1 { |
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groups = "sdio_clk"; |
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function = "sdio"; |
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bias-disable; |
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}; |
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}; |
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sdio_clk_gate_pins: sdio_clk_gate { |
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mux { |
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groups = "GPIOX_4"; |
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function = "gpio_periphs"; |
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bias-pull-down; |
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}; |
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}; |
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sdio_irq_pins: sdio_irq { |
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mux { |
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groups = "sdio_irq"; |
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function = "sdio"; |
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bias-disable; |
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}; |
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}; |
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uart_a_pins: uart_a { |
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mux { |
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groups = "uart_tx_a", |
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"uart_rx_a"; |
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function = "uart_a"; |
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bias-disable; |
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}; |
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}; |
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uart_a_cts_rts_pins: uart_a_cts_rts { |
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mux { |
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groups = "uart_cts_a", |
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"uart_rts_a"; |
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function = "uart_a"; |
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bias-disable; |
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}; |
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}; |
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uart_b_pins: uart_b { |
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mux { |
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groups = "uart_tx_b", |
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"uart_rx_b"; |
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function = "uart_b"; |
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bias-disable; |
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}; |
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}; |
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uart_b_cts_rts_pins: uart_b_cts_rts { |
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mux { |
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groups = "uart_cts_b", |
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"uart_rts_b"; |
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function = "uart_b"; |
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bias-disable; |
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}; |
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}; |
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uart_c_pins: uart_c { |
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mux { |
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groups = "uart_tx_c", |
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"uart_rx_c"; |
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function = "uart_c"; |
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bias-disable; |
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}; |
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}; |
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uart_c_cts_rts_pins: uart_c_cts_rts { |
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mux { |
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groups = "uart_cts_c", |
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"uart_rts_c"; |
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function = "uart_c"; |
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bias-disable; |
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}; |
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}; |
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i2c_a_pins: i2c_a { |
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mux { |
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groups = "i2c_sck_a", |
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"i2c_sda_a"; |
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function = "i2c_a"; |
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bias-disable; |
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}; |
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}; |
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i2c_b_pins: i2c_b { |
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mux { |
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groups = "i2c_sck_b", |
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"i2c_sda_b"; |
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function = "i2c_b"; |
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bias-disable; |
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}; |
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}; |
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i2c_c_pins: i2c_c { |
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mux { |
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groups = "i2c_sck_c", |
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"i2c_sda_c"; |
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function = "i2c_c"; |
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bias-disable; |
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}; |
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}; |
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i2c_c_dv18_pins: i2c_c_dv18 { |
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mux { |
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groups = "i2c_sck_c_dv19", |
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"i2c_sda_c_dv18"; |
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function = "i2c_c"; |
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bias-disable; |
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}; |
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}; |
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eth_pins: eth_c { |
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mux { |
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groups = "eth_mdio", |
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"eth_mdc", |
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"eth_clk_rx_clk", |
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"eth_rx_dv", |
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"eth_rxd0", |
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"eth_rxd1", |
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"eth_rxd2", |
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"eth_rxd3", |
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"eth_rgmii_tx_clk", |
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"eth_tx_en", |
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"eth_txd0", |
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"eth_txd1", |
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"eth_txd2", |
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"eth_txd3"; |
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function = "eth"; |
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bias-disable; |
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}; |
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}; |
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eth_link_led_pins: eth_link_led { |
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mux { |
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groups = "eth_link_led"; |
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function = "eth_led"; |
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bias-disable; |
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}; |
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}; |
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eth_act_led_pins: eth_act_led { |
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mux { |
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groups = "eth_act_led"; |
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function = "eth_led"; |
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}; |
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}; |
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pwm_a_pins: pwm_a { |
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mux { |
|
groups = "pwm_a"; |
|
function = "pwm_a"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
pwm_b_pins: pwm_b { |
|
mux { |
|
groups = "pwm_b"; |
|
function = "pwm_b"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
pwm_c_pins: pwm_c { |
|
mux { |
|
groups = "pwm_c"; |
|
function = "pwm_c"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
pwm_d_pins: pwm_d { |
|
mux { |
|
groups = "pwm_d"; |
|
function = "pwm_d"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
pwm_e_pins: pwm_e { |
|
mux { |
|
groups = "pwm_e"; |
|
function = "pwm_e"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
pwm_f_clk_pins: pwm_f_clk { |
|
mux { |
|
groups = "pwm_f_clk"; |
|
function = "pwm_f"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
pwm_f_x_pins: pwm_f_x { |
|
mux { |
|
groups = "pwm_f_x"; |
|
function = "pwm_f"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
hdmi_hpd_pins: hdmi_hpd { |
|
mux { |
|
groups = "hdmi_hpd"; |
|
function = "hdmi_hpd"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
hdmi_i2c_pins: hdmi_i2c { |
|
mux { |
|
groups = "hdmi_sda", "hdmi_scl"; |
|
function = "hdmi_i2c"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
i2s_am_clk_pins: i2s_am_clk { |
|
mux { |
|
groups = "i2s_am_clk"; |
|
function = "i2s_out"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
i2s_out_ao_clk_pins: i2s_out_ao_clk { |
|
mux { |
|
groups = "i2s_out_ao_clk"; |
|
function = "i2s_out"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
i2s_out_lr_clk_pins: i2s_out_lr_clk { |
|
mux { |
|
groups = "i2s_out_lr_clk"; |
|
function = "i2s_out"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
i2s_out_ch01_pins: i2s_out_ch01 { |
|
mux { |
|
groups = "i2s_out_ch01"; |
|
function = "i2s_out"; |
|
bias-disable; |
|
}; |
|
}; |
|
i2sout_ch23_z_pins: i2sout_ch23_z { |
|
mux { |
|
groups = "i2sout_ch23_z"; |
|
function = "i2s_out"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
i2sout_ch45_z_pins: i2sout_ch45_z { |
|
mux { |
|
groups = "i2sout_ch45_z"; |
|
function = "i2s_out"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
i2sout_ch67_z_pins: i2sout_ch67_z { |
|
mux { |
|
groups = "i2sout_ch67_z"; |
|
function = "i2s_out"; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
spdif_out_h_pins: spdif_out_ao_h { |
|
mux { |
|
groups = "spdif_out_h"; |
|
function = "spdif_out"; |
|
bias-disable; |
|
}; |
|
}; |
|
}; |
|
|
|
eth-phy-mux { |
|
compatible = "mdio-mux-mmioreg", "mdio-mux"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
reg = <0x0 0x55c 0x0 0x4>; |
|
mux-mask = <0xffffffff>; |
|
mdio-parent-bus = <&mdio0>; |
|
|
|
internal_mdio: mdio@e40908ff { |
|
reg = <0xe40908ff>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
internal_phy: ethernet-phy@8 { |
|
compatible = "ethernet-phy-id0181.4400"; |
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <8>; |
|
max-speed = <100>; |
|
}; |
|
}; |
|
|
|
external_mdio: mdio@2009087f { |
|
reg = <0x2009087f>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
}; |
|
}; |
|
}; |
|
|
|
&pwrc { |
|
resets = <&reset RESET_VIU>, |
|
<&reset RESET_VENC>, |
|
<&reset RESET_VCBUS>, |
|
<&reset RESET_BT656>, |
|
<&reset RESET_DVIN_RESET>, |
|
<&reset RESET_RDMA>, |
|
<&reset RESET_VENCI>, |
|
<&reset RESET_VENCP>, |
|
<&reset RESET_VDAC>, |
|
<&reset RESET_VDI6>, |
|
<&reset RESET_VENCL>, |
|
<&reset RESET_VID_LOCK>; |
|
reset-names = "viu", "venc", "vcbus", "bt656", |
|
"dvin", "rdma", "venci", "vencp", |
|
"vdac", "vdi6", "vencl", "vid_lock"; |
|
clocks = <&clkc CLKID_VPU>, |
|
<&clkc CLKID_VAPB>; |
|
clock-names = "vpu", "vapb"; |
|
/* |
|
* VPU clocking is provided by two identical clock paths |
|
* VPU_0 and VPU_1 muxed to a single clock by a glitch |
|
* free mux to safely change frequency while running. |
|
* Same for VAPB but with a final gate after the glitch free mux. |
|
*/ |
|
assigned-clocks = <&clkc CLKID_VPU_0_SEL>, |
|
<&clkc CLKID_VPU_0>, |
|
<&clkc CLKID_VPU>, /* Glitch free mux */ |
|
<&clkc CLKID_VAPB_0_SEL>, |
|
<&clkc CLKID_VAPB_0>, |
|
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ |
|
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, |
|
<0>, /* Do Nothing */ |
|
<&clkc CLKID_VPU_0>, |
|
<&clkc CLKID_FCLK_DIV4>, |
|
<0>, /* Do Nothing */ |
|
<&clkc CLKID_VAPB_0>; |
|
assigned-clock-rates = <0>, /* Do Nothing */ |
|
<666666666>, |
|
<0>, /* Do Nothing */ |
|
<0>, /* Do Nothing */ |
|
<250000000>, |
|
<0>; /* Do Nothing */ |
|
}; |
|
|
|
&saradc { |
|
compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; |
|
clocks = <&xtal>, |
|
<&clkc CLKID_SAR_ADC>, |
|
<&clkc CLKID_SAR_ADC_CLK>, |
|
<&clkc CLKID_SAR_ADC_SEL>; |
|
clock-names = "clkin", "core", "adc_clk", "adc_sel"; |
|
}; |
|
|
|
&sd_emmc_a { |
|
clocks = <&clkc CLKID_SD_EMMC_A>, |
|
<&clkc CLKID_SD_EMMC_A_CLK0>, |
|
<&clkc CLKID_FCLK_DIV2>; |
|
clock-names = "core", "clkin0", "clkin1"; |
|
resets = <&reset RESET_SD_EMMC_A>; |
|
}; |
|
|
|
&sd_emmc_b { |
|
clocks = <&clkc CLKID_SD_EMMC_B>, |
|
<&clkc CLKID_SD_EMMC_B_CLK0>, |
|
<&clkc CLKID_FCLK_DIV2>; |
|
clock-names = "core", "clkin0", "clkin1"; |
|
resets = <&reset RESET_SD_EMMC_B>; |
|
}; |
|
|
|
&sd_emmc_c { |
|
clocks = <&clkc CLKID_SD_EMMC_C>, |
|
<&clkc CLKID_SD_EMMC_C_CLK0>, |
|
<&clkc CLKID_FCLK_DIV2>; |
|
clock-names = "core", "clkin0", "clkin1"; |
|
resets = <&reset RESET_SD_EMMC_C>; |
|
}; |
|
|
|
&simplefb_hdmi { |
|
clocks = <&clkc CLKID_HDMI_PCLK>, |
|
<&clkc CLKID_CLK81>, |
|
<&clkc CLKID_GCLK_VENCI_INT0>; |
|
}; |
|
|
|
&spicc { |
|
clocks = <&clkc CLKID_SPICC>; |
|
clock-names = "core"; |
|
resets = <&reset RESET_PERIPHS_SPICC>; |
|
num-cs = <1>; |
|
}; |
|
|
|
&spifc { |
|
clocks = <&clkc CLKID_SPI>; |
|
}; |
|
|
|
&uart_A { |
|
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; |
|
clock-names = "xtal", "pclk", "baud"; |
|
}; |
|
|
|
&uart_AO { |
|
clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; |
|
clock-names = "xtal", "pclk", "baud"; |
|
}; |
|
|
|
&uart_AO_B { |
|
clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; |
|
clock-names = "xtal", "pclk", "baud"; |
|
}; |
|
|
|
&uart_B { |
|
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; |
|
clock-names = "xtal", "pclk", "baud"; |
|
}; |
|
|
|
&uart_C { |
|
clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; |
|
clock-names = "xtal", "pclk", "baud"; |
|
}; |
|
|
|
&vpu { |
|
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; |
|
power-domains = <&pwrc PWRC_GXBB_VPU_ID>; |
|
}; |
|
|
|
&vdec { |
|
compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec"; |
|
clocks = <&clkc CLKID_DOS_PARSER>, |
|
<&clkc CLKID_DOS>, |
|
<&clkc CLKID_VDEC_1>, |
|
<&clkc CLKID_VDEC_HEVC>; |
|
clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; |
|
resets = <&reset RESET_PARSER>; |
|
reset-names = "esparser"; |
|
};
|
|
|