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846 lines
20 KiB
846 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2011 Freescale Semiconductor, Inc. |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/time.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include "mxs-saif.h" |
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#define MXS_SET_ADDR 0x4 |
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#define MXS_CLR_ADDR 0x8 |
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static struct mxs_saif *mxs_saif[2]; |
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|
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/* |
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* SAIF is a little different with other normal SOC DAIs on clock using. |
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* |
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* For MXS, two SAIF modules are instantiated on-chip. |
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* Each SAIF has a set of clock pins and can be operating in master |
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* mode simultaneously if they are connected to different off-chip codecs. |
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* Also, one of the two SAIFs can master or drive the clock pins while the |
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* other SAIF, in slave mode, receives clocking from the master SAIF. |
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* This also means that both SAIFs must operate at the same sample rate. |
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* |
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* We abstract this as each saif has a master, the master could be |
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* itself or other saifs. In the generic saif driver, saif does not need |
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* to know the different clkmux. Saif only needs to know who is its master |
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* and operating its master to generate the proper clock rate for it. |
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* The master id is provided in mach-specific layer according to different |
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* clkmux setting. |
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*/ |
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|
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static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
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int clk_id, unsigned int freq, int dir) |
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{ |
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); |
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switch (clk_id) { |
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case MXS_SAIF_MCLK: |
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saif->mclk = freq; |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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/* |
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* Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK |
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* is provided by other SAIF, we provide a interface here to get its master |
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* from its master_id. |
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* Note that the master could be itself. |
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*/ |
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static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) |
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{ |
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return mxs_saif[saif->master_id]; |
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} |
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/* |
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* Set SAIF clock and MCLK |
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*/ |
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static int mxs_saif_set_clk(struct mxs_saif *saif, |
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unsigned int mclk, |
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unsigned int rate) |
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{ |
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u32 scr; |
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int ret; |
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struct mxs_saif *master_saif; |
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dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); |
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/* Set master saif to generate proper clock */ |
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master_saif = mxs_saif_get_master(saif); |
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if (!master_saif) |
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return -EINVAL; |
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dev_dbg(saif->dev, "master saif%d\n", master_saif->id); |
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/* Checking if can playback and capture simutaneously */ |
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if (master_saif->ongoing && rate != master_saif->cur_rate) { |
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dev_err(saif->dev, |
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"can not change clock, master saif%d(rate %d) is ongoing\n", |
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master_saif->id, master_saif->cur_rate); |
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return -EINVAL; |
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} |
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scr = __raw_readl(master_saif->base + SAIF_CTRL); |
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scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; |
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scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; |
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/* |
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* Set SAIF clock |
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* |
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* The SAIF clock should be either 384*fs or 512*fs. |
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* If MCLK is used, the SAIF clk ratio needs to match mclk ratio. |
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* For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs. |
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* For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs. |
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* |
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* If MCLK is not used, we just set saif clk to 512*fs. |
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*/ |
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ret = clk_prepare_enable(master_saif->clk); |
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if (ret) |
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return ret; |
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if (master_saif->mclk_in_use) { |
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switch (mclk / rate) { |
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case 32: |
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case 64: |
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case 128: |
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case 256: |
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case 512: |
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scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; |
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ret = clk_set_rate(master_saif->clk, 512 * rate); |
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break; |
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case 48: |
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case 96: |
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case 192: |
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case 384: |
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scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; |
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ret = clk_set_rate(master_saif->clk, 384 * rate); |
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break; |
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default: |
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/* SAIF MCLK should be a sub-rate of 512x or 384x */ |
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clk_disable_unprepare(master_saif->clk); |
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return -EINVAL; |
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} |
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} else { |
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ret = clk_set_rate(master_saif->clk, 512 * rate); |
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scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; |
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} |
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clk_disable_unprepare(master_saif->clk); |
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if (ret) |
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return ret; |
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master_saif->cur_rate = rate; |
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if (!master_saif->mclk_in_use) { |
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__raw_writel(scr, master_saif->base + SAIF_CTRL); |
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return 0; |
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} |
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/* |
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* Program the over-sample rate for MCLK output |
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* |
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* The available MCLK range is 32x, 48x... 512x. The rate |
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* could be from 8kHz to 192kH. |
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*/ |
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switch (mclk / rate) { |
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case 32: |
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); |
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break; |
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case 64: |
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); |
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break; |
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case 128: |
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); |
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break; |
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case 256: |
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); |
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break; |
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case 512: |
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); |
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break; |
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case 48: |
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); |
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break; |
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case 96: |
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); |
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break; |
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case 192: |
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); |
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break; |
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case 384: |
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); |
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break; |
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default: |
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return -EINVAL; |
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} |
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__raw_writel(scr, master_saif->base + SAIF_CTRL); |
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return 0; |
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} |
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/* |
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* Put and disable MCLK. |
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*/ |
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int mxs_saif_put_mclk(unsigned int saif_id) |
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{ |
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struct mxs_saif *saif = mxs_saif[saif_id]; |
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u32 stat; |
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if (!saif) |
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return -EINVAL; |
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stat = __raw_readl(saif->base + SAIF_STAT); |
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if (stat & BM_SAIF_STAT_BUSY) { |
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dev_err(saif->dev, "error: busy\n"); |
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return -EBUSY; |
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} |
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clk_disable_unprepare(saif->clk); |
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/* disable MCLK output */ |
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__raw_writel(BM_SAIF_CTRL_CLKGATE, |
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saif->base + SAIF_CTRL + MXS_SET_ADDR); |
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__raw_writel(BM_SAIF_CTRL_RUN, |
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saif->base + SAIF_CTRL + MXS_CLR_ADDR); |
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saif->mclk_in_use = 0; |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); |
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/* |
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* Get MCLK and set clock rate, then enable it |
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* |
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* This interface is used for codecs who are using MCLK provided |
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* by saif. |
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*/ |
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int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, |
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unsigned int rate) |
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{ |
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struct mxs_saif *saif = mxs_saif[saif_id]; |
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u32 stat; |
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int ret; |
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struct mxs_saif *master_saif; |
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if (!saif) |
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return -EINVAL; |
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/* Clear Reset */ |
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__raw_writel(BM_SAIF_CTRL_SFTRST, |
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saif->base + SAIF_CTRL + MXS_CLR_ADDR); |
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/* FIXME: need clear clk gate for register r/w */ |
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__raw_writel(BM_SAIF_CTRL_CLKGATE, |
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saif->base + SAIF_CTRL + MXS_CLR_ADDR); |
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master_saif = mxs_saif_get_master(saif); |
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if (saif != master_saif) { |
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dev_err(saif->dev, "can not get mclk from a non-master saif\n"); |
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return -EINVAL; |
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} |
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stat = __raw_readl(saif->base + SAIF_STAT); |
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if (stat & BM_SAIF_STAT_BUSY) { |
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dev_err(saif->dev, "error: busy\n"); |
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return -EBUSY; |
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} |
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saif->mclk_in_use = 1; |
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ret = mxs_saif_set_clk(saif, mclk, rate); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(saif->clk); |
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if (ret) |
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return ret; |
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/* enable MCLK output */ |
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__raw_writel(BM_SAIF_CTRL_RUN, |
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saif->base + SAIF_CTRL + MXS_SET_ADDR); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); |
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/* |
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* SAIF DAI format configuration. |
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* Should only be called when port is inactive. |
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*/ |
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static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) |
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{ |
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u32 scr, stat; |
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u32 scr0; |
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); |
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stat = __raw_readl(saif->base + SAIF_STAT); |
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if (stat & BM_SAIF_STAT_BUSY) { |
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dev_err(cpu_dai->dev, "error: busy\n"); |
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return -EBUSY; |
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} |
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/* If SAIF1 is configured as slave, the clk gate needs to be cleared |
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* before the register can be written. |
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*/ |
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if (saif->id != saif->master_id) { |
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__raw_writel(BM_SAIF_CTRL_SFTRST, |
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saif->base + SAIF_CTRL + MXS_CLR_ADDR); |
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__raw_writel(BM_SAIF_CTRL_CLKGATE, |
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saif->base + SAIF_CTRL + MXS_CLR_ADDR); |
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} |
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scr0 = __raw_readl(saif->base + SAIF_CTRL); |
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scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ |
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& ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; |
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scr = 0; |
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/* DAI mode */ |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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/* data frame low 1clk before data */ |
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scr |= BM_SAIF_CTRL_DELAY; |
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scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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/* data frame high with data */ |
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scr &= ~BM_SAIF_CTRL_DELAY; |
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scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; |
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scr &= ~BM_SAIF_CTRL_JUSTIFY; |
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break; |
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default: |
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return -EINVAL; |
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} |
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/* DAI clock inversion */ |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_IB_IF: |
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scr |= BM_SAIF_CTRL_BITCLK_EDGE; |
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scr |= BM_SAIF_CTRL_LRCLK_POLARITY; |
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break; |
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case SND_SOC_DAIFMT_IB_NF: |
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scr |= BM_SAIF_CTRL_BITCLK_EDGE; |
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scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; |
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break; |
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case SND_SOC_DAIFMT_NB_IF: |
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scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; |
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scr |= BM_SAIF_CTRL_LRCLK_POLARITY; |
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break; |
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case SND_SOC_DAIFMT_NB_NF: |
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scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; |
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scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; |
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break; |
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} |
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/* |
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* Note: We simply just support master mode since SAIF TX can only |
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* work as master. |
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* Here the master is relative to codec side. |
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* Saif internally could be slave when working on EXTMASTER mode. |
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* We just hide this to machine driver. |
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*/ |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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if (saif->id == saif->master_id) |
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scr &= ~BM_SAIF_CTRL_SLAVE_MODE; |
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else |
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scr |= BM_SAIF_CTRL_SLAVE_MODE; |
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__raw_writel(scr | scr0, saif->base + SAIF_CTRL); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int mxs_saif_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *cpu_dai) |
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{ |
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); |
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int ret; |
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/* clear error status to 0 for each re-open */ |
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saif->fifo_underrun = 0; |
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saif->fifo_overrun = 0; |
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/* Clear Reset for normal operations */ |
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__raw_writel(BM_SAIF_CTRL_SFTRST, |
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saif->base + SAIF_CTRL + MXS_CLR_ADDR); |
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/* clear clock gate */ |
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__raw_writel(BM_SAIF_CTRL_CLKGATE, |
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saif->base + SAIF_CTRL + MXS_CLR_ADDR); |
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ret = clk_prepare(saif->clk); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static void mxs_saif_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *cpu_dai) |
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{ |
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); |
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clk_unprepare(saif->clk); |
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} |
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/* |
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* Should only be called when port is inactive. |
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* although can be called multiple times by upper layers. |
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*/ |
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static int mxs_saif_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *cpu_dai) |
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{ |
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); |
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struct mxs_saif *master_saif; |
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u32 scr, stat; |
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int ret; |
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master_saif = mxs_saif_get_master(saif); |
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if (!master_saif) |
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return -EINVAL; |
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|
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/* mclk should already be set */ |
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if (!saif->mclk && saif->mclk_in_use) { |
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dev_err(cpu_dai->dev, "set mclk first\n"); |
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return -EINVAL; |
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} |
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stat = __raw_readl(saif->base + SAIF_STAT); |
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if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) { |
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dev_err(cpu_dai->dev, "error: busy\n"); |
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return -EBUSY; |
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} |
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|
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/* |
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* Set saif clk based on sample rate. |
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* If mclk is used, we also set mclk, if not, saif->mclk is |
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* default 0, means not used. |
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*/ |
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ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); |
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if (ret) { |
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dev_err(cpu_dai->dev, "unable to get proper clk\n"); |
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return ret; |
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} |
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|
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if (saif != master_saif) { |
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/* |
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* Set an initial clock rate for the saif internal logic to work |
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* properly. This is important when working in EXTMASTER mode |
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* that uses the other saif's BITCLK&LRCLK but it still needs a |
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* basic clock which should be fast enough for the internal |
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* logic. |
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*/ |
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clk_enable(saif->clk); |
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ret = clk_set_rate(saif->clk, 24000000); |
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clk_disable(saif->clk); |
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if (ret) |
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return ret; |
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|
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ret = clk_prepare(master_saif->clk); |
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if (ret) |
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return ret; |
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} |
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scr = __raw_readl(saif->base + SAIF_CTRL); |
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scr &= ~BM_SAIF_CTRL_WORD_LENGTH; |
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scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; |
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switch (params_format(params)) { |
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case SNDRV_PCM_FORMAT_S16_LE: |
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scr |= BF_SAIF_CTRL_WORD_LENGTH(0); |
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break; |
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case SNDRV_PCM_FORMAT_S20_3LE: |
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scr |= BF_SAIF_CTRL_WORD_LENGTH(4); |
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scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; |
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break; |
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case SNDRV_PCM_FORMAT_S24_LE: |
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scr |= BF_SAIF_CTRL_WORD_LENGTH(8); |
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scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; |
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break; |
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default: |
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return -EINVAL; |
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} |
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|
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/* Tx/Rx config */ |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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/* enable TX mode */ |
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scr &= ~BM_SAIF_CTRL_READ_MODE; |
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} else { |
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/* enable RX mode */ |
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scr |= BM_SAIF_CTRL_READ_MODE; |
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} |
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|
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__raw_writel(scr, saif->base + SAIF_CTRL); |
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return 0; |
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} |
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|
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static int mxs_saif_prepare(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *cpu_dai) |
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{ |
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); |
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|
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/* enable FIFO error irqs */ |
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__raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, |
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saif->base + SAIF_CTRL + MXS_SET_ADDR); |
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|
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return 0; |
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} |
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static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *cpu_dai) |
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{ |
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); |
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struct mxs_saif *master_saif; |
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u32 delay; |
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int ret; |
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master_saif = mxs_saif_get_master(saif); |
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if (!master_saif) |
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return -EINVAL; |
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|
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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if (saif->state == MXS_SAIF_STATE_RUNNING) |
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return 0; |
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|
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dev_dbg(cpu_dai->dev, "start\n"); |
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|
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ret = clk_enable(master_saif->clk); |
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if (ret) { |
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dev_err(saif->dev, "Failed to enable master clock\n"); |
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return ret; |
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} |
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|
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/* |
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* If the saif's master is not itself, we also need to enable |
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* itself clk for its internal basic logic to work. |
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*/ |
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if (saif != master_saif) { |
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ret = clk_enable(saif->clk); |
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if (ret) { |
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dev_err(saif->dev, "Failed to enable master clock\n"); |
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clk_disable(master_saif->clk); |
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return ret; |
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} |
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|
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__raw_writel(BM_SAIF_CTRL_RUN, |
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saif->base + SAIF_CTRL + MXS_SET_ADDR); |
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} |
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|
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if (!master_saif->mclk_in_use) |
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__raw_writel(BM_SAIF_CTRL_RUN, |
|
master_saif->base + SAIF_CTRL + MXS_SET_ADDR); |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
|
/* |
|
* write data to saif data register to trigger |
|
* the transfer. |
|
* For 24-bit format the 32-bit FIFO register stores |
|
* only one channel, so we need to write twice. |
|
* This is also safe for the other non 24-bit formats. |
|
*/ |
|
__raw_writel(0, saif->base + SAIF_DATA); |
|
__raw_writel(0, saif->base + SAIF_DATA); |
|
} else { |
|
/* |
|
* read data from saif data register to trigger |
|
* the receive. |
|
* For 24-bit format the 32-bit FIFO register stores |
|
* only one channel, so we need to read twice. |
|
* This is also safe for the other non 24-bit formats. |
|
*/ |
|
__raw_readl(saif->base + SAIF_DATA); |
|
__raw_readl(saif->base + SAIF_DATA); |
|
} |
|
|
|
master_saif->ongoing = 1; |
|
saif->state = MXS_SAIF_STATE_RUNNING; |
|
|
|
dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", |
|
__raw_readl(saif->base + SAIF_CTRL), |
|
__raw_readl(saif->base + SAIF_STAT)); |
|
|
|
dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", |
|
__raw_readl(master_saif->base + SAIF_CTRL), |
|
__raw_readl(master_saif->base + SAIF_STAT)); |
|
break; |
|
case SNDRV_PCM_TRIGGER_SUSPEND: |
|
case SNDRV_PCM_TRIGGER_STOP: |
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
|
if (saif->state == MXS_SAIF_STATE_STOPPED) |
|
return 0; |
|
|
|
dev_dbg(cpu_dai->dev, "stop\n"); |
|
|
|
/* wait a while for the current sample to complete */ |
|
delay = USEC_PER_SEC / master_saif->cur_rate; |
|
|
|
if (!master_saif->mclk_in_use) { |
|
__raw_writel(BM_SAIF_CTRL_RUN, |
|
master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); |
|
udelay(delay); |
|
} |
|
clk_disable(master_saif->clk); |
|
|
|
if (saif != master_saif) { |
|
__raw_writel(BM_SAIF_CTRL_RUN, |
|
saif->base + SAIF_CTRL + MXS_CLR_ADDR); |
|
udelay(delay); |
|
clk_disable(saif->clk); |
|
} |
|
|
|
master_saif->ongoing = 0; |
|
saif->state = MXS_SAIF_STATE_STOPPED; |
|
|
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
#define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 |
|
#define MXS_SAIF_FORMATS \ |
|
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
|
SNDRV_PCM_FMTBIT_S24_LE) |
|
|
|
static const struct snd_soc_dai_ops mxs_saif_dai_ops = { |
|
.startup = mxs_saif_startup, |
|
.shutdown = mxs_saif_shutdown, |
|
.trigger = mxs_saif_trigger, |
|
.prepare = mxs_saif_prepare, |
|
.hw_params = mxs_saif_hw_params, |
|
.set_sysclk = mxs_saif_set_dai_sysclk, |
|
.set_fmt = mxs_saif_set_dai_fmt, |
|
}; |
|
|
|
static int mxs_saif_dai_probe(struct snd_soc_dai *dai) |
|
{ |
|
struct mxs_saif *saif = dev_get_drvdata(dai->dev); |
|
|
|
snd_soc_dai_set_drvdata(dai, saif); |
|
|
|
return 0; |
|
} |
|
|
|
static struct snd_soc_dai_driver mxs_saif_dai = { |
|
.name = "mxs-saif", |
|
.probe = mxs_saif_dai_probe, |
|
.playback = { |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = MXS_SAIF_RATES, |
|
.formats = MXS_SAIF_FORMATS, |
|
}, |
|
.capture = { |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = MXS_SAIF_RATES, |
|
.formats = MXS_SAIF_FORMATS, |
|
}, |
|
.ops = &mxs_saif_dai_ops, |
|
}; |
|
|
|
static const struct snd_soc_component_driver mxs_saif_component = { |
|
.name = "mxs-saif", |
|
}; |
|
|
|
static irqreturn_t mxs_saif_irq(int irq, void *dev_id) |
|
{ |
|
struct mxs_saif *saif = dev_id; |
|
unsigned int stat; |
|
|
|
stat = __raw_readl(saif->base + SAIF_STAT); |
|
if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | |
|
BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) |
|
return IRQ_NONE; |
|
|
|
if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { |
|
dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); |
|
__raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, |
|
saif->base + SAIF_STAT + MXS_CLR_ADDR); |
|
} |
|
|
|
if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { |
|
dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); |
|
__raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, |
|
saif->base + SAIF_STAT + MXS_CLR_ADDR); |
|
} |
|
|
|
dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", |
|
__raw_readl(saif->base + SAIF_CTRL), |
|
__raw_readl(saif->base + SAIF_STAT)); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int mxs_saif_mclk_init(struct platform_device *pdev) |
|
{ |
|
struct mxs_saif *saif = platform_get_drvdata(pdev); |
|
struct device_node *np = pdev->dev.of_node; |
|
struct clk *clk; |
|
int ret; |
|
|
|
clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", |
|
__clk_get_name(saif->clk), 0, |
|
saif->base + SAIF_CTRL, |
|
BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, |
|
0, NULL); |
|
if (IS_ERR(clk)) { |
|
ret = PTR_ERR(clk); |
|
if (ret == -EEXIST) |
|
return 0; |
|
dev_err(&pdev->dev, "failed to register mclk: %d\n", ret); |
|
return PTR_ERR(clk); |
|
} |
|
|
|
ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); |
|
if (ret) |
|
return ret; |
|
|
|
return 0; |
|
} |
|
|
|
static int mxs_saif_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *np = pdev->dev.of_node; |
|
struct mxs_saif *saif; |
|
int irq, ret; |
|
struct device_node *master; |
|
|
|
saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); |
|
if (!saif) |
|
return -ENOMEM; |
|
|
|
ret = of_alias_get_id(np, "saif"); |
|
if (ret < 0) |
|
return ret; |
|
else |
|
saif->id = ret; |
|
|
|
if (saif->id >= ARRAY_SIZE(mxs_saif)) { |
|
dev_err(&pdev->dev, "get wrong saif id\n"); |
|
return -EINVAL; |
|
} |
|
|
|
/* |
|
* If there is no "fsl,saif-master" phandle, it's a saif |
|
* master. Otherwise, it's a slave and its phandle points |
|
* to the master. |
|
*/ |
|
master = of_parse_phandle(np, "fsl,saif-master", 0); |
|
if (!master) { |
|
saif->master_id = saif->id; |
|
} else { |
|
ret = of_alias_get_id(master, "saif"); |
|
if (ret < 0) |
|
return ret; |
|
else |
|
saif->master_id = ret; |
|
|
|
if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { |
|
dev_err(&pdev->dev, "get wrong master id\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
mxs_saif[saif->id] = saif; |
|
|
|
saif->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(saif->clk)) { |
|
ret = PTR_ERR(saif->clk); |
|
dev_err(&pdev->dev, "Cannot get the clock: %d\n", |
|
ret); |
|
return ret; |
|
} |
|
|
|
saif->base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(saif->base)) |
|
return PTR_ERR(saif->base); |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return irq; |
|
|
|
saif->dev = &pdev->dev; |
|
ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0, |
|
dev_name(&pdev->dev), saif); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to request irq\n"); |
|
return ret; |
|
} |
|
|
|
platform_set_drvdata(pdev, saif); |
|
|
|
/* We only support saif0 being tx and clock master */ |
|
if (saif->id == 0) { |
|
ret = mxs_saif_mclk_init(pdev); |
|
if (ret) |
|
dev_warn(&pdev->dev, "failed to init clocks\n"); |
|
} |
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component, |
|
&mxs_saif_dai, 1); |
|
if (ret) { |
|
dev_err(&pdev->dev, "register DAI failed\n"); |
|
return ret; |
|
} |
|
|
|
ret = mxs_pcm_platform_register(&pdev->dev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "register PCM failed: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id mxs_saif_dt_ids[] = { |
|
{ .compatible = "fsl,imx28-saif", }, |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); |
|
|
|
static struct platform_driver mxs_saif_driver = { |
|
.probe = mxs_saif_probe, |
|
|
|
.driver = { |
|
.name = "mxs-saif", |
|
.of_match_table = mxs_saif_dt_ids, |
|
}, |
|
}; |
|
|
|
module_platform_driver(mxs_saif_driver); |
|
|
|
MODULE_AUTHOR("Freescale Semiconductor, Inc."); |
|
MODULE_DESCRIPTION("MXS ASoC SAIF driver"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:mxs-saif");
|
|
|