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159 lines
4.6 KiB
159 lines
4.6 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* -*- linux-c -*- ------------------------------------------------------- * |
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* |
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* Copyright 2002 H. Peter Anvin - All Rights Reserved |
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* |
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* ----------------------------------------------------------------------- */ |
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/* |
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* raid6/sse1.c |
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* |
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* SSE-1/MMXEXT implementation of RAID-6 syndrome functions |
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* |
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* This is really an MMX implementation, but it requires SSE-1 or |
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* AMD MMXEXT for prefetch support and a few other features. The |
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* support for nontemporal memory accesses is enough to make this |
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* worthwhile as a separate implementation. |
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*/ |
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#ifdef CONFIG_X86_32 |
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#include <linux/raid/pq.h> |
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#include "x86.h" |
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/* Defined in raid6/mmx.c */ |
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extern const struct raid6_mmx_constants { |
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u64 x1d; |
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} raid6_mmx_constants; |
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static int raid6_have_sse1_or_mmxext(void) |
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{ |
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/* Not really boot_cpu but "all_cpus" */ |
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return boot_cpu_has(X86_FEATURE_MMX) && |
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(boot_cpu_has(X86_FEATURE_XMM) || |
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boot_cpu_has(X86_FEATURE_MMXEXT)); |
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} |
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/* |
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* Plain SSE1 implementation |
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*/ |
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static void raid6_sse11_gen_syndrome(int disks, size_t bytes, void **ptrs) |
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{ |
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u8 **dptr = (u8 **)ptrs; |
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u8 *p, *q; |
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int d, z, z0; |
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z0 = disks - 3; /* Highest data disk */ |
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p = dptr[z0+1]; /* XOR parity */ |
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q = dptr[z0+2]; /* RS syndrome */ |
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kernel_fpu_begin(); |
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asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); |
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asm volatile("pxor %mm5,%mm5"); /* Zero temp */ |
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for ( d = 0 ; d < bytes ; d += 8 ) { |
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asm volatile("prefetchnta %0" : : "m" (dptr[z0][d])); |
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asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */ |
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asm volatile("prefetchnta %0" : : "m" (dptr[z0-1][d])); |
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asm volatile("movq %mm2,%mm4"); /* Q[0] */ |
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asm volatile("movq %0,%%mm6" : : "m" (dptr[z0-1][d])); |
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for ( z = z0-2 ; z >= 0 ; z-- ) { |
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d])); |
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asm volatile("pcmpgtb %mm4,%mm5"); |
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asm volatile("paddb %mm4,%mm4"); |
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asm volatile("pand %mm0,%mm5"); |
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asm volatile("pxor %mm5,%mm4"); |
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asm volatile("pxor %mm5,%mm5"); |
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asm volatile("pxor %mm6,%mm2"); |
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asm volatile("pxor %mm6,%mm4"); |
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asm volatile("movq %0,%%mm6" : : "m" (dptr[z][d])); |
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} |
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asm volatile("pcmpgtb %mm4,%mm5"); |
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asm volatile("paddb %mm4,%mm4"); |
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asm volatile("pand %mm0,%mm5"); |
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asm volatile("pxor %mm5,%mm4"); |
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asm volatile("pxor %mm5,%mm5"); |
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asm volatile("pxor %mm6,%mm2"); |
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asm volatile("pxor %mm6,%mm4"); |
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asm volatile("movntq %%mm2,%0" : "=m" (p[d])); |
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asm volatile("movntq %%mm4,%0" : "=m" (q[d])); |
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} |
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asm volatile("sfence" : : : "memory"); |
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kernel_fpu_end(); |
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} |
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const struct raid6_calls raid6_sse1x1 = { |
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raid6_sse11_gen_syndrome, |
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NULL, /* XOR not yet implemented */ |
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raid6_have_sse1_or_mmxext, |
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"sse1x1", |
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1 /* Has cache hints */ |
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}; |
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/* |
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* Unrolled-by-2 SSE1 implementation |
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*/ |
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static void raid6_sse12_gen_syndrome(int disks, size_t bytes, void **ptrs) |
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{ |
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u8 **dptr = (u8 **)ptrs; |
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u8 *p, *q; |
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int d, z, z0; |
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z0 = disks - 3; /* Highest data disk */ |
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p = dptr[z0+1]; /* XOR parity */ |
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q = dptr[z0+2]; /* RS syndrome */ |
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kernel_fpu_begin(); |
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asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d)); |
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asm volatile("pxor %mm5,%mm5"); /* Zero temp */ |
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asm volatile("pxor %mm7,%mm7"); /* Zero temp */ |
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/* We uniformly assume a single prefetch covers at least 16 bytes */ |
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for ( d = 0 ; d < bytes ; d += 16 ) { |
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asm volatile("prefetchnta %0" : : "m" (dptr[z0][d])); |
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asm volatile("movq %0,%%mm2" : : "m" (dptr[z0][d])); /* P[0] */ |
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asm volatile("movq %0,%%mm3" : : "m" (dptr[z0][d+8])); /* P[1] */ |
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asm volatile("movq %mm2,%mm4"); /* Q[0] */ |
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asm volatile("movq %mm3,%mm6"); /* Q[1] */ |
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for ( z = z0-1 ; z >= 0 ; z-- ) { |
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d])); |
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asm volatile("pcmpgtb %mm4,%mm5"); |
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asm volatile("pcmpgtb %mm6,%mm7"); |
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asm volatile("paddb %mm4,%mm4"); |
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asm volatile("paddb %mm6,%mm6"); |
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asm volatile("pand %mm0,%mm5"); |
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asm volatile("pand %mm0,%mm7"); |
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asm volatile("pxor %mm5,%mm4"); |
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asm volatile("pxor %mm7,%mm6"); |
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asm volatile("movq %0,%%mm5" : : "m" (dptr[z][d])); |
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asm volatile("movq %0,%%mm7" : : "m" (dptr[z][d+8])); |
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asm volatile("pxor %mm5,%mm2"); |
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asm volatile("pxor %mm7,%mm3"); |
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asm volatile("pxor %mm5,%mm4"); |
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asm volatile("pxor %mm7,%mm6"); |
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asm volatile("pxor %mm5,%mm5"); |
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asm volatile("pxor %mm7,%mm7"); |
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} |
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asm volatile("movntq %%mm2,%0" : "=m" (p[d])); |
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asm volatile("movntq %%mm3,%0" : "=m" (p[d+8])); |
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asm volatile("movntq %%mm4,%0" : "=m" (q[d])); |
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asm volatile("movntq %%mm6,%0" : "=m" (q[d+8])); |
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} |
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asm volatile("sfence" : :: "memory"); |
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kernel_fpu_end(); |
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} |
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const struct raid6_calls raid6_sse1x2 = { |
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raid6_sse12_gen_syndrome, |
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NULL, /* XOR not yet implemented */ |
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raid6_have_sse1_or_mmxext, |
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"sse1x2", |
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1 /* Has cache hints */ |
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}; |
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#endif
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