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2096 lines
52 KiB
2096 lines
52 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* NVIDIA Tegra xHCI host controller driver |
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* |
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* Copyright (C) 2014 NVIDIA Corporation |
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* Copyright (C) 2014 Google, Inc. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/firmware.h> |
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#include <linux/interrupt.h> |
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#include <linux/iopoll.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/phy/tegra/xusb.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm.h> |
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#include <linux/pm_domain.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/reset.h> |
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#include <linux/slab.h> |
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#include <linux/usb/otg.h> |
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#include <linux/usb/phy.h> |
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#include <linux/usb/role.h> |
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#include <soc/tegra/pmc.h> |
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#include "xhci.h" |
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#define TEGRA_XHCI_SS_HIGH_SPEED 120000000 |
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#define TEGRA_XHCI_SS_LOW_SPEED 12000000 |
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/* FPCI CFG registers */ |
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#define XUSB_CFG_1 0x004 |
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#define XUSB_IO_SPACE_EN BIT(0) |
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#define XUSB_MEM_SPACE_EN BIT(1) |
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#define XUSB_BUS_MASTER_EN BIT(2) |
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#define XUSB_CFG_4 0x010 |
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#define XUSB_BASE_ADDR_SHIFT 15 |
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#define XUSB_BASE_ADDR_MASK 0x1ffff |
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#define XUSB_CFG_16 0x040 |
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#define XUSB_CFG_24 0x060 |
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#define XUSB_CFG_AXI_CFG 0x0f8 |
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#define XUSB_CFG_ARU_C11_CSBRANGE 0x41c |
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#define XUSB_CFG_ARU_CONTEXT 0x43c |
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#define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478 |
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#define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c |
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#define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480 |
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#define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484 |
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#define XUSB_CFG_CSB_BASE_ADDR 0x800 |
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/* FPCI mailbox registers */ |
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/* XUSB_CFG_ARU_MBOX_CMD */ |
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#define MBOX_DEST_FALC BIT(27) |
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#define MBOX_DEST_PME BIT(28) |
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#define MBOX_DEST_SMI BIT(29) |
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#define MBOX_DEST_XHCI BIT(30) |
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#define MBOX_INT_EN BIT(31) |
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/* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */ |
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#define CMD_DATA_SHIFT 0 |
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#define CMD_DATA_MASK 0xffffff |
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#define CMD_TYPE_SHIFT 24 |
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#define CMD_TYPE_MASK 0xff |
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/* XUSB_CFG_ARU_MBOX_OWNER */ |
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#define MBOX_OWNER_NONE 0 |
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#define MBOX_OWNER_FW 1 |
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#define MBOX_OWNER_SW 2 |
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#define XUSB_CFG_ARU_SMI_INTR 0x428 |
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#define MBOX_SMI_INTR_FW_HANG BIT(1) |
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#define MBOX_SMI_INTR_EN BIT(3) |
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|
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/* IPFS registers */ |
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#define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0 |
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#define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4 |
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#define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8 |
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#define IPFS_XUSB_HOST_MSI_VEC0_0 0x100 |
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#define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140 |
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#define IPFS_XUSB_HOST_CONFIGURATION_0 0x180 |
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#define IPFS_EN_FPCI BIT(0) |
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#define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184 |
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#define IPFS_XUSB_HOST_INTR_MASK_0 0x188 |
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#define IPFS_IP_INT_MASK BIT(16) |
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#define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198 |
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#define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c |
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#define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc |
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#define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc |
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#define CSB_PAGE_SELECT_MASK 0x7fffff |
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#define CSB_PAGE_SELECT_SHIFT 9 |
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#define CSB_PAGE_OFFSET_MASK 0x1ff |
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#define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \ |
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CSB_PAGE_SELECT_MASK) |
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#define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK) |
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/* Falcon CSB registers */ |
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#define XUSB_FALC_CPUCTL 0x100 |
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#define CPUCTL_STARTCPU BIT(1) |
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#define CPUCTL_STATE_HALTED BIT(4) |
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#define CPUCTL_STATE_STOPPED BIT(5) |
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#define XUSB_FALC_BOOTVEC 0x104 |
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#define XUSB_FALC_DMACTL 0x10c |
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#define XUSB_FALC_IMFILLRNG1 0x154 |
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#define IMFILLRNG1_TAG_MASK 0xffff |
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#define IMFILLRNG1_TAG_LO_SHIFT 0 |
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#define IMFILLRNG1_TAG_HI_SHIFT 16 |
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#define XUSB_FALC_IMFILLCTL 0x158 |
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/* MP CSB registers */ |
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#define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 |
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#define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 |
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#define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08 |
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#define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10 |
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#define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8 |
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#define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff |
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#define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24 |
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#define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff |
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#define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14 |
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#define L2IMEMOP_ACTION_SHIFT 24 |
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#define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT) |
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#define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT) |
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#define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18 |
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#define L2IMEMOP_RESULT_VLD BIT(31) |
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#define XUSB_CSB_MP_APMAP 0x10181c |
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#define APMAP_BOOTPATH BIT(31) |
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#define IMEM_BLOCK_SIZE 256 |
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struct tegra_xusb_fw_header { |
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__le32 boot_loadaddr_in_imem; |
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__le32 boot_codedfi_offset; |
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__le32 boot_codetag; |
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__le32 boot_codesize; |
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__le32 phys_memaddr; |
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__le16 reqphys_memsize; |
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__le16 alloc_phys_memsize; |
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__le32 rodata_img_offset; |
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__le32 rodata_section_start; |
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__le32 rodata_section_end; |
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__le32 main_fnaddr; |
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__le32 fwimg_cksum; |
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__le32 fwimg_created_time; |
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__le32 imem_resident_start; |
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__le32 imem_resident_end; |
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__le32 idirect_start; |
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__le32 idirect_end; |
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__le32 l2_imem_start; |
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__le32 l2_imem_end; |
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__le32 version_id; |
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u8 init_ddirect; |
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u8 reserved[3]; |
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__le32 phys_addr_log_buffer; |
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__le32 total_log_entries; |
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__le32 dequeue_ptr; |
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__le32 dummy_var[2]; |
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__le32 fwimg_len; |
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u8 magic[8]; |
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__le32 ss_low_power_entry_timeout; |
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u8 num_hsic_port; |
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u8 padding[139]; /* Pad to 256 bytes */ |
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}; |
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struct tegra_xusb_phy_type { |
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const char *name; |
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unsigned int num; |
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}; |
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struct tegra_xusb_mbox_regs { |
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u16 cmd; |
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u16 data_in; |
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u16 data_out; |
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u16 owner; |
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}; |
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struct tegra_xusb_context_soc { |
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struct { |
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const unsigned int *offsets; |
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unsigned int num_offsets; |
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} ipfs; |
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struct { |
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const unsigned int *offsets; |
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unsigned int num_offsets; |
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} fpci; |
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}; |
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struct tegra_xusb_soc { |
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const char *firmware; |
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const char * const *supply_names; |
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unsigned int num_supplies; |
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const struct tegra_xusb_phy_type *phy_types; |
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unsigned int num_types; |
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const struct tegra_xusb_context_soc *context; |
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struct { |
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struct { |
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unsigned int offset; |
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unsigned int count; |
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} usb2, ulpi, hsic, usb3; |
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} ports; |
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struct tegra_xusb_mbox_regs mbox; |
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bool scale_ss_clock; |
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bool has_ipfs; |
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bool lpm_support; |
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bool otg_reset_sspi; |
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}; |
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struct tegra_xusb_context { |
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u32 *ipfs; |
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u32 *fpci; |
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}; |
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struct tegra_xusb { |
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struct device *dev; |
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void __iomem *regs; |
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struct usb_hcd *hcd; |
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struct mutex lock; |
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int xhci_irq; |
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int mbox_irq; |
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void __iomem *ipfs_base; |
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void __iomem *fpci_base; |
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const struct tegra_xusb_soc *soc; |
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struct regulator_bulk_data *supplies; |
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struct tegra_xusb_padctl *padctl; |
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struct clk *host_clk; |
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struct clk *falcon_clk; |
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struct clk *ss_clk; |
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struct clk *ss_src_clk; |
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struct clk *hs_src_clk; |
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struct clk *fs_src_clk; |
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struct clk *pll_u_480m; |
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struct clk *clk_m; |
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struct clk *pll_e; |
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struct reset_control *host_rst; |
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struct reset_control *ss_rst; |
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struct device *genpd_dev_host; |
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struct device *genpd_dev_ss; |
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struct device_link *genpd_dl_host; |
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struct device_link *genpd_dl_ss; |
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struct phy **phys; |
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unsigned int num_phys; |
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struct usb_phy **usbphy; |
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unsigned int num_usb_phys; |
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int otg_usb2_port; |
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int otg_usb3_port; |
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bool host_mode; |
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struct notifier_block id_nb; |
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struct work_struct id_work; |
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/* Firmware loading related */ |
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struct { |
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size_t size; |
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void *virt; |
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dma_addr_t phys; |
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} fw; |
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struct tegra_xusb_context context; |
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}; |
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static struct hc_driver __read_mostly tegra_xhci_hc_driver; |
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static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) |
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{ |
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return readl(tegra->fpci_base + offset); |
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} |
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static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, |
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unsigned int offset) |
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{ |
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writel(value, tegra->fpci_base + offset); |
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} |
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static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) |
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{ |
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return readl(tegra->ipfs_base + offset); |
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} |
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static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, |
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unsigned int offset) |
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{ |
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writel(value, tegra->ipfs_base + offset); |
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} |
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static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) |
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{ |
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u32 page = CSB_PAGE_SELECT(offset); |
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u32 ofs = CSB_PAGE_OFFSET(offset); |
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fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); |
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return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); |
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} |
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static void csb_writel(struct tegra_xusb *tegra, u32 value, |
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unsigned int offset) |
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{ |
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u32 page = CSB_PAGE_SELECT(offset); |
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u32 ofs = CSB_PAGE_OFFSET(offset); |
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fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); |
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fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); |
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} |
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static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, |
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unsigned long rate) |
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{ |
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unsigned long new_parent_rate, old_parent_rate; |
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struct clk *clk = tegra->ss_src_clk; |
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unsigned int div; |
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int err; |
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if (clk_get_rate(clk) == rate) |
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return 0; |
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switch (rate) { |
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case TEGRA_XHCI_SS_HIGH_SPEED: |
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/* |
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* Reparent to PLLU_480M. Set divider first to avoid |
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* overclocking. |
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*/ |
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old_parent_rate = clk_get_rate(clk_get_parent(clk)); |
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new_parent_rate = clk_get_rate(tegra->pll_u_480m); |
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div = new_parent_rate / rate; |
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err = clk_set_rate(clk, old_parent_rate / div); |
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if (err) |
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return err; |
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err = clk_set_parent(clk, tegra->pll_u_480m); |
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if (err) |
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return err; |
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/* |
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* The rate should already be correct, but set it again just |
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* to be sure. |
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*/ |
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err = clk_set_rate(clk, rate); |
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if (err) |
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return err; |
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break; |
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case TEGRA_XHCI_SS_LOW_SPEED: |
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/* Reparent to CLK_M */ |
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err = clk_set_parent(clk, tegra->clk_m); |
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if (err) |
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return err; |
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err = clk_set_rate(clk, rate); |
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if (err) |
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return err; |
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break; |
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default: |
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dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate); |
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return -EINVAL; |
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} |
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if (clk_get_rate(clk) != rate) { |
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dev_err(tegra->dev, "SS clock doesn't match requested rate\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static unsigned long extract_field(u32 value, unsigned int start, |
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unsigned int count) |
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{ |
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return (value >> start) & ((1 << count) - 1); |
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} |
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/* Command requests from the firmware */ |
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enum tegra_xusb_mbox_cmd { |
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MBOX_CMD_MSG_ENABLED = 1, |
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MBOX_CMD_INC_FALC_CLOCK, |
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MBOX_CMD_DEC_FALC_CLOCK, |
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MBOX_CMD_INC_SSPI_CLOCK, |
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MBOX_CMD_DEC_SSPI_CLOCK, |
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MBOX_CMD_SET_BW, /* no ACK/NAK required */ |
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MBOX_CMD_SET_SS_PWR_GATING, |
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MBOX_CMD_SET_SS_PWR_UNGATING, |
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MBOX_CMD_SAVE_DFE_CTLE_CTX, |
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MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */ |
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MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */ |
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MBOX_CMD_START_HSIC_IDLE, |
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MBOX_CMD_STOP_HSIC_IDLE, |
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MBOX_CMD_DBC_WAKE_STACK, /* unused */ |
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MBOX_CMD_HSIC_PRETEND_CONNECT, |
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MBOX_CMD_RESET_SSPI, |
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MBOX_CMD_DISABLE_SS_LFPS_DETECTION, |
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MBOX_CMD_ENABLE_SS_LFPS_DETECTION, |
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MBOX_CMD_MAX, |
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/* Response message to above commands */ |
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MBOX_CMD_ACK = 128, |
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MBOX_CMD_NAK |
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}; |
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struct tegra_xusb_mbox_msg { |
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u32 cmd; |
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u32 data; |
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}; |
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static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg) |
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{ |
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return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT | |
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(msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT; |
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} |
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static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg, |
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u32 value) |
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{ |
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msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; |
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msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK; |
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} |
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static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) |
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{ |
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switch (cmd) { |
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case MBOX_CMD_SET_BW: |
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case MBOX_CMD_ACK: |
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case MBOX_CMD_NAK: |
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return false; |
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default: |
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return true; |
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} |
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} |
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static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, |
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const struct tegra_xusb_mbox_msg *msg) |
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{ |
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bool wait_for_idle = false; |
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u32 value; |
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/* |
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* Acquire the mailbox. The firmware still owns the mailbox for |
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* ACK/NAK messages. |
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*/ |
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if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { |
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value = fpci_readl(tegra, tegra->soc->mbox.owner); |
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if (value != MBOX_OWNER_NONE) { |
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dev_err(tegra->dev, "mailbox is busy\n"); |
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return -EBUSY; |
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} |
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fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); |
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value = fpci_readl(tegra, tegra->soc->mbox.owner); |
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if (value != MBOX_OWNER_SW) { |
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dev_err(tegra->dev, "failed to acquire mailbox\n"); |
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return -EBUSY; |
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} |
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wait_for_idle = true; |
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} |
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value = tegra_xusb_mbox_pack(msg); |
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fpci_writel(tegra, value, tegra->soc->mbox.data_in); |
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value = fpci_readl(tegra, tegra->soc->mbox.cmd); |
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value |= MBOX_INT_EN | MBOX_DEST_FALC; |
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fpci_writel(tegra, value, tegra->soc->mbox.cmd); |
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|
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if (wait_for_idle) { |
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unsigned long timeout = jiffies + msecs_to_jiffies(250); |
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|
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while (time_before(jiffies, timeout)) { |
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value = fpci_readl(tegra, tegra->soc->mbox.owner); |
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if (value == MBOX_OWNER_NONE) |
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break; |
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usleep_range(10, 20); |
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} |
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if (time_after(jiffies, timeout)) |
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value = fpci_readl(tegra, tegra->soc->mbox.owner); |
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if (value != MBOX_OWNER_NONE) |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) |
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{ |
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struct tegra_xusb *tegra = data; |
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u32 value; |
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/* clear mailbox interrupts */ |
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value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); |
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fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); |
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if (value & MBOX_SMI_INTR_FW_HANG) |
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dev_err(tegra->dev, "controller firmware hang\n"); |
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return IRQ_WAKE_THREAD; |
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} |
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static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, |
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const struct tegra_xusb_mbox_msg *msg) |
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{ |
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struct tegra_xusb_padctl *padctl = tegra->padctl; |
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const struct tegra_xusb_soc *soc = tegra->soc; |
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struct device *dev = tegra->dev; |
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struct tegra_xusb_mbox_msg rsp; |
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unsigned long mask; |
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unsigned int port; |
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bool idle, enable; |
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int err = 0; |
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|
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memset(&rsp, 0, sizeof(rsp)); |
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|
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switch (msg->cmd) { |
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case MBOX_CMD_INC_FALC_CLOCK: |
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case MBOX_CMD_DEC_FALC_CLOCK: |
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rsp.data = clk_get_rate(tegra->falcon_clk) / 1000; |
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if (rsp.data != msg->data) |
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rsp.cmd = MBOX_CMD_NAK; |
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else |
|
rsp.cmd = MBOX_CMD_ACK; |
|
|
|
break; |
|
|
|
case MBOX_CMD_INC_SSPI_CLOCK: |
|
case MBOX_CMD_DEC_SSPI_CLOCK: |
|
if (tegra->soc->scale_ss_clock) { |
|
err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000); |
|
if (err < 0) |
|
rsp.cmd = MBOX_CMD_NAK; |
|
else |
|
rsp.cmd = MBOX_CMD_ACK; |
|
|
|
rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000; |
|
} else { |
|
rsp.cmd = MBOX_CMD_ACK; |
|
rsp.data = msg->data; |
|
} |
|
|
|
break; |
|
|
|
case MBOX_CMD_SET_BW: |
|
/* |
|
* TODO: Request bandwidth once EMC scaling is supported. |
|
* Ignore for now since ACK/NAK is not required for SET_BW |
|
* messages. |
|
*/ |
|
break; |
|
|
|
case MBOX_CMD_SAVE_DFE_CTLE_CTX: |
|
err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data); |
|
if (err < 0) { |
|
dev_err(dev, "failed to save context for USB3#%u: %d\n", |
|
msg->data, err); |
|
rsp.cmd = MBOX_CMD_NAK; |
|
} else { |
|
rsp.cmd = MBOX_CMD_ACK; |
|
} |
|
|
|
rsp.data = msg->data; |
|
break; |
|
|
|
case MBOX_CMD_START_HSIC_IDLE: |
|
case MBOX_CMD_STOP_HSIC_IDLE: |
|
if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE) |
|
idle = false; |
|
else |
|
idle = true; |
|
|
|
mask = extract_field(msg->data, 1 + soc->ports.hsic.offset, |
|
soc->ports.hsic.count); |
|
|
|
for_each_set_bit(port, &mask, 32) { |
|
err = tegra_xusb_padctl_hsic_set_idle(padctl, port, |
|
idle); |
|
if (err < 0) |
|
break; |
|
} |
|
|
|
if (err < 0) { |
|
dev_err(dev, "failed to set HSIC#%u %s: %d\n", port, |
|
idle ? "idle" : "busy", err); |
|
rsp.cmd = MBOX_CMD_NAK; |
|
} else { |
|
rsp.cmd = MBOX_CMD_ACK; |
|
} |
|
|
|
rsp.data = msg->data; |
|
break; |
|
|
|
case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: |
|
case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: |
|
if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION) |
|
enable = false; |
|
else |
|
enable = true; |
|
|
|
mask = extract_field(msg->data, 1 + soc->ports.usb3.offset, |
|
soc->ports.usb3.count); |
|
|
|
for_each_set_bit(port, &mask, soc->ports.usb3.count) { |
|
err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl, |
|
port, |
|
enable); |
|
if (err < 0) |
|
break; |
|
|
|
/* |
|
* wait 500us for LFPS detector to be disabled before |
|
* sending ACK |
|
*/ |
|
if (!enable) |
|
usleep_range(500, 1000); |
|
} |
|
|
|
if (err < 0) { |
|
dev_err(dev, |
|
"failed to %s LFPS detection on USB3#%u: %d\n", |
|
enable ? "enable" : "disable", port, err); |
|
rsp.cmd = MBOX_CMD_NAK; |
|
} else { |
|
rsp.cmd = MBOX_CMD_ACK; |
|
} |
|
|
|
rsp.data = msg->data; |
|
break; |
|
|
|
default: |
|
dev_warn(dev, "unknown message: %#x\n", msg->cmd); |
|
break; |
|
} |
|
|
|
if (rsp.cmd) { |
|
const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK"; |
|
|
|
err = tegra_xusb_mbox_send(tegra, &rsp); |
|
if (err < 0) |
|
dev_err(dev, "failed to send %s: %d\n", cmd, err); |
|
} |
|
} |
|
|
|
static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) |
|
{ |
|
struct tegra_xusb *tegra = data; |
|
struct tegra_xusb_mbox_msg msg; |
|
u32 value; |
|
|
|
mutex_lock(&tegra->lock); |
|
|
|
value = fpci_readl(tegra, tegra->soc->mbox.data_out); |
|
tegra_xusb_mbox_unpack(&msg, value); |
|
|
|
value = fpci_readl(tegra, tegra->soc->mbox.cmd); |
|
value &= ~MBOX_DEST_SMI; |
|
fpci_writel(tegra, value, tegra->soc->mbox.cmd); |
|
|
|
/* clear mailbox owner if no ACK/NAK is required */ |
|
if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) |
|
fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); |
|
|
|
tegra_xusb_mbox_handle(tegra, &msg); |
|
|
|
mutex_unlock(&tegra->lock); |
|
return IRQ_HANDLED; |
|
} |
|
|
|
static void tegra_xusb_config(struct tegra_xusb *tegra) |
|
{ |
|
u32 regs = tegra->hcd->rsrc_start; |
|
u32 value; |
|
|
|
if (tegra->soc->has_ipfs) { |
|
value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0); |
|
value |= IPFS_EN_FPCI; |
|
ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0); |
|
|
|
usleep_range(10, 20); |
|
} |
|
|
|
/* Program BAR0 space */ |
|
value = fpci_readl(tegra, XUSB_CFG_4); |
|
value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); |
|
value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); |
|
fpci_writel(tegra, value, XUSB_CFG_4); |
|
|
|
usleep_range(100, 200); |
|
|
|
/* Enable bus master */ |
|
value = fpci_readl(tegra, XUSB_CFG_1); |
|
value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN; |
|
fpci_writel(tegra, value, XUSB_CFG_1); |
|
|
|
if (tegra->soc->has_ipfs) { |
|
/* Enable interrupt assertion */ |
|
value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0); |
|
value |= IPFS_IP_INT_MASK; |
|
ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0); |
|
|
|
/* Set hysteresis */ |
|
ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0); |
|
} |
|
} |
|
|
|
static int tegra_xusb_clk_enable(struct tegra_xusb *tegra) |
|
{ |
|
int err; |
|
|
|
err = clk_prepare_enable(tegra->pll_e); |
|
if (err < 0) |
|
return err; |
|
|
|
err = clk_prepare_enable(tegra->host_clk); |
|
if (err < 0) |
|
goto disable_plle; |
|
|
|
err = clk_prepare_enable(tegra->ss_clk); |
|
if (err < 0) |
|
goto disable_host; |
|
|
|
err = clk_prepare_enable(tegra->falcon_clk); |
|
if (err < 0) |
|
goto disable_ss; |
|
|
|
err = clk_prepare_enable(tegra->fs_src_clk); |
|
if (err < 0) |
|
goto disable_falc; |
|
|
|
err = clk_prepare_enable(tegra->hs_src_clk); |
|
if (err < 0) |
|
goto disable_fs_src; |
|
|
|
if (tegra->soc->scale_ss_clock) { |
|
err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED); |
|
if (err < 0) |
|
goto disable_hs_src; |
|
} |
|
|
|
return 0; |
|
|
|
disable_hs_src: |
|
clk_disable_unprepare(tegra->hs_src_clk); |
|
disable_fs_src: |
|
clk_disable_unprepare(tegra->fs_src_clk); |
|
disable_falc: |
|
clk_disable_unprepare(tegra->falcon_clk); |
|
disable_ss: |
|
clk_disable_unprepare(tegra->ss_clk); |
|
disable_host: |
|
clk_disable_unprepare(tegra->host_clk); |
|
disable_plle: |
|
clk_disable_unprepare(tegra->pll_e); |
|
return err; |
|
} |
|
|
|
static void tegra_xusb_clk_disable(struct tegra_xusb *tegra) |
|
{ |
|
clk_disable_unprepare(tegra->pll_e); |
|
clk_disable_unprepare(tegra->host_clk); |
|
clk_disable_unprepare(tegra->ss_clk); |
|
clk_disable_unprepare(tegra->falcon_clk); |
|
clk_disable_unprepare(tegra->fs_src_clk); |
|
clk_disable_unprepare(tegra->hs_src_clk); |
|
} |
|
|
|
static int tegra_xusb_phy_enable(struct tegra_xusb *tegra) |
|
{ |
|
unsigned int i; |
|
int err; |
|
|
|
for (i = 0; i < tegra->num_phys; i++) { |
|
err = phy_init(tegra->phys[i]); |
|
if (err) |
|
goto disable_phy; |
|
|
|
err = phy_power_on(tegra->phys[i]); |
|
if (err) { |
|
phy_exit(tegra->phys[i]); |
|
goto disable_phy; |
|
} |
|
} |
|
|
|
return 0; |
|
|
|
disable_phy: |
|
while (i--) { |
|
phy_power_off(tegra->phys[i]); |
|
phy_exit(tegra->phys[i]); |
|
} |
|
|
|
return err; |
|
} |
|
|
|
static void tegra_xusb_phy_disable(struct tegra_xusb *tegra) |
|
{ |
|
unsigned int i; |
|
|
|
for (i = 0; i < tegra->num_phys; i++) { |
|
phy_power_off(tegra->phys[i]); |
|
phy_exit(tegra->phys[i]); |
|
} |
|
} |
|
|
|
static int tegra_xusb_runtime_suspend(struct device *dev) |
|
{ |
|
struct tegra_xusb *tegra = dev_get_drvdata(dev); |
|
|
|
regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); |
|
tegra_xusb_clk_disable(tegra); |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra_xusb_runtime_resume(struct device *dev) |
|
{ |
|
struct tegra_xusb *tegra = dev_get_drvdata(dev); |
|
int err; |
|
|
|
err = tegra_xusb_clk_enable(tegra); |
|
if (err) { |
|
dev_err(dev, "failed to enable clocks: %d\n", err); |
|
return err; |
|
} |
|
|
|
err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies); |
|
if (err) { |
|
dev_err(dev, "failed to enable regulators: %d\n", err); |
|
goto disable_clk; |
|
} |
|
|
|
return 0; |
|
|
|
disable_clk: |
|
tegra_xusb_clk_disable(tegra); |
|
return err; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int tegra_xusb_init_context(struct tegra_xusb *tegra) |
|
{ |
|
const struct tegra_xusb_context_soc *soc = tegra->soc->context; |
|
|
|
tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets, |
|
sizeof(u32), GFP_KERNEL); |
|
if (!tegra->context.ipfs) |
|
return -ENOMEM; |
|
|
|
tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets, |
|
sizeof(u32), GFP_KERNEL); |
|
if (!tegra->context.fpci) |
|
return -ENOMEM; |
|
|
|
return 0; |
|
} |
|
#else |
|
static inline int tegra_xusb_init_context(struct tegra_xusb *tegra) |
|
{ |
|
return 0; |
|
} |
|
#endif |
|
|
|
static int tegra_xusb_request_firmware(struct tegra_xusb *tegra) |
|
{ |
|
struct tegra_xusb_fw_header *header; |
|
const struct firmware *fw; |
|
int err; |
|
|
|
err = request_firmware(&fw, tegra->soc->firmware, tegra->dev); |
|
if (err < 0) { |
|
dev_err(tegra->dev, "failed to request firmware: %d\n", err); |
|
return err; |
|
} |
|
|
|
/* Load Falcon controller with its firmware. */ |
|
header = (struct tegra_xusb_fw_header *)fw->data; |
|
tegra->fw.size = le32_to_cpu(header->fwimg_len); |
|
|
|
tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size, |
|
&tegra->fw.phys, GFP_KERNEL); |
|
if (!tegra->fw.virt) { |
|
dev_err(tegra->dev, "failed to allocate memory for firmware\n"); |
|
release_firmware(fw); |
|
return -ENOMEM; |
|
} |
|
|
|
header = (struct tegra_xusb_fw_header *)tegra->fw.virt; |
|
memcpy(tegra->fw.virt, fw->data, tegra->fw.size); |
|
release_firmware(fw); |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) |
|
{ |
|
unsigned int code_tag_blocks, code_size_blocks, code_blocks; |
|
struct xhci_cap_regs __iomem *cap = tegra->regs; |
|
struct tegra_xusb_fw_header *header; |
|
struct device *dev = tegra->dev; |
|
struct xhci_op_regs __iomem *op; |
|
unsigned long timeout; |
|
time64_t timestamp; |
|
struct tm time; |
|
u64 address; |
|
u32 value; |
|
int err; |
|
|
|
header = (struct tegra_xusb_fw_header *)tegra->fw.virt; |
|
op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase)); |
|
|
|
if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { |
|
dev_info(dev, "Firmware already loaded, Falcon state %#x\n", |
|
csb_readl(tegra, XUSB_FALC_CPUCTL)); |
|
return 0; |
|
} |
|
|
|
/* Program the size of DFI into ILOAD_ATTR. */ |
|
csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR); |
|
|
|
/* |
|
* Boot code of the firmware reads the ILOAD_BASE registers |
|
* to get to the start of the DFI in system memory. |
|
*/ |
|
address = tegra->fw.phys + sizeof(*header); |
|
csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI); |
|
csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO); |
|
|
|
/* Set BOOTPATH to 1 in APMAP. */ |
|
csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP); |
|
|
|
/* Invalidate L2IMEM. */ |
|
csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG); |
|
|
|
/* |
|
* Initiate fetch of bootcode from system memory into L2IMEM. |
|
* Program bootcode location and size in system memory. |
|
*/ |
|
code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag), |
|
IMEM_BLOCK_SIZE); |
|
code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize), |
|
IMEM_BLOCK_SIZE); |
|
code_blocks = code_tag_blocks + code_size_blocks; |
|
|
|
value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) << |
|
L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) | |
|
((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) << |
|
L2IMEMOP_SIZE_SRC_COUNT_SHIFT); |
|
csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE); |
|
|
|
/* Trigger L2IMEM load operation. */ |
|
csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT, |
|
XUSB_CSB_MP_L2IMEMOP_TRIG); |
|
|
|
/* Setup Falcon auto-fill. */ |
|
csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL); |
|
|
|
value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) << |
|
IMFILLRNG1_TAG_LO_SHIFT) | |
|
((code_blocks & IMFILLRNG1_TAG_MASK) << |
|
IMFILLRNG1_TAG_HI_SHIFT); |
|
csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1); |
|
|
|
csb_writel(tegra, 0, XUSB_FALC_DMACTL); |
|
|
|
/* wait for RESULT_VLD to get set */ |
|
#define tegra_csb_readl(offset) csb_readl(tegra, offset) |
|
err = readx_poll_timeout(tegra_csb_readl, |
|
XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value, |
|
value & L2IMEMOP_RESULT_VLD, 100, 10000); |
|
if (err < 0) { |
|
dev_err(dev, "DMA controller not ready %#010x\n", value); |
|
return err; |
|
} |
|
#undef tegra_csb_readl |
|
|
|
csb_writel(tegra, le32_to_cpu(header->boot_codetag), |
|
XUSB_FALC_BOOTVEC); |
|
|
|
/* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */ |
|
csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); |
|
|
|
timeout = jiffies + msecs_to_jiffies(200); |
|
|
|
do { |
|
value = readl(&op->status); |
|
if ((value & STS_CNR) == 0) |
|
break; |
|
|
|
usleep_range(1000, 2000); |
|
} while (time_is_after_jiffies(timeout)); |
|
|
|
value = readl(&op->status); |
|
if (value & STS_CNR) { |
|
value = csb_readl(tegra, XUSB_FALC_CPUCTL); |
|
dev_err(dev, "XHCI controller not read: %#010x\n", value); |
|
return -EIO; |
|
} |
|
|
|
timestamp = le32_to_cpu(header->fwimg_created_time); |
|
time64_to_tm(timestamp, 0, &time); |
|
|
|
dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n", |
|
time.tm_year + 1900, time.tm_mon + 1, time.tm_mday, |
|
time.tm_hour, time.tm_min, time.tm_sec); |
|
|
|
return 0; |
|
} |
|
|
|
static void tegra_xusb_powerdomain_remove(struct device *dev, |
|
struct tegra_xusb *tegra) |
|
{ |
|
if (tegra->genpd_dl_ss) |
|
device_link_del(tegra->genpd_dl_ss); |
|
if (tegra->genpd_dl_host) |
|
device_link_del(tegra->genpd_dl_host); |
|
if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss)) |
|
dev_pm_domain_detach(tegra->genpd_dev_ss, true); |
|
if (!IS_ERR_OR_NULL(tegra->genpd_dev_host)) |
|
dev_pm_domain_detach(tegra->genpd_dev_host, true); |
|
} |
|
|
|
static int tegra_xusb_powerdomain_init(struct device *dev, |
|
struct tegra_xusb *tegra) |
|
{ |
|
int err; |
|
|
|
tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host"); |
|
if (IS_ERR(tegra->genpd_dev_host)) { |
|
err = PTR_ERR(tegra->genpd_dev_host); |
|
dev_err(dev, "failed to get host pm-domain: %d\n", err); |
|
return err; |
|
} |
|
|
|
tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss"); |
|
if (IS_ERR(tegra->genpd_dev_ss)) { |
|
err = PTR_ERR(tegra->genpd_dev_ss); |
|
dev_err(dev, "failed to get superspeed pm-domain: %d\n", err); |
|
return err; |
|
} |
|
|
|
tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host, |
|
DL_FLAG_PM_RUNTIME | |
|
DL_FLAG_STATELESS); |
|
if (!tegra->genpd_dl_host) { |
|
dev_err(dev, "adding host device link failed!\n"); |
|
return -ENODEV; |
|
} |
|
|
|
tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss, |
|
DL_FLAG_PM_RUNTIME | |
|
DL_FLAG_STATELESS); |
|
if (!tegra->genpd_dl_ss) { |
|
dev_err(dev, "adding superspeed device link failed!\n"); |
|
return -ENODEV; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) |
|
{ |
|
struct tegra_xusb_mbox_msg msg; |
|
int err; |
|
|
|
/* Enable firmware messages from controller. */ |
|
msg.cmd = MBOX_CMD_MSG_ENABLED; |
|
msg.data = 0; |
|
|
|
err = tegra_xusb_mbox_send(tegra, &msg); |
|
if (err < 0) |
|
dev_err(tegra->dev, "failed to enable messages: %d\n", err); |
|
|
|
return err; |
|
} |
|
|
|
static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) |
|
{ |
|
int err; |
|
|
|
mutex_lock(&tegra->lock); |
|
err = __tegra_xusb_enable_firmware_messages(tegra); |
|
mutex_unlock(&tegra->lock); |
|
|
|
return err; |
|
} |
|
|
|
static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main, |
|
bool set) |
|
{ |
|
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); |
|
struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd; |
|
unsigned int wait = (!main && !set) ? 1000 : 10; |
|
u16 typeReq = set ? SetPortFeature : ClearPortFeature; |
|
u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1; |
|
u32 status; |
|
u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER; |
|
u32 status_val = set ? stat_power : 0; |
|
|
|
dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__, |
|
set ? "set" : "clear", main ? "HS" : "SS"); |
|
|
|
hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex, |
|
NULL, 0); |
|
|
|
do { |
|
tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex, |
|
(char *) &status, sizeof(status)); |
|
if (status_val == (status & stat_power)) |
|
break; |
|
|
|
if (!main && !set) |
|
usleep_range(600, 700); |
|
else |
|
usleep_range(10, 20); |
|
} while (--wait > 0); |
|
|
|
if (status_val != (status & stat_power)) |
|
dev_info(tegra->dev, "failed to %s %s PP %d\n", |
|
set ? "set" : "clear", |
|
main ? "HS" : "SS", status); |
|
} |
|
|
|
static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name, |
|
int port) |
|
{ |
|
unsigned int i, phy_count = 0; |
|
|
|
for (i = 0; i < tegra->soc->num_types; i++) { |
|
if (!strncmp(tegra->soc->phy_types[i].name, name, |
|
strlen(name))) |
|
return tegra->phys[phy_count+port]; |
|
|
|
phy_count += tegra->soc->phy_types[i].num; |
|
} |
|
|
|
return NULL; |
|
} |
|
|
|
static void tegra_xhci_id_work(struct work_struct *work) |
|
{ |
|
struct tegra_xusb *tegra = container_of(work, struct tegra_xusb, |
|
id_work); |
|
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); |
|
struct tegra_xusb_mbox_msg msg; |
|
struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", |
|
tegra->otg_usb2_port); |
|
u32 status; |
|
int ret; |
|
|
|
dev_dbg(tegra->dev, "host mode %s\n", tegra->host_mode ? "on" : "off"); |
|
|
|
mutex_lock(&tegra->lock); |
|
|
|
if (tegra->host_mode) |
|
phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST); |
|
else |
|
phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE); |
|
|
|
mutex_unlock(&tegra->lock); |
|
|
|
if (tegra->host_mode) { |
|
/* switch to host mode */ |
|
if (tegra->otg_usb3_port >= 0) { |
|
if (tegra->soc->otg_reset_sspi) { |
|
/* set PP=0 */ |
|
tegra_xhci_hc_driver.hub_control( |
|
xhci->shared_hcd, GetPortStatus, |
|
0, tegra->otg_usb3_port+1, |
|
(char *) &status, sizeof(status)); |
|
if (status & USB_SS_PORT_STAT_POWER) |
|
tegra_xhci_set_port_power(tegra, false, |
|
false); |
|
|
|
/* reset OTG port SSPI */ |
|
msg.cmd = MBOX_CMD_RESET_SSPI; |
|
msg.data = tegra->otg_usb3_port+1; |
|
|
|
ret = tegra_xusb_mbox_send(tegra, &msg); |
|
if (ret < 0) { |
|
dev_info(tegra->dev, |
|
"failed to RESET_SSPI %d\n", |
|
ret); |
|
} |
|
} |
|
|
|
tegra_xhci_set_port_power(tegra, false, true); |
|
} |
|
|
|
tegra_xhci_set_port_power(tegra, true, true); |
|
|
|
} else { |
|
if (tegra->otg_usb3_port >= 0) |
|
tegra_xhci_set_port_power(tegra, false, false); |
|
|
|
tegra_xhci_set_port_power(tegra, true, false); |
|
} |
|
} |
|
|
|
static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra, |
|
struct usb_phy *usbphy) |
|
{ |
|
unsigned int i; |
|
|
|
for (i = 0; i < tegra->num_usb_phys; i++) { |
|
if (tegra->usbphy[i] && usbphy == tegra->usbphy[i]) |
|
return i; |
|
} |
|
|
|
return -1; |
|
} |
|
|
|
static int tegra_xhci_id_notify(struct notifier_block *nb, |
|
unsigned long action, void *data) |
|
{ |
|
struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb, |
|
id_nb); |
|
struct usb_phy *usbphy = (struct usb_phy *)data; |
|
|
|
dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event); |
|
|
|
if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) || |
|
(!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) { |
|
dev_dbg(tegra->dev, "Same role(%d) received. Ignore", |
|
tegra->host_mode); |
|
return NOTIFY_OK; |
|
} |
|
|
|
tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy); |
|
tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion( |
|
tegra->padctl, |
|
tegra->otg_usb2_port); |
|
|
|
tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false; |
|
|
|
schedule_work(&tegra->id_work); |
|
|
|
return NOTIFY_OK; |
|
} |
|
|
|
static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra) |
|
{ |
|
unsigned int i; |
|
|
|
tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys, |
|
sizeof(*tegra->usbphy), GFP_KERNEL); |
|
if (!tegra->usbphy) |
|
return -ENOMEM; |
|
|
|
INIT_WORK(&tegra->id_work, tegra_xhci_id_work); |
|
tegra->id_nb.notifier_call = tegra_xhci_id_notify; |
|
tegra->otg_usb2_port = -EINVAL; |
|
tegra->otg_usb3_port = -EINVAL; |
|
|
|
for (i = 0; i < tegra->num_usb_phys; i++) { |
|
struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i); |
|
|
|
if (!phy) |
|
continue; |
|
|
|
tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev, |
|
phy->dev.of_node, |
|
&tegra->id_nb); |
|
if (!IS_ERR(tegra->usbphy[i])) { |
|
dev_dbg(tegra->dev, "usbphy-%d registered", i); |
|
otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self); |
|
} else { |
|
/* |
|
* usb-phy is optional, continue if its not available. |
|
*/ |
|
tegra->usbphy[i] = NULL; |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra) |
|
{ |
|
unsigned int i; |
|
|
|
cancel_work_sync(&tegra->id_work); |
|
|
|
for (i = 0; i < tegra->num_usb_phys; i++) |
|
if (tegra->usbphy[i]) |
|
otg_set_host(tegra->usbphy[i]->otg, NULL); |
|
} |
|
|
|
static int tegra_xusb_probe(struct platform_device *pdev) |
|
{ |
|
struct tegra_xusb *tegra; |
|
struct resource *regs; |
|
struct xhci_hcd *xhci; |
|
unsigned int i, j, k; |
|
struct phy *phy; |
|
int err; |
|
|
|
BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256); |
|
|
|
tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); |
|
if (!tegra) |
|
return -ENOMEM; |
|
|
|
tegra->soc = of_device_get_match_data(&pdev->dev); |
|
mutex_init(&tegra->lock); |
|
tegra->dev = &pdev->dev; |
|
|
|
err = tegra_xusb_init_context(tegra); |
|
if (err < 0) |
|
return err; |
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
tegra->regs = devm_ioremap_resource(&pdev->dev, regs); |
|
if (IS_ERR(tegra->regs)) |
|
return PTR_ERR(tegra->regs); |
|
|
|
tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1); |
|
if (IS_ERR(tegra->fpci_base)) |
|
return PTR_ERR(tegra->fpci_base); |
|
|
|
if (tegra->soc->has_ipfs) { |
|
tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2); |
|
if (IS_ERR(tegra->ipfs_base)) |
|
return PTR_ERR(tegra->ipfs_base); |
|
} |
|
|
|
tegra->xhci_irq = platform_get_irq(pdev, 0); |
|
if (tegra->xhci_irq < 0) |
|
return tegra->xhci_irq; |
|
|
|
tegra->mbox_irq = platform_get_irq(pdev, 1); |
|
if (tegra->mbox_irq < 0) |
|
return tegra->mbox_irq; |
|
|
|
tegra->padctl = tegra_xusb_padctl_get(&pdev->dev); |
|
if (IS_ERR(tegra->padctl)) |
|
return PTR_ERR(tegra->padctl); |
|
|
|
tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host"); |
|
if (IS_ERR(tegra->host_clk)) { |
|
err = PTR_ERR(tegra->host_clk); |
|
dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src"); |
|
if (IS_ERR(tegra->falcon_clk)) { |
|
err = PTR_ERR(tegra->falcon_clk); |
|
dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); |
|
if (IS_ERR(tegra->ss_clk)) { |
|
err = PTR_ERR(tegra->ss_clk); |
|
dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src"); |
|
if (IS_ERR(tegra->ss_src_clk)) { |
|
err = PTR_ERR(tegra->ss_src_clk); |
|
dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src"); |
|
if (IS_ERR(tegra->hs_src_clk)) { |
|
err = PTR_ERR(tegra->hs_src_clk); |
|
dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src"); |
|
if (IS_ERR(tegra->fs_src_clk)) { |
|
err = PTR_ERR(tegra->fs_src_clk); |
|
dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m"); |
|
if (IS_ERR(tegra->pll_u_480m)) { |
|
err = PTR_ERR(tegra->pll_u_480m); |
|
dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); |
|
if (IS_ERR(tegra->clk_m)) { |
|
err = PTR_ERR(tegra->clk_m); |
|
dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e"); |
|
if (IS_ERR(tegra->pll_e)) { |
|
err = PTR_ERR(tegra->pll_e); |
|
dev_err(&pdev->dev, "failed to get pll_e: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { |
|
tegra->host_rst = devm_reset_control_get(&pdev->dev, |
|
"xusb_host"); |
|
if (IS_ERR(tegra->host_rst)) { |
|
err = PTR_ERR(tegra->host_rst); |
|
dev_err(&pdev->dev, |
|
"failed to get xusb_host reset: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); |
|
if (IS_ERR(tegra->ss_rst)) { |
|
err = PTR_ERR(tegra->ss_rst); |
|
dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", |
|
err); |
|
goto put_padctl; |
|
} |
|
|
|
err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, |
|
tegra->ss_clk, |
|
tegra->ss_rst); |
|
if (err) { |
|
dev_err(&pdev->dev, |
|
"failed to enable XUSBA domain: %d\n", err); |
|
goto put_padctl; |
|
} |
|
|
|
err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, |
|
tegra->host_clk, |
|
tegra->host_rst); |
|
if (err) { |
|
tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); |
|
dev_err(&pdev->dev, |
|
"failed to enable XUSBC domain: %d\n", err); |
|
goto put_padctl; |
|
} |
|
} else { |
|
err = tegra_xusb_powerdomain_init(&pdev->dev, tegra); |
|
if (err) |
|
goto put_powerdomains; |
|
} |
|
|
|
tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies, |
|
sizeof(*tegra->supplies), GFP_KERNEL); |
|
if (!tegra->supplies) { |
|
err = -ENOMEM; |
|
goto put_powerdomains; |
|
} |
|
|
|
regulator_bulk_set_supply_names(tegra->supplies, |
|
tegra->soc->supply_names, |
|
tegra->soc->num_supplies); |
|
|
|
err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies, |
|
tegra->supplies); |
|
if (err) { |
|
dev_err(&pdev->dev, "failed to get regulators: %d\n", err); |
|
goto put_powerdomains; |
|
} |
|
|
|
for (i = 0; i < tegra->soc->num_types; i++) { |
|
if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4)) |
|
tegra->num_usb_phys = tegra->soc->phy_types[i].num; |
|
tegra->num_phys += tegra->soc->phy_types[i].num; |
|
} |
|
|
|
tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys, |
|
sizeof(*tegra->phys), GFP_KERNEL); |
|
if (!tegra->phys) { |
|
err = -ENOMEM; |
|
goto put_powerdomains; |
|
} |
|
|
|
for (i = 0, k = 0; i < tegra->soc->num_types; i++) { |
|
char prop[8]; |
|
|
|
for (j = 0; j < tegra->soc->phy_types[i].num; j++) { |
|
snprintf(prop, sizeof(prop), "%s-%d", |
|
tegra->soc->phy_types[i].name, j); |
|
|
|
phy = devm_phy_optional_get(&pdev->dev, prop); |
|
if (IS_ERR(phy)) { |
|
dev_err(&pdev->dev, |
|
"failed to get PHY %s: %ld\n", prop, |
|
PTR_ERR(phy)); |
|
err = PTR_ERR(phy); |
|
goto put_powerdomains; |
|
} |
|
|
|
tegra->phys[k++] = phy; |
|
} |
|
} |
|
|
|
tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev, |
|
dev_name(&pdev->dev)); |
|
if (!tegra->hcd) { |
|
err = -ENOMEM; |
|
goto put_powerdomains; |
|
} |
|
|
|
tegra->hcd->regs = tegra->regs; |
|
tegra->hcd->rsrc_start = regs->start; |
|
tegra->hcd->rsrc_len = resource_size(regs); |
|
|
|
/* |
|
* This must happen after usb_create_hcd(), because usb_create_hcd() |
|
* will overwrite the drvdata of the device with the hcd it creates. |
|
*/ |
|
platform_set_drvdata(pdev, tegra); |
|
|
|
err = tegra_xusb_phy_enable(tegra); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err); |
|
goto put_hcd; |
|
} |
|
|
|
/* |
|
* The XUSB Falcon microcontroller can only address 40 bits, so set |
|
* the DMA mask accordingly. |
|
*/ |
|
err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40)); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); |
|
goto disable_phy; |
|
} |
|
|
|
err = tegra_xusb_request_firmware(tegra); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to request firmware: %d\n", err); |
|
goto disable_phy; |
|
} |
|
|
|
pm_runtime_enable(&pdev->dev); |
|
|
|
if (!pm_runtime_enabled(&pdev->dev)) |
|
err = tegra_xusb_runtime_resume(&pdev->dev); |
|
else |
|
err = pm_runtime_get_sync(&pdev->dev); |
|
|
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to enable device: %d\n", err); |
|
goto free_firmware; |
|
} |
|
|
|
tegra_xusb_config(tegra); |
|
|
|
err = tegra_xusb_load_firmware(tegra); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to load firmware: %d\n", err); |
|
goto put_rpm; |
|
} |
|
|
|
err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err); |
|
goto put_rpm; |
|
} |
|
|
|
device_wakeup_enable(tegra->hcd->self.controller); |
|
|
|
xhci = hcd_to_xhci(tegra->hcd); |
|
|
|
xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver, |
|
&pdev->dev, |
|
dev_name(&pdev->dev), |
|
tegra->hcd); |
|
if (!xhci->shared_hcd) { |
|
dev_err(&pdev->dev, "failed to create shared HCD\n"); |
|
err = -ENOMEM; |
|
goto remove_usb2; |
|
} |
|
|
|
err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err); |
|
goto put_usb3; |
|
} |
|
|
|
err = tegra_xusb_enable_firmware_messages(tegra); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to enable messages: %d\n", err); |
|
goto remove_usb3; |
|
} |
|
|
|
err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq, |
|
tegra_xusb_mbox_irq, |
|
tegra_xusb_mbox_thread, 0, |
|
dev_name(&pdev->dev), tegra); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); |
|
goto remove_usb3; |
|
} |
|
|
|
err = tegra_xusb_init_usb_phy(tegra); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err); |
|
goto remove_usb3; |
|
} |
|
|
|
return 0; |
|
|
|
remove_usb3: |
|
usb_remove_hcd(xhci->shared_hcd); |
|
put_usb3: |
|
usb_put_hcd(xhci->shared_hcd); |
|
remove_usb2: |
|
usb_remove_hcd(tegra->hcd); |
|
put_rpm: |
|
if (!pm_runtime_status_suspended(&pdev->dev)) |
|
tegra_xusb_runtime_suspend(&pdev->dev); |
|
put_hcd: |
|
usb_put_hcd(tegra->hcd); |
|
free_firmware: |
|
dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, |
|
tegra->fw.phys); |
|
disable_phy: |
|
tegra_xusb_phy_disable(tegra); |
|
pm_runtime_disable(&pdev->dev); |
|
put_powerdomains: |
|
if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { |
|
tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); |
|
tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); |
|
} else { |
|
tegra_xusb_powerdomain_remove(&pdev->dev, tegra); |
|
} |
|
put_padctl: |
|
tegra_xusb_padctl_put(tegra->padctl); |
|
return err; |
|
} |
|
|
|
static int tegra_xusb_remove(struct platform_device *pdev) |
|
{ |
|
struct tegra_xusb *tegra = platform_get_drvdata(pdev); |
|
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); |
|
|
|
tegra_xusb_deinit_usb_phy(tegra); |
|
|
|
usb_remove_hcd(xhci->shared_hcd); |
|
usb_put_hcd(xhci->shared_hcd); |
|
xhci->shared_hcd = NULL; |
|
usb_remove_hcd(tegra->hcd); |
|
usb_put_hcd(tegra->hcd); |
|
|
|
dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, |
|
tegra->fw.phys); |
|
|
|
pm_runtime_put_sync(&pdev->dev); |
|
pm_runtime_disable(&pdev->dev); |
|
|
|
if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { |
|
tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); |
|
tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); |
|
} else { |
|
tegra_xusb_powerdomain_remove(&pdev->dev, tegra); |
|
} |
|
|
|
tegra_xusb_phy_disable(tegra); |
|
|
|
tegra_xusb_padctl_put(tegra->padctl); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static bool xhci_hub_ports_suspended(struct xhci_hub *hub) |
|
{ |
|
struct device *dev = hub->hcd->self.controller; |
|
bool status = true; |
|
unsigned int i; |
|
u32 value; |
|
|
|
for (i = 0; i < hub->num_ports; i++) { |
|
value = readl(hub->ports[i]->addr); |
|
if ((value & PORT_PE) == 0) |
|
continue; |
|
|
|
if ((value & PORT_PLS_MASK) != XDEV_U3) { |
|
dev_info(dev, "%u-%u isn't suspended: %#010x\n", |
|
hub->hcd->self.busnum, i + 1, value); |
|
status = false; |
|
} |
|
} |
|
|
|
return status; |
|
} |
|
|
|
static int tegra_xusb_check_ports(struct tegra_xusb *tegra) |
|
{ |
|
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); |
|
unsigned long flags; |
|
int err = 0; |
|
|
|
spin_lock_irqsave(&xhci->lock, flags); |
|
|
|
if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) || |
|
!xhci_hub_ports_suspended(&xhci->usb3_rhub)) |
|
err = -EBUSY; |
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags); |
|
|
|
return err; |
|
} |
|
|
|
static void tegra_xusb_save_context(struct tegra_xusb *tegra) |
|
{ |
|
const struct tegra_xusb_context_soc *soc = tegra->soc->context; |
|
struct tegra_xusb_context *ctx = &tegra->context; |
|
unsigned int i; |
|
|
|
if (soc->ipfs.num_offsets > 0) { |
|
for (i = 0; i < soc->ipfs.num_offsets; i++) |
|
ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]); |
|
} |
|
|
|
if (soc->fpci.num_offsets > 0) { |
|
for (i = 0; i < soc->fpci.num_offsets; i++) |
|
ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]); |
|
} |
|
} |
|
|
|
static void tegra_xusb_restore_context(struct tegra_xusb *tegra) |
|
{ |
|
const struct tegra_xusb_context_soc *soc = tegra->soc->context; |
|
struct tegra_xusb_context *ctx = &tegra->context; |
|
unsigned int i; |
|
|
|
if (soc->fpci.num_offsets > 0) { |
|
for (i = 0; i < soc->fpci.num_offsets; i++) |
|
fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]); |
|
} |
|
|
|
if (soc->ipfs.num_offsets > 0) { |
|
for (i = 0; i < soc->ipfs.num_offsets; i++) |
|
ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]); |
|
} |
|
} |
|
|
|
static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool wakeup) |
|
{ |
|
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); |
|
int err; |
|
|
|
err = tegra_xusb_check_ports(tegra); |
|
if (err < 0) { |
|
dev_err(tegra->dev, "not all ports suspended: %d\n", err); |
|
return err; |
|
} |
|
|
|
err = xhci_suspend(xhci, wakeup); |
|
if (err < 0) { |
|
dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err); |
|
return err; |
|
} |
|
|
|
tegra_xusb_save_context(tegra); |
|
tegra_xusb_phy_disable(tegra); |
|
tegra_xusb_clk_disable(tegra); |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool wakeup) |
|
{ |
|
struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); |
|
int err; |
|
|
|
err = tegra_xusb_clk_enable(tegra); |
|
if (err < 0) { |
|
dev_err(tegra->dev, "failed to enable clocks: %d\n", err); |
|
return err; |
|
} |
|
|
|
err = tegra_xusb_phy_enable(tegra); |
|
if (err < 0) { |
|
dev_err(tegra->dev, "failed to enable PHYs: %d\n", err); |
|
goto disable_clk; |
|
} |
|
|
|
tegra_xusb_config(tegra); |
|
tegra_xusb_restore_context(tegra); |
|
|
|
err = tegra_xusb_load_firmware(tegra); |
|
if (err < 0) { |
|
dev_err(tegra->dev, "failed to load firmware: %d\n", err); |
|
goto disable_phy; |
|
} |
|
|
|
err = __tegra_xusb_enable_firmware_messages(tegra); |
|
if (err < 0) { |
|
dev_err(tegra->dev, "failed to enable messages: %d\n", err); |
|
goto disable_phy; |
|
} |
|
|
|
err = xhci_resume(xhci, true); |
|
if (err < 0) { |
|
dev_err(tegra->dev, "failed to resume XHCI: %d\n", err); |
|
goto disable_phy; |
|
} |
|
|
|
return 0; |
|
|
|
disable_phy: |
|
tegra_xusb_phy_disable(tegra); |
|
disable_clk: |
|
tegra_xusb_clk_disable(tegra); |
|
return err; |
|
} |
|
|
|
static int tegra_xusb_suspend(struct device *dev) |
|
{ |
|
struct tegra_xusb *tegra = dev_get_drvdata(dev); |
|
bool wakeup = device_may_wakeup(dev); |
|
int err; |
|
|
|
synchronize_irq(tegra->mbox_irq); |
|
|
|
mutex_lock(&tegra->lock); |
|
err = tegra_xusb_enter_elpg(tegra, wakeup); |
|
mutex_unlock(&tegra->lock); |
|
|
|
return err; |
|
} |
|
|
|
static int tegra_xusb_resume(struct device *dev) |
|
{ |
|
struct tegra_xusb *tegra = dev_get_drvdata(dev); |
|
bool wakeup = device_may_wakeup(dev); |
|
int err; |
|
|
|
mutex_lock(&tegra->lock); |
|
err = tegra_xusb_exit_elpg(tegra, wakeup); |
|
mutex_unlock(&tegra->lock); |
|
|
|
return err; |
|
} |
|
#endif |
|
|
|
static const struct dev_pm_ops tegra_xusb_pm_ops = { |
|
SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend, |
|
tegra_xusb_runtime_resume, NULL) |
|
SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume) |
|
}; |
|
|
|
static const char * const tegra124_supply_names[] = { |
|
"avddio-pex", |
|
"dvddio-pex", |
|
"avdd-usb", |
|
"hvdd-usb-ss", |
|
}; |
|
|
|
static const struct tegra_xusb_phy_type tegra124_phy_types[] = { |
|
{ .name = "usb3", .num = 2, }, |
|
{ .name = "usb2", .num = 3, }, |
|
{ .name = "hsic", .num = 2, }, |
|
}; |
|
|
|
static const unsigned int tegra124_xusb_context_ipfs[] = { |
|
IPFS_XUSB_HOST_MSI_BAR_SZ_0, |
|
IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0, |
|
IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0, |
|
IPFS_XUSB_HOST_MSI_VEC0_0, |
|
IPFS_XUSB_HOST_MSI_EN_VEC0_0, |
|
IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0, |
|
IPFS_XUSB_HOST_INTR_MASK_0, |
|
IPFS_XUSB_HOST_INTR_ENABLE_0, |
|
IPFS_XUSB_HOST_UFPCI_CONFIG_0, |
|
IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0, |
|
IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0, |
|
}; |
|
|
|
static const unsigned int tegra124_xusb_context_fpci[] = { |
|
XUSB_CFG_ARU_CONTEXT_HS_PLS, |
|
XUSB_CFG_ARU_CONTEXT_FS_PLS, |
|
XUSB_CFG_ARU_CONTEXT_HSFS_SPEED, |
|
XUSB_CFG_ARU_CONTEXT_HSFS_PP, |
|
XUSB_CFG_ARU_CONTEXT, |
|
XUSB_CFG_AXI_CFG, |
|
XUSB_CFG_24, |
|
XUSB_CFG_16, |
|
}; |
|
|
|
static const struct tegra_xusb_context_soc tegra124_xusb_context = { |
|
.ipfs = { |
|
.num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs), |
|
.offsets = tegra124_xusb_context_ipfs, |
|
}, |
|
.fpci = { |
|
.num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), |
|
.offsets = tegra124_xusb_context_fpci, |
|
}, |
|
}; |
|
|
|
static const struct tegra_xusb_soc tegra124_soc = { |
|
.firmware = "nvidia/tegra124/xusb.bin", |
|
.supply_names = tegra124_supply_names, |
|
.num_supplies = ARRAY_SIZE(tegra124_supply_names), |
|
.phy_types = tegra124_phy_types, |
|
.num_types = ARRAY_SIZE(tegra124_phy_types), |
|
.context = &tegra124_xusb_context, |
|
.ports = { |
|
.usb2 = { .offset = 4, .count = 4, }, |
|
.hsic = { .offset = 6, .count = 2, }, |
|
.usb3 = { .offset = 0, .count = 2, }, |
|
}, |
|
.scale_ss_clock = true, |
|
.has_ipfs = true, |
|
.otg_reset_sspi = false, |
|
.mbox = { |
|
.cmd = 0xe4, |
|
.data_in = 0xe8, |
|
.data_out = 0xec, |
|
.owner = 0xf0, |
|
}, |
|
}; |
|
MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); |
|
|
|
static const char * const tegra210_supply_names[] = { |
|
"dvddio-pex", |
|
"hvddio-pex", |
|
"avdd-usb", |
|
}; |
|
|
|
static const struct tegra_xusb_phy_type tegra210_phy_types[] = { |
|
{ .name = "usb3", .num = 4, }, |
|
{ .name = "usb2", .num = 4, }, |
|
{ .name = "hsic", .num = 1, }, |
|
}; |
|
|
|
static const struct tegra_xusb_soc tegra210_soc = { |
|
.firmware = "nvidia/tegra210/xusb.bin", |
|
.supply_names = tegra210_supply_names, |
|
.num_supplies = ARRAY_SIZE(tegra210_supply_names), |
|
.phy_types = tegra210_phy_types, |
|
.num_types = ARRAY_SIZE(tegra210_phy_types), |
|
.context = &tegra124_xusb_context, |
|
.ports = { |
|
.usb2 = { .offset = 4, .count = 4, }, |
|
.hsic = { .offset = 8, .count = 1, }, |
|
.usb3 = { .offset = 0, .count = 4, }, |
|
}, |
|
.scale_ss_clock = false, |
|
.has_ipfs = true, |
|
.otg_reset_sspi = true, |
|
.mbox = { |
|
.cmd = 0xe4, |
|
.data_in = 0xe8, |
|
.data_out = 0xec, |
|
.owner = 0xf0, |
|
}, |
|
}; |
|
MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); |
|
|
|
static const char * const tegra186_supply_names[] = { |
|
}; |
|
MODULE_FIRMWARE("nvidia/tegra186/xusb.bin"); |
|
|
|
static const struct tegra_xusb_phy_type tegra186_phy_types[] = { |
|
{ .name = "usb3", .num = 3, }, |
|
{ .name = "usb2", .num = 3, }, |
|
{ .name = "hsic", .num = 1, }, |
|
}; |
|
|
|
static const struct tegra_xusb_context_soc tegra186_xusb_context = { |
|
.fpci = { |
|
.num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), |
|
.offsets = tegra124_xusb_context_fpci, |
|
}, |
|
}; |
|
|
|
static const struct tegra_xusb_soc tegra186_soc = { |
|
.firmware = "nvidia/tegra186/xusb.bin", |
|
.supply_names = tegra186_supply_names, |
|
.num_supplies = ARRAY_SIZE(tegra186_supply_names), |
|
.phy_types = tegra186_phy_types, |
|
.num_types = ARRAY_SIZE(tegra186_phy_types), |
|
.context = &tegra186_xusb_context, |
|
.ports = { |
|
.usb3 = { .offset = 0, .count = 3, }, |
|
.usb2 = { .offset = 3, .count = 3, }, |
|
.hsic = { .offset = 6, .count = 1, }, |
|
}, |
|
.scale_ss_clock = false, |
|
.has_ipfs = false, |
|
.otg_reset_sspi = false, |
|
.mbox = { |
|
.cmd = 0xe4, |
|
.data_in = 0xe8, |
|
.data_out = 0xec, |
|
.owner = 0xf0, |
|
}, |
|
.lpm_support = true, |
|
}; |
|
|
|
static const char * const tegra194_supply_names[] = { |
|
}; |
|
|
|
static const struct tegra_xusb_phy_type tegra194_phy_types[] = { |
|
{ .name = "usb3", .num = 4, }, |
|
{ .name = "usb2", .num = 4, }, |
|
}; |
|
|
|
static const struct tegra_xusb_soc tegra194_soc = { |
|
.firmware = "nvidia/tegra194/xusb.bin", |
|
.supply_names = tegra194_supply_names, |
|
.num_supplies = ARRAY_SIZE(tegra194_supply_names), |
|
.phy_types = tegra194_phy_types, |
|
.num_types = ARRAY_SIZE(tegra194_phy_types), |
|
.context = &tegra186_xusb_context, |
|
.ports = { |
|
.usb3 = { .offset = 0, .count = 4, }, |
|
.usb2 = { .offset = 4, .count = 4, }, |
|
}, |
|
.scale_ss_clock = false, |
|
.has_ipfs = false, |
|
.otg_reset_sspi = false, |
|
.mbox = { |
|
.cmd = 0x68, |
|
.data_in = 0x6c, |
|
.data_out = 0x70, |
|
.owner = 0x74, |
|
}, |
|
.lpm_support = true, |
|
}; |
|
MODULE_FIRMWARE("nvidia/tegra194/xusb.bin"); |
|
|
|
static const struct of_device_id tegra_xusb_of_match[] = { |
|
{ .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, |
|
{ .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, |
|
{ .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, |
|
{ .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, tegra_xusb_of_match); |
|
|
|
static struct platform_driver tegra_xusb_driver = { |
|
.probe = tegra_xusb_probe, |
|
.remove = tegra_xusb_remove, |
|
.driver = { |
|
.name = "tegra-xusb", |
|
.pm = &tegra_xusb_pm_ops, |
|
.of_match_table = tegra_xusb_of_match, |
|
}, |
|
}; |
|
|
|
static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci) |
|
{ |
|
struct tegra_xusb *tegra = dev_get_drvdata(dev); |
|
|
|
xhci->quirks |= XHCI_PLAT; |
|
if (tegra && tegra->soc->lpm_support) |
|
xhci->quirks |= XHCI_LPM_SUPPORT; |
|
} |
|
|
|
static int tegra_xhci_setup(struct usb_hcd *hcd) |
|
{ |
|
return xhci_gen_setup(hcd, tegra_xhci_quirks); |
|
} |
|
|
|
static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = { |
|
.reset = tegra_xhci_setup, |
|
}; |
|
|
|
static int __init tegra_xusb_init(void) |
|
{ |
|
xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides); |
|
|
|
return platform_driver_register(&tegra_xusb_driver); |
|
} |
|
module_init(tegra_xusb_init); |
|
|
|
static void __exit tegra_xusb_exit(void) |
|
{ |
|
platform_driver_unregister(&tegra_xusb_driver); |
|
} |
|
module_exit(tegra_xusb_exit); |
|
|
|
MODULE_AUTHOR("Andrew Bresticker <[email protected]>"); |
|
MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|