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743 lines
24 KiB
743 lines
24 KiB
/* SPDX-License-Identifier: GPL-1.0+ */ |
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/* |
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* OHCI HCD (Host Controller Driver) for USB. |
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* |
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* (C) Copyright 1999 Roman Weissgaerber <[email protected]> |
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* (C) Copyright 2000-2002 David Brownell <[email protected]> |
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* |
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* This file is licenced under the GPL. |
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*/ |
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|
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/* |
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* __hc32 and __hc16 are "Host Controller" types, they may be equivalent to |
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* __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the |
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* host controller implementation. |
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*/ |
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typedef __u32 __bitwise __hc32; |
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typedef __u16 __bitwise __hc16; |
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/* |
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* OHCI Endpoint Descriptor (ED) ... holds TD queue |
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* See OHCI spec, section 4.2 |
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* |
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* This is a "Queue Head" for those transfers, which is why |
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* both EHCI and UHCI call similar structures a "QH". |
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*/ |
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struct ed { |
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/* first fields are hardware-specified */ |
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__hc32 hwINFO; /* endpoint config bitmap */ |
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/* info bits defined by hcd */ |
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#define ED_DEQUEUE (1 << 27) |
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/* info bits defined by the hardware */ |
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#define ED_ISO (1 << 15) |
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#define ED_SKIP (1 << 14) |
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#define ED_LOWSPEED (1 << 13) |
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#define ED_OUT (0x01 << 11) |
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#define ED_IN (0x02 << 11) |
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__hc32 hwTailP; /* tail of TD list */ |
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__hc32 hwHeadP; /* head of TD list (hc r/w) */ |
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#define ED_C (0x02) /* toggle carry */ |
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#define ED_H (0x01) /* halted */ |
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__hc32 hwNextED; /* next ED in list */ |
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/* rest are purely for the driver's use */ |
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dma_addr_t dma; /* addr of ED */ |
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struct td *dummy; /* next TD to activate */ |
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/* host's view of schedule */ |
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struct ed *ed_next; /* on schedule or rm_list */ |
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struct ed *ed_prev; /* for non-interrupt EDs */ |
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struct list_head td_list; /* "shadow list" of our TDs */ |
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struct list_head in_use_list; |
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/* create --> IDLE --> OPER --> ... --> IDLE --> destroy |
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* usually: OPER --> UNLINK --> (IDLE | OPER) --> ... |
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*/ |
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u8 state; /* ED_{IDLE,UNLINK,OPER} */ |
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#define ED_IDLE 0x00 /* NOT linked to HC */ |
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#define ED_UNLINK 0x01 /* being unlinked from hc */ |
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#define ED_OPER 0x02 /* IS linked to hc */ |
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u8 type; /* PIPE_{BULK,...} */ |
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/* periodic scheduling params (for intr and iso) */ |
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u8 branch; |
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u16 interval; |
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u16 load; |
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u16 last_iso; /* iso only */ |
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/* HC may see EDs on rm_list until next frame (frame_no == tick) */ |
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u16 tick; |
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/* Detect TDs not added to the done queue */ |
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unsigned takeback_wdh_cnt; |
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struct td *pending_td; |
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#define OKAY_TO_TAKEBACK(ohci, ed) \ |
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((int) (ohci->wdh_cnt - ed->takeback_wdh_cnt) >= 0) |
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} __attribute__ ((aligned(16))); |
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#define ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */ |
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/* |
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* OHCI Transfer Descriptor (TD) ... one per transfer segment |
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* See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt) |
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* and 4.3.2 (iso) |
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*/ |
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struct td { |
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/* first fields are hardware-specified */ |
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__hc32 hwINFO; /* transfer info bitmask */ |
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/* hwINFO bits for both general and iso tds: */ |
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#define TD_CC 0xf0000000 /* condition code */ |
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#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) |
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//#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) |
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#define TD_DI 0x00E00000 /* frames before interrupt */ |
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#define TD_DI_SET(X) (((X) & 0x07)<< 21) |
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/* these two bits are available for definition/use by HCDs in both |
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* general and iso tds ... others are available for only one type |
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*/ |
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#define TD_DONE 0x00020000 /* retired to donelist */ |
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#define TD_ISO 0x00010000 /* copy of ED_ISO */ |
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/* hwINFO bits for general tds: */ |
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#define TD_EC 0x0C000000 /* error count */ |
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#define TD_T 0x03000000 /* data toggle state */ |
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#define TD_T_DATA0 0x02000000 /* DATA0 */ |
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#define TD_T_DATA1 0x03000000 /* DATA1 */ |
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#define TD_T_TOGGLE 0x00000000 /* uses ED_C */ |
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#define TD_DP 0x00180000 /* direction/pid */ |
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#define TD_DP_SETUP 0x00000000 /* SETUP pid */ |
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#define TD_DP_IN 0x00100000 /* IN pid */ |
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#define TD_DP_OUT 0x00080000 /* OUT pid */ |
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/* 0x00180000 rsvd */ |
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#define TD_R 0x00040000 /* round: short packets OK? */ |
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/* (no hwINFO #defines yet for iso tds) */ |
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__hc32 hwCBP; /* Current Buffer Pointer (or 0) */ |
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__hc32 hwNextTD; /* Next TD Pointer */ |
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__hc32 hwBE; /* Memory Buffer End Pointer */ |
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/* PSW is only for ISO. Only 1 PSW entry is used, but on |
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* big-endian PPC hardware that's the second entry. |
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*/ |
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#define MAXPSW 2 |
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__hc16 hwPSW [MAXPSW]; |
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/* rest are purely for the driver's use */ |
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__u8 index; |
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struct ed *ed; |
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struct td *td_hash; /* dma-->td hashtable */ |
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struct td *next_dl_td; |
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struct urb *urb; |
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dma_addr_t td_dma; /* addr of this TD */ |
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dma_addr_t data_dma; /* addr of data it points to */ |
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struct list_head td_list; /* "shadow list", TDs on same ED */ |
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} __attribute__ ((aligned(32))); /* c/b/i need 16; only iso needs 32 */ |
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#define TD_MASK ((u32)~0x1f) /* strip hw status in low addr bits */ |
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/* |
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* Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW |
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*/ |
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#define TD_CC_NOERROR 0x00 |
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#define TD_CC_CRC 0x01 |
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#define TD_CC_BITSTUFFING 0x02 |
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#define TD_CC_DATATOGGLEM 0x03 |
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#define TD_CC_STALL 0x04 |
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#define TD_DEVNOTRESP 0x05 |
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#define TD_PIDCHECKFAIL 0x06 |
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#define TD_UNEXPECTEDPID 0x07 |
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#define TD_DATAOVERRUN 0x08 |
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#define TD_DATAUNDERRUN 0x09 |
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/* 0x0A, 0x0B reserved for hardware */ |
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#define TD_BUFFEROVERRUN 0x0C |
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#define TD_BUFFERUNDERRUN 0x0D |
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/* 0x0E, 0x0F reserved for HCD */ |
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#define TD_NOTACCESSED 0x0F |
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/* map OHCI TD status codes (CC) to errno values */ |
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static const int __maybe_unused cc_to_error [16] = { |
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/* No Error */ 0, |
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/* CRC Error */ -EILSEQ, |
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/* Bit Stuff */ -EPROTO, |
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/* Data Togg */ -EILSEQ, |
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/* Stall */ -EPIPE, |
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/* DevNotResp */ -ETIME, |
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/* PIDCheck */ -EPROTO, |
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/* UnExpPID */ -EPROTO, |
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/* DataOver */ -EOVERFLOW, |
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/* DataUnder */ -EREMOTEIO, |
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/* (for hw) */ -EIO, |
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/* (for hw) */ -EIO, |
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/* BufferOver */ -ECOMM, |
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/* BuffUnder */ -ENOSR, |
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/* (for HCD) */ -EALREADY, |
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/* (for HCD) */ -EALREADY |
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}; |
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/* |
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* The HCCA (Host Controller Communications Area) is a 256 byte |
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* structure defined section 4.4.1 of the OHCI spec. The HC is |
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* told the base address of it. It must be 256-byte aligned. |
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*/ |
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struct ohci_hcca { |
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#define NUM_INTS 32 |
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__hc32 int_table [NUM_INTS]; /* periodic schedule */ |
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/* |
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* OHCI defines u16 frame_no, followed by u16 zero pad. |
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* Since some processors can't do 16 bit bus accesses, |
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* portable access must be a 32 bits wide. |
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*/ |
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__hc32 frame_no; /* current frame number */ |
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__hc32 done_head; /* info returned for an interrupt */ |
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u8 reserved_for_hc [116]; |
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u8 what [4]; /* spec only identifies 252 bytes :) */ |
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} __attribute__ ((aligned(256))); |
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/* |
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* This is the structure of the OHCI controller's memory mapped I/O region. |
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* You must use readl() and writel() (in <asm/io.h>) to access these fields!! |
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* Layout is in section 7 (and appendix B) of the spec. |
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*/ |
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struct ohci_regs { |
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/* control and status registers (section 7.1) */ |
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__hc32 revision; |
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__hc32 control; |
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__hc32 cmdstatus; |
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__hc32 intrstatus; |
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__hc32 intrenable; |
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__hc32 intrdisable; |
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/* memory pointers (section 7.2) */ |
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__hc32 hcca; |
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__hc32 ed_periodcurrent; |
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__hc32 ed_controlhead; |
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__hc32 ed_controlcurrent; |
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__hc32 ed_bulkhead; |
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__hc32 ed_bulkcurrent; |
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__hc32 donehead; |
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/* frame counters (section 7.3) */ |
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__hc32 fminterval; |
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__hc32 fmremaining; |
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__hc32 fmnumber; |
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__hc32 periodicstart; |
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__hc32 lsthresh; |
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/* Root hub ports (section 7.4) */ |
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struct ohci_roothub_regs { |
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__hc32 a; |
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__hc32 b; |
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__hc32 status; |
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#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports (RH_A_NDP) */ |
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__hc32 portstatus [MAX_ROOT_PORTS]; |
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} roothub; |
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/* and optional "legacy support" registers (appendix B) at 0x0100 */ |
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} __attribute__ ((aligned(32))); |
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/* OHCI CONTROL AND STATUS REGISTER MASKS */ |
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/* |
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* HcControl (control) register masks |
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*/ |
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#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ |
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#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ |
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#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ |
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#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ |
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#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ |
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#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ |
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#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ |
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#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ |
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#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ |
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/* pre-shifted values for HCFS */ |
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# define OHCI_USB_RESET (0 << 6) |
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# define OHCI_USB_RESUME (1 << 6) |
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# define OHCI_USB_OPER (2 << 6) |
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# define OHCI_USB_SUSPEND (3 << 6) |
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/* |
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* HcCommandStatus (cmdstatus) register masks |
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*/ |
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#define OHCI_HCR (1 << 0) /* host controller reset */ |
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#define OHCI_CLF (1 << 1) /* control list filled */ |
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#define OHCI_BLF (1 << 2) /* bulk list filled */ |
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#define OHCI_OCR (1 << 3) /* ownership change request */ |
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#define OHCI_SOC (3 << 16) /* scheduling overrun count */ |
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/* |
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* masks used with interrupt registers: |
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* HcInterruptStatus (intrstatus) |
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* HcInterruptEnable (intrenable) |
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* HcInterruptDisable (intrdisable) |
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*/ |
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#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ |
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#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ |
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#define OHCI_INTR_SF (1 << 2) /* start frame */ |
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#define OHCI_INTR_RD (1 << 3) /* resume detect */ |
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#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ |
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#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ |
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#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ |
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#define OHCI_INTR_OC (1 << 30) /* ownership change */ |
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#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ |
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/* OHCI ROOT HUB REGISTER MASKS */ |
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/* roothub.portstatus [i] bits */ |
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#define RH_PS_CCS 0x00000001 /* current connect status */ |
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#define RH_PS_PES 0x00000002 /* port enable status*/ |
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#define RH_PS_PSS 0x00000004 /* port suspend status */ |
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#define RH_PS_POCI 0x00000008 /* port over current indicator */ |
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#define RH_PS_PRS 0x00000010 /* port reset status */ |
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#define RH_PS_PPS 0x00000100 /* port power status */ |
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#define RH_PS_LSDA 0x00000200 /* low speed device attached */ |
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#define RH_PS_CSC 0x00010000 /* connect status change */ |
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#define RH_PS_PESC 0x00020000 /* port enable status change */ |
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#define RH_PS_PSSC 0x00040000 /* port suspend status change */ |
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#define RH_PS_OCIC 0x00080000 /* over current indicator change */ |
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#define RH_PS_PRSC 0x00100000 /* port reset status change */ |
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/* roothub.status bits */ |
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#define RH_HS_LPS 0x00000001 /* local power status */ |
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#define RH_HS_OCI 0x00000002 /* over current indicator */ |
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#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ |
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#define RH_HS_LPSC 0x00010000 /* local power status change */ |
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#define RH_HS_OCIC 0x00020000 /* over current indicator change */ |
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#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ |
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/* roothub.b masks */ |
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#define RH_B_DR 0x0000ffff /* device removable flags */ |
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#define RH_B_PPCM 0xffff0000 /* port power control mask */ |
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/* roothub.a masks */ |
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#define RH_A_NDP (0xff << 0) /* number of downstream ports */ |
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#define RH_A_PSM (1 << 8) /* power switching mode */ |
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#define RH_A_NPS (1 << 9) /* no power switching */ |
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#define RH_A_DT (1 << 10) /* device type (mbz) */ |
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#define RH_A_OCPM (1 << 11) /* over current protection mode */ |
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#define RH_A_NOCP (1 << 12) /* no over current protection */ |
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#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ |
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/* hcd-private per-urb state */ |
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typedef struct urb_priv { |
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struct ed *ed; |
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u16 length; // # tds in this request |
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u16 td_cnt; // tds already serviced |
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struct list_head pending; |
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struct td *td[]; // all TDs in this request |
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} urb_priv_t; |
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#define TD_HASH_SIZE 64 /* power'o'two */ |
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// sizeof (struct td) ~= 64 == 2^6 ... |
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#define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE) |
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/* |
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* This is the full ohci controller description |
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* |
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* Note how the "proper" USB information is just |
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* a subset of what the full implementation needs. (Linus) |
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*/ |
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enum ohci_rh_state { |
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OHCI_RH_HALTED, |
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OHCI_RH_SUSPENDED, |
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OHCI_RH_RUNNING |
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}; |
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struct ohci_hcd { |
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spinlock_t lock; |
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/* |
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* I/O memory used to communicate with the HC (dma-consistent) |
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*/ |
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struct ohci_regs __iomem *regs; |
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/* |
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* main memory used to communicate with the HC (dma-consistent). |
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* hcd adds to schedule for a live hc any time, but removals finish |
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* only at the start of the next frame. |
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*/ |
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struct ohci_hcca *hcca; |
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dma_addr_t hcca_dma; |
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struct ed *ed_rm_list; /* to be removed */ |
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struct ed *ed_bulktail; /* last in bulk list */ |
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struct ed *ed_controltail; /* last in ctrl list */ |
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struct ed *periodic [NUM_INTS]; /* shadow int_table */ |
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void (*start_hnp)(struct ohci_hcd *ohci); |
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/* |
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* memory management for queue data structures |
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* |
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* @td_cache and @ed_cache are %NULL if &usb_hcd.localmem_pool is used. |
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*/ |
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struct dma_pool *td_cache; |
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struct dma_pool *ed_cache; |
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struct td *td_hash [TD_HASH_SIZE]; |
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struct td *dl_start, *dl_end; /* the done list */ |
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struct list_head pending; |
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struct list_head eds_in_use; /* all EDs with at least 1 TD */ |
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/* |
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* driver state |
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*/ |
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enum ohci_rh_state rh_state; |
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int num_ports; |
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int load [NUM_INTS]; |
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u32 hc_control; /* copy of hc control reg */ |
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unsigned long next_statechange; /* suspend/resume */ |
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u32 fminterval; /* saved register */ |
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unsigned autostop:1; /* rh auto stopping/stopped */ |
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unsigned working:1; |
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unsigned restart_work:1; |
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unsigned long flags; /* for HC bugs */ |
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#define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */ |
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#define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */ |
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#define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */ |
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#define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */ |
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#define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */ |
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#define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/ |
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#define OHCI_QUIRK_NEC 0x40 /* lost interrupts */ |
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#define OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */ |
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#define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */ |
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#define OHCI_QUIRK_AMD_PLL 0x200 /* AMD PLL quirk*/ |
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#define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */ |
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#define OHCI_QUIRK_GLOBAL_SUSPEND 0x800 /* must suspend ports */ |
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#define OHCI_QUIRK_QEMU 0x1000 /* relax timing expectations */ |
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// there are also chip quirks/bugs in init logic |
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unsigned prev_frame_no; |
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unsigned wdh_cnt, prev_wdh_cnt; |
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u32 prev_donehead; |
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struct timer_list io_watchdog; |
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struct work_struct nec_work; /* Worker for NEC quirk */ |
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struct dentry *debug_dir; |
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/* platform-specific data -- must come last */ |
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unsigned long priv[] __aligned(sizeof(s64)); |
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}; |
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#ifdef CONFIG_USB_PCI |
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static inline int quirk_nec(struct ohci_hcd *ohci) |
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{ |
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return ohci->flags & OHCI_QUIRK_NEC; |
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} |
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static inline int quirk_zfmicro(struct ohci_hcd *ohci) |
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{ |
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return ohci->flags & OHCI_QUIRK_ZFMICRO; |
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} |
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static inline int quirk_amdiso(struct ohci_hcd *ohci) |
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{ |
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return ohci->flags & OHCI_QUIRK_AMD_PLL; |
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} |
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static inline int quirk_amdprefetch(struct ohci_hcd *ohci) |
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{ |
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return ohci->flags & OHCI_QUIRK_AMD_PREFETCH; |
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} |
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#else |
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static inline int quirk_nec(struct ohci_hcd *ohci) |
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{ |
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return 0; |
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} |
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static inline int quirk_zfmicro(struct ohci_hcd *ohci) |
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{ |
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return 0; |
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} |
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static inline int quirk_amdiso(struct ohci_hcd *ohci) |
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{ |
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return 0; |
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} |
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static inline int quirk_amdprefetch(struct ohci_hcd *ohci) |
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{ |
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return 0; |
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} |
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#endif |
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/* convert between an hcd pointer and the corresponding ohci_hcd */ |
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static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd) |
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{ |
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return (struct ohci_hcd *) (hcd->hcd_priv); |
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} |
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static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci) |
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{ |
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return container_of ((void *) ohci, struct usb_hcd, hcd_priv); |
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} |
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/*-------------------------------------------------------------------------*/ |
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#define ohci_dbg(ohci, fmt, args...) \ |
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dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) |
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#define ohci_err(ohci, fmt, args...) \ |
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dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) |
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#define ohci_info(ohci, fmt, args...) \ |
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dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) |
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#define ohci_warn(ohci, fmt, args...) \ |
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dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) |
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/*-------------------------------------------------------------------------*/ |
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/* |
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* While most USB host controllers implement their registers and |
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* in-memory communication descriptors in little-endian format, |
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* a minority (notably the IBM STB04XXX and the Motorola MPC5200 |
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* processors) implement them in big endian format. |
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* |
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* In addition some more exotic implementations like the Toshiba |
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* Spider (aka SCC) cell southbridge are "mixed" endian, that is, |
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* they have a different endianness for registers vs. in-memory |
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* descriptors. |
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* |
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* This attempts to support either format at compile time without a |
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* runtime penalty, or both formats with the additional overhead |
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* of checking a flag bit. |
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* |
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* That leads to some tricky Kconfig rules howevber. There are |
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* different defaults based on some arch/ppc platforms, though |
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* the basic rules are: |
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* |
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* Controller type Kconfig options needed |
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* --------------- ---------------------- |
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* little endian CONFIG_USB_OHCI_LITTLE_ENDIAN |
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* |
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* fully big endian CONFIG_USB_OHCI_BIG_ENDIAN_DESC _and_ |
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* CONFIG_USB_OHCI_BIG_ENDIAN_MMIO |
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* |
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* mixed endian CONFIG_USB_OHCI_LITTLE_ENDIAN _and_ |
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* CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC} |
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* |
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* (If you have a mixed endian controller, you -must- also define |
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* CONFIG_USB_OHCI_LITTLE_ENDIAN or things will not work when building |
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* both your mixed endian and a fully big endian controller support in |
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* the same kernel image). |
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*/ |
|
|
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#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC |
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#ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN |
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#define big_endian_desc(ohci) (ohci->flags & OHCI_QUIRK_BE_DESC) |
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#else |
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#define big_endian_desc(ohci) 1 /* only big endian */ |
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#endif |
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#else |
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#define big_endian_desc(ohci) 0 /* only little endian */ |
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#endif |
|
|
|
#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO |
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#ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN |
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#define big_endian_mmio(ohci) (ohci->flags & OHCI_QUIRK_BE_MMIO) |
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#else |
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#define big_endian_mmio(ohci) 1 /* only big endian */ |
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#endif |
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#else |
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#define big_endian_mmio(ohci) 0 /* only little endian */ |
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#endif |
|
|
|
/* |
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* Big-endian read/write functions are arch-specific. |
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* Other arches can be added if/when they're needed. |
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* |
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*/ |
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static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci, |
|
__hc32 __iomem * regs) |
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{ |
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#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO |
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return big_endian_mmio(ohci) ? |
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readl_be (regs) : |
|
readl (regs); |
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#else |
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return readl (regs); |
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#endif |
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} |
|
|
|
static inline void _ohci_writel (const struct ohci_hcd *ohci, |
|
const unsigned int val, __hc32 __iomem *regs) |
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{ |
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#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO |
|
big_endian_mmio(ohci) ? |
|
writel_be (val, regs) : |
|
writel (val, regs); |
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#else |
|
writel (val, regs); |
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#endif |
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} |
|
|
|
#define ohci_readl(o,r) _ohci_readl(o,r) |
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#define ohci_writel(o,v,r) _ohci_writel(o,v,r) |
|
|
|
|
|
/*-------------------------------------------------------------------------*/ |
|
|
|
/* cpu to ohci */ |
|
static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x) |
|
{ |
|
return big_endian_desc(ohci) ? |
|
(__force __hc16)cpu_to_be16(x) : |
|
(__force __hc16)cpu_to_le16(x); |
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} |
|
|
|
static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x) |
|
{ |
|
return big_endian_desc(ohci) ? |
|
cpu_to_be16p(x) : |
|
cpu_to_le16p(x); |
|
} |
|
|
|
static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x) |
|
{ |
|
return big_endian_desc(ohci) ? |
|
(__force __hc32)cpu_to_be32(x) : |
|
(__force __hc32)cpu_to_le32(x); |
|
} |
|
|
|
static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x) |
|
{ |
|
return big_endian_desc(ohci) ? |
|
cpu_to_be32p(x) : |
|
cpu_to_le32p(x); |
|
} |
|
|
|
/* ohci to cpu */ |
|
static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x) |
|
{ |
|
return big_endian_desc(ohci) ? |
|
be16_to_cpu((__force __be16)x) : |
|
le16_to_cpu((__force __le16)x); |
|
} |
|
|
|
static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x) |
|
{ |
|
return big_endian_desc(ohci) ? |
|
be16_to_cpup((__force __be16 *)x) : |
|
le16_to_cpup((__force __le16 *)x); |
|
} |
|
|
|
static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x) |
|
{ |
|
return big_endian_desc(ohci) ? |
|
be32_to_cpu((__force __be32)x) : |
|
le32_to_cpu((__force __le32)x); |
|
} |
|
|
|
static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x) |
|
{ |
|
return big_endian_desc(ohci) ? |
|
be32_to_cpup((__force __be32 *)x) : |
|
le32_to_cpup((__force __le32 *)x); |
|
} |
|
|
|
/*-------------------------------------------------------------------------*/ |
|
|
|
/* |
|
* The HCCA frame number is 16 bits, but is accessed as 32 bits since not all |
|
* hardware handles 16 bit reads. Depending on the SoC implementation, the |
|
* frame number can wind up in either bits [31:16] (default) or |
|
* [15:0] (OHCI_QUIRK_FRAME_NO) on big endian hosts. |
|
* |
|
* Somewhat similarly, the 16-bit PSW fields in a transfer descriptor are |
|
* reordered on BE. |
|
*/ |
|
|
|
static inline u16 ohci_frame_no(const struct ohci_hcd *ohci) |
|
{ |
|
u32 tmp; |
|
if (big_endian_desc(ohci)) { |
|
tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no); |
|
if (!(ohci->flags & OHCI_QUIRK_FRAME_NO)) |
|
tmp >>= 16; |
|
} else |
|
tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no); |
|
|
|
return (u16)tmp; |
|
} |
|
|
|
static inline __hc16 *ohci_hwPSWp(const struct ohci_hcd *ohci, |
|
const struct td *td, int index) |
|
{ |
|
return (__hc16 *)(big_endian_desc(ohci) ? |
|
&td->hwPSW[index ^ 1] : &td->hwPSW[index]); |
|
} |
|
|
|
static inline u16 ohci_hwPSW(const struct ohci_hcd *ohci, |
|
const struct td *td, int index) |
|
{ |
|
return hc16_to_cpup(ohci, ohci_hwPSWp(ohci, td, index)); |
|
} |
|
|
|
/*-------------------------------------------------------------------------*/ |
|
|
|
#define FI 0x2edf /* 12000 bits per frame (-1) */ |
|
#define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) |
|
#define FIT (1 << 31) |
|
#define LSTHRESH 0x628 /* lowspeed bit threshold */ |
|
|
|
static inline void periodic_reinit (struct ohci_hcd *ohci) |
|
{ |
|
u32 fi = ohci->fminterval & 0x03fff; |
|
u32 fit = ohci_readl(ohci, &ohci->regs->fminterval) & FIT; |
|
|
|
ohci_writel (ohci, (fit ^ FIT) | ohci->fminterval, |
|
&ohci->regs->fminterval); |
|
ohci_writel (ohci, ((9 * fi) / 10) & 0x3fff, |
|
&ohci->regs->periodicstart); |
|
} |
|
|
|
/* AMD-756 (D2 rev) reports corrupt register contents in some cases. |
|
* The erratum (#4) description is incorrect. AMD's workaround waits |
|
* till some bits (mostly reserved) are clear; ok for all revs. |
|
*/ |
|
#define read_roothub(hc, register, mask) ({ \ |
|
u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \ |
|
if (temp == -1) \ |
|
hc->rh_state = OHCI_RH_HALTED; \ |
|
else if (hc->flags & OHCI_QUIRK_AMD756) \ |
|
while (temp & mask) \ |
|
temp = ohci_readl (hc, &hc->regs->roothub.register); \ |
|
temp; }) |
|
|
|
static inline u32 roothub_a (struct ohci_hcd *hc) |
|
{ return read_roothub (hc, a, 0xfc0fe000); } |
|
static inline u32 roothub_b (struct ohci_hcd *hc) |
|
{ return ohci_readl (hc, &hc->regs->roothub.b); } |
|
static inline u32 roothub_status (struct ohci_hcd *hc) |
|
{ return ohci_readl (hc, &hc->regs->roothub.status); } |
|
static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i) |
|
{ return read_roothub (hc, portstatus [i], 0xffe0fce0); } |
|
|
|
/* Declarations of things exported for use by ohci platform drivers */ |
|
|
|
struct ohci_driver_overrides { |
|
const char *product_desc; |
|
size_t extra_priv_size; |
|
int (*reset)(struct usb_hcd *hcd); |
|
}; |
|
|
|
extern void ohci_init_driver(struct hc_driver *drv, |
|
const struct ohci_driver_overrides *over); |
|
extern int ohci_restart(struct ohci_hcd *ohci); |
|
extern int ohci_setup(struct usb_hcd *hcd); |
|
extern int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup); |
|
extern int ohci_resume(struct usb_hcd *hcd, bool hibernated); |
|
extern int ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
|
u16 wIndex, char *buf, u16 wLength); |
|
extern int ohci_hub_status_data(struct usb_hcd *hcd, char *buf);
|
|
|