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1772 lines
57 KiB
1772 lines
57 KiB
/* ========================================================================== |
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* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $ |
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* $Revision: #92 $ |
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* $Date: 2012/08/10 $ |
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* $Change: 2047372 $ |
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* |
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* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
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* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
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* otherwise expressly agreed to in writing between Synopsys and you. |
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* |
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* The Software IS NOT an item of Licensed Software or Licensed Product under |
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* any End User Software License Agreement or Agreement for Licensed Product |
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* with Synopsys or any supplement thereto. You are permitted to use and |
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* redistribute this Software in source and binary forms, with or without |
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* modification, provided that redistributions of source code must retain this |
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* notice. You may not view, use, disclose, copy or distribute this file or |
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* any information contained herein except pursuant to this license grant from |
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* Synopsys. If you do not agree with this notice, including the disclaimer |
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* below, then you are not authorized to use the Software. |
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* |
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
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* DAMAGE. |
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* ========================================================================== */ |
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|
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/** @file |
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* The dwc_otg_driver module provides the initialization and cleanup entry |
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* points for the DWC_otg driver. This module will be dynamically installed |
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* after Linux is booted using the insmod command. When the module is |
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* installed, the dwc_otg_driver_init function is called. When the module is |
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* removed (using rmmod), the dwc_otg_driver_cleanup function is called. |
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* |
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* This module also defines a data structure for the dwc_otg_driver, which is |
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* used in conjunction with the standard ARM lm_device structure. These |
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* structures allow the OTG driver to comply with the standard Linux driver |
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* model in which devices and drivers are registered with a bus driver. This |
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* has the benefit that Linux can expose attributes of the driver and device |
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* in its special sysfs file system. Users can then read or write files in |
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* this file system to perform diagnostics on the driver components or the |
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* device. |
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*/ |
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|
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#include "dwc_otg_os_dep.h" |
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#include "dwc_os.h" |
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#include "dwc_otg_dbg.h" |
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#include "dwc_otg_driver.h" |
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#include "dwc_otg_attr.h" |
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#include "dwc_otg_core_if.h" |
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#include "dwc_otg_pcd_if.h" |
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#include "dwc_otg_hcd_if.h" |
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#include "dwc_otg_fiq_fsm.h" |
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|
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#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012" |
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#define DWC_DRIVER_DESC "HS OTG USB Controller driver" |
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|
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bool microframe_schedule=true; |
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|
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static const char dwc_driver_name[] = "dwc_otg"; |
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|
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extern int pcd_init( |
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#ifdef LM_INTERFACE |
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struct lm_device *_dev |
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#elif defined(PCI_INTERFACE) |
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struct pci_dev *_dev |
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#elif defined(PLATFORM_INTERFACE) |
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struct platform_device *dev |
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#endif |
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); |
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extern int hcd_init( |
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#ifdef LM_INTERFACE |
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struct lm_device *_dev |
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#elif defined(PCI_INTERFACE) |
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struct pci_dev *_dev |
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#elif defined(PLATFORM_INTERFACE) |
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struct platform_device *dev |
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#endif |
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); |
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|
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extern int pcd_remove( |
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#ifdef LM_INTERFACE |
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struct lm_device *_dev |
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#elif defined(PCI_INTERFACE) |
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struct pci_dev *_dev |
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#elif defined(PLATFORM_INTERFACE) |
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struct platform_device *_dev |
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#endif |
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); |
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|
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extern void hcd_remove( |
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#ifdef LM_INTERFACE |
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struct lm_device *_dev |
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#elif defined(PCI_INTERFACE) |
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struct pci_dev *_dev |
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#elif defined(PLATFORM_INTERFACE) |
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struct platform_device *_dev |
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#endif |
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); |
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|
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extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host); |
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|
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/*-------------------------------------------------------------------------*/ |
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/* Encapsulate the module parameter settings */ |
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|
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struct dwc_otg_driver_module_params { |
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int32_t opt; |
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int32_t otg_cap; |
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int32_t dma_enable; |
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int32_t dma_desc_enable; |
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int32_t dma_burst_size; |
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int32_t speed; |
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int32_t host_support_fs_ls_low_power; |
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int32_t host_ls_low_power_phy_clk; |
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int32_t enable_dynamic_fifo; |
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int32_t data_fifo_size; |
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int32_t dev_rx_fifo_size; |
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int32_t dev_nperio_tx_fifo_size; |
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uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; |
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int32_t host_rx_fifo_size; |
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int32_t host_nperio_tx_fifo_size; |
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int32_t host_perio_tx_fifo_size; |
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int32_t max_transfer_size; |
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int32_t max_packet_count; |
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int32_t host_channels; |
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int32_t dev_endpoints; |
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int32_t phy_type; |
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int32_t phy_utmi_width; |
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int32_t phy_ulpi_ddr; |
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int32_t phy_ulpi_ext_vbus; |
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int32_t i2c_enable; |
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int32_t ulpi_fs_ls; |
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int32_t ts_dline; |
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int32_t en_multiple_tx_fifo; |
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uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; |
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uint32_t thr_ctl; |
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uint32_t tx_thr_length; |
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uint32_t rx_thr_length; |
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int32_t pti_enable; |
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int32_t mpi_enable; |
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int32_t lpm_enable; |
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int32_t ic_usb_cap; |
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int32_t ahb_thr_ratio; |
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int32_t power_down; |
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int32_t reload_ctl; |
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int32_t dev_out_nak; |
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int32_t cont_on_bna; |
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int32_t ahb_single; |
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int32_t otg_ver; |
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int32_t adp_enable; |
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}; |
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static struct dwc_otg_driver_module_params dwc_otg_module_params = { |
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.opt = -1, |
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.otg_cap = -1, |
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.dma_enable = -1, |
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.dma_desc_enable = -1, |
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.dma_burst_size = -1, |
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.speed = -1, |
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.host_support_fs_ls_low_power = -1, |
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.host_ls_low_power_phy_clk = -1, |
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.enable_dynamic_fifo = -1, |
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.data_fifo_size = -1, |
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.dev_rx_fifo_size = -1, |
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.dev_nperio_tx_fifo_size = -1, |
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.dev_perio_tx_fifo_size = { |
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/* dev_perio_tx_fifo_size_1 */ |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1 |
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/* 15 */ |
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}, |
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.host_rx_fifo_size = -1, |
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.host_nperio_tx_fifo_size = -1, |
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.host_perio_tx_fifo_size = -1, |
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.max_transfer_size = -1, |
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.max_packet_count = -1, |
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.host_channels = -1, |
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.dev_endpoints = -1, |
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.phy_type = -1, |
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.phy_utmi_width = -1, |
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.phy_ulpi_ddr = -1, |
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.phy_ulpi_ext_vbus = -1, |
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.i2c_enable = -1, |
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.ulpi_fs_ls = -1, |
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.ts_dline = -1, |
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.en_multiple_tx_fifo = -1, |
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.dev_tx_fifo_size = { |
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/* dev_tx_fifo_size */ |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1, |
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-1 |
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/* 15 */ |
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}, |
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.thr_ctl = -1, |
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.tx_thr_length = -1, |
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.rx_thr_length = -1, |
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.pti_enable = -1, |
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.mpi_enable = -1, |
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.lpm_enable = 0, |
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.ic_usb_cap = -1, |
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.ahb_thr_ratio = -1, |
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.power_down = -1, |
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.reload_ctl = -1, |
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.dev_out_nak = -1, |
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.cont_on_bna = -1, |
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.ahb_single = -1, |
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.otg_ver = -1, |
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.adp_enable = -1, |
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}; |
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|
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//Global variable to switch the fiq fix on or off |
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bool fiq_enable = 1; |
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// Global variable to enable the split transaction fix |
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bool fiq_fsm_enable = true; |
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//Bulk split-transaction NAK holdoff in microframes |
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uint16_t nak_holdoff = 8; |
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|
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//Force host mode during CIL re-init |
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bool cil_force_host = true; |
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|
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unsigned short fiq_fsm_mask = 0x0F; |
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|
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unsigned short int_ep_interval_min = 0; |
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/** |
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* This function shows the Driver Version. |
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*/ |
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static ssize_t version_show(struct device_driver *dev, char *buf) |
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{ |
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return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n", |
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DWC_DRIVER_VERSION); |
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} |
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|
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static DRIVER_ATTR_RO(version); |
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|
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/** |
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* Global Debug Level Mask. |
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*/ |
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uint32_t g_dbg_lvl = 0; /* OFF */ |
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|
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/** |
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* This function shows the driver Debug Level. |
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*/ |
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static ssize_t debuglevel_show(struct device_driver *drv, char *buf) |
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{ |
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return sprintf(buf, "0x%0x\n", g_dbg_lvl); |
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} |
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|
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/** |
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* This function stores the driver Debug Level. |
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*/ |
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static ssize_t debuglevel_store(struct device_driver *drv, const char *buf, |
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size_t count) |
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{ |
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g_dbg_lvl = simple_strtoul(buf, NULL, 16); |
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return count; |
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} |
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|
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static DRIVER_ATTR_RW(debuglevel); |
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|
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/** |
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* This function is called during module intialization |
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* to pass module parameters to the DWC_OTG CORE. |
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*/ |
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static int set_parameters(dwc_otg_core_if_t * core_if) |
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{ |
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int retval = 0; |
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int i; |
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|
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if (dwc_otg_module_params.otg_cap != -1) { |
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retval += |
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dwc_otg_set_param_otg_cap(core_if, |
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dwc_otg_module_params.otg_cap); |
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} |
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if (dwc_otg_module_params.dma_enable != -1) { |
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retval += |
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dwc_otg_set_param_dma_enable(core_if, |
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dwc_otg_module_params. |
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dma_enable); |
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} |
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if (dwc_otg_module_params.dma_desc_enable != -1) { |
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retval += |
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dwc_otg_set_param_dma_desc_enable(core_if, |
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dwc_otg_module_params. |
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dma_desc_enable); |
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} |
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if (dwc_otg_module_params.opt != -1) { |
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retval += |
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dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt); |
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} |
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if (dwc_otg_module_params.dma_burst_size != -1) { |
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retval += |
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dwc_otg_set_param_dma_burst_size(core_if, |
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dwc_otg_module_params. |
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dma_burst_size); |
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} |
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if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) { |
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retval += |
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dwc_otg_set_param_host_support_fs_ls_low_power(core_if, |
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dwc_otg_module_params. |
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host_support_fs_ls_low_power); |
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} |
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if (dwc_otg_module_params.enable_dynamic_fifo != -1) { |
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retval += |
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dwc_otg_set_param_enable_dynamic_fifo(core_if, |
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dwc_otg_module_params. |
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enable_dynamic_fifo); |
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} |
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if (dwc_otg_module_params.data_fifo_size != -1) { |
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retval += |
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dwc_otg_set_param_data_fifo_size(core_if, |
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dwc_otg_module_params. |
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data_fifo_size); |
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} |
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if (dwc_otg_module_params.dev_rx_fifo_size != -1) { |
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retval += |
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dwc_otg_set_param_dev_rx_fifo_size(core_if, |
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dwc_otg_module_params. |
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dev_rx_fifo_size); |
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} |
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if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) { |
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retval += |
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dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if, |
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dwc_otg_module_params. |
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dev_nperio_tx_fifo_size); |
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} |
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if (dwc_otg_module_params.host_rx_fifo_size != -1) { |
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retval += |
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dwc_otg_set_param_host_rx_fifo_size(core_if, |
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dwc_otg_module_params.host_rx_fifo_size); |
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} |
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if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) { |
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retval += |
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dwc_otg_set_param_host_nperio_tx_fifo_size(core_if, |
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dwc_otg_module_params. |
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host_nperio_tx_fifo_size); |
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} |
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if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) { |
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retval += |
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dwc_otg_set_param_host_perio_tx_fifo_size(core_if, |
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dwc_otg_module_params. |
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host_perio_tx_fifo_size); |
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} |
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if (dwc_otg_module_params.max_transfer_size != -1) { |
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retval += |
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dwc_otg_set_param_max_transfer_size(core_if, |
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dwc_otg_module_params. |
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max_transfer_size); |
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} |
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if (dwc_otg_module_params.max_packet_count != -1) { |
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retval += |
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dwc_otg_set_param_max_packet_count(core_if, |
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dwc_otg_module_params. |
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max_packet_count); |
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} |
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if (dwc_otg_module_params.host_channels != -1) { |
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retval += |
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dwc_otg_set_param_host_channels(core_if, |
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dwc_otg_module_params. |
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host_channels); |
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} |
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if (dwc_otg_module_params.dev_endpoints != -1) { |
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retval += |
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dwc_otg_set_param_dev_endpoints(core_if, |
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dwc_otg_module_params. |
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dev_endpoints); |
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} |
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if (dwc_otg_module_params.phy_type != -1) { |
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retval += |
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dwc_otg_set_param_phy_type(core_if, |
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dwc_otg_module_params.phy_type); |
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} |
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if (dwc_otg_module_params.speed != -1) { |
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retval += |
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dwc_otg_set_param_speed(core_if, |
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dwc_otg_module_params.speed); |
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} |
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if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) { |
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retval += |
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dwc_otg_set_param_host_ls_low_power_phy_clk(core_if, |
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dwc_otg_module_params. |
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host_ls_low_power_phy_clk); |
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} |
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if (dwc_otg_module_params.phy_ulpi_ddr != -1) { |
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retval += |
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dwc_otg_set_param_phy_ulpi_ddr(core_if, |
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dwc_otg_module_params. |
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phy_ulpi_ddr); |
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} |
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if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) { |
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retval += |
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dwc_otg_set_param_phy_ulpi_ext_vbus(core_if, |
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dwc_otg_module_params. |
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phy_ulpi_ext_vbus); |
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} |
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if (dwc_otg_module_params.phy_utmi_width != -1) { |
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retval += |
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dwc_otg_set_param_phy_utmi_width(core_if, |
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dwc_otg_module_params. |
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phy_utmi_width); |
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} |
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if (dwc_otg_module_params.ulpi_fs_ls != -1) { |
|
retval += |
|
dwc_otg_set_param_ulpi_fs_ls(core_if, |
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dwc_otg_module_params.ulpi_fs_ls); |
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} |
|
if (dwc_otg_module_params.ts_dline != -1) { |
|
retval += |
|
dwc_otg_set_param_ts_dline(core_if, |
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dwc_otg_module_params.ts_dline); |
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} |
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if (dwc_otg_module_params.i2c_enable != -1) { |
|
retval += |
|
dwc_otg_set_param_i2c_enable(core_if, |
|
dwc_otg_module_params. |
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i2c_enable); |
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} |
|
if (dwc_otg_module_params.en_multiple_tx_fifo != -1) { |
|
retval += |
|
dwc_otg_set_param_en_multiple_tx_fifo(core_if, |
|
dwc_otg_module_params. |
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en_multiple_tx_fifo); |
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} |
|
for (i = 0; i < 15; i++) { |
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if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { |
|
retval += |
|
dwc_otg_set_param_dev_perio_tx_fifo_size(core_if, |
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dwc_otg_module_params. |
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dev_perio_tx_fifo_size |
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[i], i); |
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} |
|
} |
|
|
|
for (i = 0; i < 15; i++) { |
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if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { |
|
retval += dwc_otg_set_param_dev_tx_fifo_size(core_if, |
|
dwc_otg_module_params. |
|
dev_tx_fifo_size |
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[i], i); |
|
} |
|
} |
|
if (dwc_otg_module_params.thr_ctl != -1) { |
|
retval += |
|
dwc_otg_set_param_thr_ctl(core_if, |
|
dwc_otg_module_params.thr_ctl); |
|
} |
|
if (dwc_otg_module_params.mpi_enable != -1) { |
|
retval += |
|
dwc_otg_set_param_mpi_enable(core_if, |
|
dwc_otg_module_params. |
|
mpi_enable); |
|
} |
|
if (dwc_otg_module_params.pti_enable != -1) { |
|
retval += |
|
dwc_otg_set_param_pti_enable(core_if, |
|
dwc_otg_module_params. |
|
pti_enable); |
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} |
|
if (dwc_otg_module_params.lpm_enable != -1) { |
|
retval += |
|
dwc_otg_set_param_lpm_enable(core_if, |
|
dwc_otg_module_params. |
|
lpm_enable); |
|
} |
|
if (dwc_otg_module_params.ic_usb_cap != -1) { |
|
retval += |
|
dwc_otg_set_param_ic_usb_cap(core_if, |
|
dwc_otg_module_params. |
|
ic_usb_cap); |
|
} |
|
if (dwc_otg_module_params.tx_thr_length != -1) { |
|
retval += |
|
dwc_otg_set_param_tx_thr_length(core_if, |
|
dwc_otg_module_params.tx_thr_length); |
|
} |
|
if (dwc_otg_module_params.rx_thr_length != -1) { |
|
retval += |
|
dwc_otg_set_param_rx_thr_length(core_if, |
|
dwc_otg_module_params. |
|
rx_thr_length); |
|
} |
|
if (dwc_otg_module_params.ahb_thr_ratio != -1) { |
|
retval += |
|
dwc_otg_set_param_ahb_thr_ratio(core_if, |
|
dwc_otg_module_params.ahb_thr_ratio); |
|
} |
|
if (dwc_otg_module_params.power_down != -1) { |
|
retval += |
|
dwc_otg_set_param_power_down(core_if, |
|
dwc_otg_module_params.power_down); |
|
} |
|
if (dwc_otg_module_params.reload_ctl != -1) { |
|
retval += |
|
dwc_otg_set_param_reload_ctl(core_if, |
|
dwc_otg_module_params.reload_ctl); |
|
} |
|
|
|
if (dwc_otg_module_params.dev_out_nak != -1) { |
|
retval += |
|
dwc_otg_set_param_dev_out_nak(core_if, |
|
dwc_otg_module_params.dev_out_nak); |
|
} |
|
|
|
if (dwc_otg_module_params.cont_on_bna != -1) { |
|
retval += |
|
dwc_otg_set_param_cont_on_bna(core_if, |
|
dwc_otg_module_params.cont_on_bna); |
|
} |
|
|
|
if (dwc_otg_module_params.ahb_single != -1) { |
|
retval += |
|
dwc_otg_set_param_ahb_single(core_if, |
|
dwc_otg_module_params.ahb_single); |
|
} |
|
|
|
if (dwc_otg_module_params.otg_ver != -1) { |
|
retval += |
|
dwc_otg_set_param_otg_ver(core_if, |
|
dwc_otg_module_params.otg_ver); |
|
} |
|
if (dwc_otg_module_params.adp_enable != -1) { |
|
retval += |
|
dwc_otg_set_param_adp_enable(core_if, |
|
dwc_otg_module_params. |
|
adp_enable); |
|
} |
|
return retval; |
|
} |
|
|
|
/** |
|
* This function is the top level interrupt handler for the Common |
|
* (Device and host modes) interrupts. |
|
*/ |
|
static irqreturn_t dwc_otg_common_irq(int irq, void *dev) |
|
{ |
|
int32_t retval = IRQ_NONE; |
|
|
|
retval = dwc_otg_handle_common_intr(dev); |
|
if (retval != 0) { |
|
S3C2410X_CLEAR_EINTPEND(); |
|
} |
|
return IRQ_RETVAL(retval); |
|
} |
|
|
|
/** |
|
* This function is called when a lm_device is unregistered with the |
|
* dwc_otg_driver. This happens, for example, when the rmmod command is |
|
* executed. The device may or may not be electrically present. If it is |
|
* present, the driver stops device processing. Any resources used on behalf |
|
* of this device are freed. |
|
* |
|
* @param _dev |
|
*/ |
|
#ifdef LM_INTERFACE |
|
#define REM_RETVAL(n) |
|
static void dwc_otg_driver_remove( struct lm_device *_dev ) |
|
{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); |
|
#elif defined(PCI_INTERFACE) |
|
#define REM_RETVAL(n) |
|
static void dwc_otg_driver_remove( struct pci_dev *_dev ) |
|
{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); |
|
#elif defined(PLATFORM_INTERFACE) |
|
#define REM_RETVAL(n) n |
|
static int dwc_otg_driver_remove( struct platform_device *_dev ) |
|
{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); |
|
#endif |
|
|
|
DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); |
|
|
|
if (!otg_dev) { |
|
/* Memory allocation for the dwc_otg_device failed. */ |
|
DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); |
|
return REM_RETVAL(-ENOMEM); |
|
} |
|
#ifndef DWC_DEVICE_ONLY |
|
if (otg_dev->hcd) { |
|
hcd_remove(_dev); |
|
} else { |
|
DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); |
|
return REM_RETVAL(-EINVAL); |
|
} |
|
#endif |
|
|
|
#ifndef DWC_HOST_ONLY |
|
if (otg_dev->pcd) { |
|
pcd_remove(_dev); |
|
} else { |
|
DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__); |
|
return REM_RETVAL(-EINVAL); |
|
} |
|
#endif |
|
/* |
|
* Free the IRQ |
|
*/ |
|
if (otg_dev->common_irq_installed) { |
|
free_irq(otg_dev->os_dep.irq_num, otg_dev); |
|
} else { |
|
DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__); |
|
return REM_RETVAL(-ENXIO); |
|
} |
|
|
|
if (otg_dev->core_if) { |
|
dwc_otg_cil_remove(otg_dev->core_if); |
|
} else { |
|
DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__); |
|
return REM_RETVAL(-ENXIO); |
|
} |
|
|
|
/* |
|
* Remove the device attributes |
|
*/ |
|
dwc_otg_attr_remove(_dev); |
|
|
|
/* |
|
* Return the memory. |
|
*/ |
|
if (otg_dev->os_dep.base) { |
|
iounmap(otg_dev->os_dep.base); |
|
} |
|
DWC_FREE(otg_dev); |
|
|
|
/* |
|
* Clear the drvdata pointer. |
|
*/ |
|
#ifdef LM_INTERFACE |
|
lm_set_drvdata(_dev, 0); |
|
#elif defined(PCI_INTERFACE) |
|
release_mem_region(otg_dev->os_dep.rsrc_start, |
|
otg_dev->os_dep.rsrc_len); |
|
pci_set_drvdata(_dev, 0); |
|
#elif defined(PLATFORM_INTERFACE) |
|
platform_set_drvdata(_dev, 0); |
|
#endif |
|
return REM_RETVAL(0); |
|
} |
|
|
|
/** |
|
* This function is called when an lm_device is bound to a |
|
* dwc_otg_driver. It creates the driver components required to |
|
* control the device (CIL, HCD, and PCD) and it initializes the |
|
* device. The driver components are stored in a dwc_otg_device |
|
* structure. A reference to the dwc_otg_device is saved in the |
|
* lm_device. This allows the driver to access the dwc_otg_device |
|
* structure on subsequent calls to driver methods for this device. |
|
* |
|
* @param _dev Bus device |
|
*/ |
|
static int dwc_otg_driver_probe( |
|
#ifdef LM_INTERFACE |
|
struct lm_device *_dev |
|
#elif defined(PCI_INTERFACE) |
|
struct pci_dev *_dev, |
|
const struct pci_device_id *id |
|
#elif defined(PLATFORM_INTERFACE) |
|
struct platform_device *_dev |
|
#endif |
|
) |
|
{ |
|
int retval = 0; |
|
dwc_otg_device_t *dwc_otg_device; |
|
int devirq; |
|
|
|
dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev); |
|
#ifdef LM_INTERFACE |
|
dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start); |
|
#elif defined(PCI_INTERFACE) |
|
if (!id) { |
|
DWC_ERROR("Invalid pci_device_id %p", id); |
|
return -EINVAL; |
|
} |
|
|
|
if (!_dev || (pci_enable_device(_dev) < 0)) { |
|
DWC_ERROR("Invalid pci_device %p", _dev); |
|
return -ENODEV; |
|
} |
|
dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0)); |
|
/* other stuff needed as well? */ |
|
|
|
#elif defined(PLATFORM_INTERFACE) |
|
dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n", |
|
(unsigned)_dev->resource->start, |
|
(unsigned)(_dev->resource->end - _dev->resource->start)); |
|
#endif |
|
|
|
dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t)); |
|
|
|
if (!dwc_otg_device) { |
|
dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); |
|
dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF; |
|
dwc_otg_device->os_dep.platformdev = _dev; |
|
|
|
/* |
|
* Map the DWC_otg Core memory into virtual address space. |
|
*/ |
|
#ifdef LM_INTERFACE |
|
dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K); |
|
|
|
if (!dwc_otg_device->os_dep.base) { |
|
dev_err(&_dev->dev, "ioremap() failed\n"); |
|
DWC_FREE(dwc_otg_device); |
|
return -ENOMEM; |
|
} |
|
dev_dbg(&_dev->dev, "base=0x%08x\n", |
|
(unsigned)dwc_otg_device->os_dep.base); |
|
#elif defined(PCI_INTERFACE) |
|
_dev->current_state = PCI_D0; |
|
_dev->dev.power.power_state = PMSG_ON; |
|
|
|
if (!_dev->irq) { |
|
DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", |
|
pci_name(_dev)); |
|
iounmap(dwc_otg_device->os_dep.base); |
|
DWC_FREE(dwc_otg_device); |
|
return -ENODEV; |
|
} |
|
|
|
dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0); |
|
dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0); |
|
DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n", |
|
(unsigned)dwc_otg_device->os_dep.rsrc_start, |
|
(unsigned)dwc_otg_device->os_dep.rsrc_len); |
|
if (!request_mem_region |
|
(dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len, |
|
"dwc_otg")) { |
|
dev_dbg(&_dev->dev, "error requesting memory\n"); |
|
iounmap(dwc_otg_device->os_dep.base); |
|
DWC_FREE(dwc_otg_device); |
|
return -EFAULT; |
|
} |
|
|
|
dwc_otg_device->os_dep.base = |
|
ioremap(dwc_otg_device->os_dep.rsrc_start, |
|
dwc_otg_device->os_dep.rsrc_len); |
|
if (dwc_otg_device->os_dep.base == NULL) { |
|
dev_dbg(&_dev->dev, "error mapping memory\n"); |
|
release_mem_region(dwc_otg_device->os_dep.rsrc_start, |
|
dwc_otg_device->os_dep.rsrc_len); |
|
iounmap(dwc_otg_device->os_dep.base); |
|
DWC_FREE(dwc_otg_device); |
|
return -EFAULT; |
|
} |
|
dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", |
|
dwc_otg_device->os_dep.base); |
|
dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base; |
|
dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", |
|
dwc_otg_device->os_dep.base); |
|
dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__, |
|
(unsigned)dwc_otg_device->os_dep.rsrc_start, |
|
dwc_otg_device->os_dep.base); |
|
|
|
pci_set_master(_dev); |
|
pci_set_drvdata(_dev, dwc_otg_device); |
|
#elif defined(PLATFORM_INTERFACE) |
|
DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n", |
|
_dev->resource->start, |
|
_dev->resource->end - _dev->resource->start + 1); |
|
#if 1 |
|
if (!request_mem_region(_dev->resource[0].start, |
|
_dev->resource[0].end - _dev->resource[0].start + 1, |
|
"dwc_otg")) { |
|
dev_dbg(&_dev->dev, "error reserving mapped memory\n"); |
|
retval = -EFAULT; |
|
goto fail; |
|
} |
|
|
|
dwc_otg_device->os_dep.base = ioremap(_dev->resource[0].start, |
|
_dev->resource[0].end - |
|
_dev->resource[0].start+1); |
|
if (fiq_enable) |
|
{ |
|
if (!request_mem_region(_dev->resource[1].start, |
|
_dev->resource[1].end - _dev->resource[1].start + 1, |
|
"dwc_otg")) { |
|
dev_dbg(&_dev->dev, "error reserving mapped memory\n"); |
|
retval = -EFAULT; |
|
goto fail; |
|
} |
|
|
|
dwc_otg_device->os_dep.mphi_base = ioremap(_dev->resource[1].start, |
|
_dev->resource[1].end - |
|
_dev->resource[1].start + 1); |
|
dwc_otg_device->os_dep.use_swirq = (_dev->resource[1].end - _dev->resource[1].start) == 0x200; |
|
} |
|
|
|
#else |
|
{ |
|
struct map_desc desc = { |
|
.virtual = IO_ADDRESS((unsigned)_dev->resource->start), |
|
.pfn = __phys_to_pfn((unsigned)_dev->resource->start), |
|
.length = SZ_128K, |
|
.type = MT_DEVICE |
|
}; |
|
iotable_init(&desc, 1); |
|
dwc_otg_device->os_dep.base = (void *)desc.virtual; |
|
} |
|
#endif |
|
if (!dwc_otg_device->os_dep.base) { |
|
dev_err(&_dev->dev, "ioremap() failed\n"); |
|
retval = -ENOMEM; |
|
goto fail; |
|
} |
|
#endif |
|
|
|
/* |
|
* Initialize driver data to point to the global DWC_otg |
|
* Device structure. |
|
*/ |
|
#ifdef LM_INTERFACE |
|
lm_set_drvdata(_dev, dwc_otg_device); |
|
#elif defined(PLATFORM_INTERFACE) |
|
platform_set_drvdata(_dev, dwc_otg_device); |
|
#endif |
|
dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device); |
|
|
|
dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base); |
|
DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n", |
|
dwc_otg_device, dwc_otg_device->core_if);//GRAYG |
|
|
|
if (!dwc_otg_device->core_if) { |
|
dev_err(&_dev->dev, "CIL initialization failed!\n"); |
|
retval = -ENOMEM; |
|
goto fail; |
|
} |
|
|
|
dev_dbg(&_dev->dev, "Calling get_gsnpsid\n"); |
|
/* |
|
* Attempt to ensure this device is really a DWC_otg Controller. |
|
* Read and verify the SNPSID register contents. The value should be |
|
* 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3", |
|
* as in "OTG version 2.XX" or "OTG version 3.XX". |
|
*/ |
|
|
|
if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) && |
|
((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) { |
|
dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", |
|
dwc_otg_get_gsnpsid(dwc_otg_device->core_if)); |
|
retval = -EINVAL; |
|
goto fail; |
|
} |
|
|
|
/* |
|
* Validate parameter values. |
|
*/ |
|
dev_dbg(&_dev->dev, "Calling set_parameters\n"); |
|
if (set_parameters(dwc_otg_device->core_if)) { |
|
retval = -EINVAL; |
|
goto fail; |
|
} |
|
|
|
/* |
|
* Create Device Attributes in sysfs |
|
*/ |
|
dev_dbg(&_dev->dev, "Calling attr_create\n"); |
|
dwc_otg_attr_create(_dev); |
|
|
|
/* |
|
* Disable the global interrupt until all the interrupt |
|
* handlers are installed. |
|
*/ |
|
dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n"); |
|
dwc_otg_disable_global_interrupts(dwc_otg_device->core_if); |
|
|
|
/* |
|
* Install the interrupt handler for the common interrupts before |
|
* enabling common interrupts in core_init below. |
|
*/ |
|
|
|
#if defined(PLATFORM_INTERFACE) |
|
devirq = platform_get_irq_byname(_dev, fiq_enable ? "soft" : "usb"); |
|
if (devirq < 0) |
|
devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1); |
|
#else |
|
devirq = _dev->irq; |
|
#endif |
|
DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", |
|
devirq); |
|
dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq); |
|
retval = request_irq(devirq, dwc_otg_common_irq, |
|
IRQF_SHARED, |
|
"dwc_otg", dwc_otg_device); |
|
if (retval) { |
|
DWC_ERROR("request of irq%d failed\n", devirq); |
|
retval = -EBUSY; |
|
goto fail; |
|
} else { |
|
dwc_otg_device->common_irq_installed = 1; |
|
} |
|
dwc_otg_device->os_dep.irq_num = devirq; |
|
dwc_otg_device->os_dep.fiq_num = -EINVAL; |
|
if (fiq_enable) { |
|
int devfiq = platform_get_irq_byname(_dev, "usb"); |
|
if (devfiq < 0) |
|
devfiq = platform_get_irq(_dev, 1); |
|
dwc_otg_device->os_dep.fiq_num = devfiq; |
|
} |
|
|
|
#ifndef IRQF_TRIGGER_LOW |
|
#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) |
|
dev_dbg(&_dev->dev, "Calling set_irq_type\n"); |
|
set_irq_type(devirq, |
|
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) |
|
IRQT_LOW |
|
#else |
|
IRQ_TYPE_LEVEL_LOW |
|
#endif |
|
); |
|
#endif |
|
#endif /*IRQF_TRIGGER_LOW*/ |
|
|
|
/* |
|
* Initialize the DWC_otg core. |
|
*/ |
|
dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n"); |
|
dwc_otg_core_init(dwc_otg_device->core_if); |
|
|
|
#ifndef DWC_HOST_ONLY |
|
/* |
|
* Initialize the PCD |
|
*/ |
|
dev_dbg(&_dev->dev, "Calling pcd_init\n"); |
|
retval = pcd_init(_dev); |
|
if (retval != 0) { |
|
DWC_ERROR("pcd_init failed\n"); |
|
dwc_otg_device->pcd = NULL; |
|
goto fail; |
|
} |
|
#endif |
|
#ifndef DWC_DEVICE_ONLY |
|
/* |
|
* Initialize the HCD |
|
*/ |
|
dev_dbg(&_dev->dev, "Calling hcd_init\n"); |
|
retval = hcd_init(_dev); |
|
if (retval != 0) { |
|
DWC_ERROR("hcd_init failed\n"); |
|
dwc_otg_device->hcd = NULL; |
|
goto fail; |
|
} |
|
#endif |
|
/* Recover from drvdata having been overwritten by hcd_init() */ |
|
#ifdef LM_INTERFACE |
|
lm_set_drvdata(_dev, dwc_otg_device); |
|
#elif defined(PLATFORM_INTERFACE) |
|
platform_set_drvdata(_dev, dwc_otg_device); |
|
#elif defined(PCI_INTERFACE) |
|
pci_set_drvdata(_dev, dwc_otg_device); |
|
dwc_otg_device->os_dep.pcidev = _dev; |
|
#endif |
|
|
|
/* |
|
* Enable the global interrupt after all the interrupt |
|
* handlers are installed if there is no ADP support else |
|
* perform initial actions required for Internal ADP logic. |
|
*/ |
|
if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) { |
|
dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n"); |
|
dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); |
|
dev_dbg(&_dev->dev, "Done\n"); |
|
} else |
|
dwc_otg_adp_start(dwc_otg_device->core_if, |
|
dwc_otg_is_host_mode(dwc_otg_device->core_if)); |
|
|
|
return 0; |
|
|
|
fail: |
|
dwc_otg_driver_remove(_dev); |
|
return retval; |
|
} |
|
|
|
/** |
|
* This structure defines the methods to be called by a bus driver |
|
* during the lifecycle of a device on that bus. Both drivers and |
|
* devices are registered with a bus driver. The bus driver matches |
|
* devices to drivers based on information in the device and driver |
|
* structures. |
|
* |
|
* The probe function is called when the bus driver matches a device |
|
* to this driver. The remove function is called when a device is |
|
* unregistered with the bus driver. |
|
*/ |
|
#ifdef LM_INTERFACE |
|
static struct lm_driver dwc_otg_driver = { |
|
.drv = {.name = (char *)dwc_driver_name,}, |
|
.probe = dwc_otg_driver_probe, |
|
.remove = dwc_otg_driver_remove, |
|
// 'suspend' and 'resume' absent |
|
}; |
|
#elif defined(PCI_INTERFACE) |
|
static const struct pci_device_id pci_ids[] = { { |
|
PCI_DEVICE(0x16c3, 0xabcd), |
|
.driver_data = |
|
(unsigned long)0xdeadbeef, |
|
}, { /* end: all zeroes */ } |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(pci, pci_ids); |
|
|
|
/* pci driver glue; this is a "new style" PCI driver module */ |
|
static struct pci_driver dwc_otg_driver = { |
|
.name = "dwc_otg", |
|
.id_table = pci_ids, |
|
|
|
.probe = dwc_otg_driver_probe, |
|
.remove = dwc_otg_driver_remove, |
|
|
|
.driver = { |
|
.name = (char *)dwc_driver_name, |
|
}, |
|
}; |
|
#elif defined(PLATFORM_INTERFACE) |
|
static struct platform_device_id platform_ids[] = { |
|
{ |
|
.name = "bcm2708_usb", |
|
.driver_data = (kernel_ulong_t) 0xdeadbeef, |
|
}, |
|
{ /* end: all zeroes */ } |
|
}; |
|
MODULE_DEVICE_TABLE(platform, platform_ids); |
|
|
|
static const struct of_device_id dwc_otg_of_match_table[] = { |
|
{ .compatible = "brcm,bcm2708-usb", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table); |
|
|
|
static struct platform_driver dwc_otg_driver = { |
|
.driver = { |
|
.name = (char *)dwc_driver_name, |
|
.of_match_table = dwc_otg_of_match_table, |
|
}, |
|
.id_table = platform_ids, |
|
|
|
.probe = dwc_otg_driver_probe, |
|
.remove = dwc_otg_driver_remove, |
|
// no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early' |
|
}; |
|
#endif |
|
|
|
/** |
|
* This function is called when the dwc_otg_driver is installed with the |
|
* insmod command. It registers the dwc_otg_driver structure with the |
|
* appropriate bus driver. This will cause the dwc_otg_driver_probe function |
|
* to be called. In addition, the bus driver will automatically expose |
|
* attributes defined for the device and driver in the special sysfs file |
|
* system. |
|
* |
|
* @return |
|
*/ |
|
static int __init dwc_otg_driver_init(void) |
|
{ |
|
int retval = 0; |
|
int error; |
|
struct device_driver *drv; |
|
|
|
if(fiq_fsm_enable && !fiq_enable) { |
|
printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n"); |
|
fiq_enable = 1; |
|
} |
|
|
|
printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name, |
|
DWC_DRIVER_VERSION, |
|
#ifdef LM_INTERFACE |
|
"logicmodule"); |
|
retval = lm_driver_register(&dwc_otg_driver); |
|
drv = &dwc_otg_driver.drv; |
|
#elif defined(PCI_INTERFACE) |
|
"pci"); |
|
retval = pci_register_driver(&dwc_otg_driver); |
|
drv = &dwc_otg_driver.driver; |
|
#elif defined(PLATFORM_INTERFACE) |
|
"platform"); |
|
retval = platform_driver_register(&dwc_otg_driver); |
|
drv = &dwc_otg_driver.driver; |
|
#endif |
|
if (retval < 0) { |
|
printk(KERN_ERR "%s retval=%d\n", __func__, retval); |
|
return retval; |
|
} |
|
printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled"); |
|
printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled"); |
|
printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled"); |
|
|
|
error = driver_create_file(drv, &driver_attr_version); |
|
#ifdef DEBUG |
|
error = driver_create_file(drv, &driver_attr_debuglevel); |
|
#endif |
|
return retval; |
|
} |
|
|
|
module_init(dwc_otg_driver_init); |
|
|
|
/** |
|
* This function is called when the driver is removed from the kernel |
|
* with the rmmod command. The driver unregisters itself with its bus |
|
* driver. |
|
* |
|
*/ |
|
static void __exit dwc_otg_driver_cleanup(void) |
|
{ |
|
printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n"); |
|
|
|
#ifdef LM_INTERFACE |
|
driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel); |
|
driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version); |
|
lm_driver_unregister(&dwc_otg_driver); |
|
#elif defined(PCI_INTERFACE) |
|
driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); |
|
driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); |
|
pci_unregister_driver(&dwc_otg_driver); |
|
#elif defined(PLATFORM_INTERFACE) |
|
driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); |
|
driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); |
|
platform_driver_unregister(&dwc_otg_driver); |
|
#endif |
|
|
|
printk(KERN_INFO "%s module removed\n", dwc_driver_name); |
|
} |
|
|
|
module_exit(dwc_otg_driver_cleanup); |
|
|
|
MODULE_DESCRIPTION(DWC_DRIVER_DESC); |
|
MODULE_AUTHOR("Synopsys Inc."); |
|
MODULE_LICENSE("GPL"); |
|
|
|
module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); |
|
MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); |
|
module_param_named(opt, dwc_otg_module_params.opt, int, 0444); |
|
MODULE_PARM_DESC(opt, "OPT Mode"); |
|
module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); |
|
MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); |
|
|
|
module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, |
|
0444); |
|
MODULE_PARM_DESC(dma_desc_enable, |
|
"DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled"); |
|
|
|
module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, |
|
0444); |
|
MODULE_PARM_DESC(dma_burst_size, |
|
"DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); |
|
module_param_named(speed, dwc_otg_module_params.speed, int, 0444); |
|
MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); |
|
module_param_named(host_support_fs_ls_low_power, |
|
dwc_otg_module_params.host_support_fs_ls_low_power, int, |
|
0444); |
|
MODULE_PARM_DESC(host_support_fs_ls_low_power, |
|
"Support Low Power w/FS or LS 0=Support 1=Don't Support"); |
|
module_param_named(host_ls_low_power_phy_clk, |
|
dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); |
|
MODULE_PARM_DESC(host_ls_low_power_phy_clk, |
|
"Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); |
|
module_param_named(enable_dynamic_fifo, |
|
dwc_otg_module_params.enable_dynamic_fifo, int, 0444); |
|
MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); |
|
module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, |
|
0444); |
|
MODULE_PARM_DESC(data_fifo_size, |
|
"Total number of words in the data FIFO memory 32-32768"); |
|
module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, |
|
int, 0444); |
|
MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); |
|
module_param_named(dev_nperio_tx_fifo_size, |
|
dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); |
|
MODULE_PARM_DESC(dev_nperio_tx_fifo_size, |
|
"Number of words in the non-periodic Tx FIFO 16-32768"); |
|
module_param_named(dev_perio_tx_fifo_size_1, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_2, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_3, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_4, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_5, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_6, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_7, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_8, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_9, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_10, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_11, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_12, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_13, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_14, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(dev_perio_tx_fifo_size_15, |
|
dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); |
|
MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, |
|
"Number of words in the periodic Tx FIFO 4-768"); |
|
module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, |
|
int, 0444); |
|
MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); |
|
module_param_named(host_nperio_tx_fifo_size, |
|
dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); |
|
MODULE_PARM_DESC(host_nperio_tx_fifo_size, |
|
"Number of words in the non-periodic Tx FIFO 16-32768"); |
|
module_param_named(host_perio_tx_fifo_size, |
|
dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); |
|
MODULE_PARM_DESC(host_perio_tx_fifo_size, |
|
"Number of words in the host periodic Tx FIFO 16-32768"); |
|
module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, |
|
int, 0444); |
|
/** @todo Set the max to 512K, modify checks */ |
|
MODULE_PARM_DESC(max_transfer_size, |
|
"The maximum transfer size supported in bytes 2047-65535"); |
|
module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, |
|
int, 0444); |
|
MODULE_PARM_DESC(max_packet_count, |
|
"The maximum number of packets in a transfer 15-511"); |
|
module_param_named(host_channels, dwc_otg_module_params.host_channels, int, |
|
0444); |
|
MODULE_PARM_DESC(host_channels, |
|
"The number of host channel registers to use 1-16"); |
|
module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, |
|
0444); |
|
MODULE_PARM_DESC(dev_endpoints, |
|
"The number of endpoints in addition to EP0 available for device mode 1-15"); |
|
module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); |
|
MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); |
|
module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, |
|
0444); |
|
MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); |
|
module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); |
|
MODULE_PARM_DESC(phy_ulpi_ddr, |
|
"ULPI at double or single data rate 0=Single 1=Double"); |
|
module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, |
|
int, 0444); |
|
MODULE_PARM_DESC(phy_ulpi_ext_vbus, |
|
"ULPI PHY using internal or external vbus 0=Internal"); |
|
module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); |
|
MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); |
|
module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); |
|
MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); |
|
module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); |
|
MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); |
|
module_param_named(debug, g_dbg_lvl, int, 0444); |
|
MODULE_PARM_DESC(debug, ""); |
|
|
|
module_param_named(en_multiple_tx_fifo, |
|
dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); |
|
MODULE_PARM_DESC(en_multiple_tx_fifo, |
|
"Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); |
|
module_param_named(dev_tx_fifo_size_1, |
|
dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_2, |
|
dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_3, |
|
dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_4, |
|
dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_5, |
|
dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_6, |
|
dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_7, |
|
dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_8, |
|
dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_9, |
|
dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_10, |
|
dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_11, |
|
dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_12, |
|
dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_13, |
|
dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_14, |
|
dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); |
|
module_param_named(dev_tx_fifo_size_15, |
|
dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); |
|
MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); |
|
|
|
module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); |
|
MODULE_PARM_DESC(thr_ctl, |
|
"Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); |
|
module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, |
|
0444); |
|
MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); |
|
module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, |
|
0444); |
|
MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); |
|
|
|
module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444); |
|
module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444); |
|
module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444); |
|
MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled"); |
|
module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444); |
|
MODULE_PARM_DESC(ic_usb_cap, |
|
"IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled"); |
|
module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, |
|
0444); |
|
MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio"); |
|
module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444); |
|
MODULE_PARM_DESC(power_down, "Power Down Mode"); |
|
module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444); |
|
MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control"); |
|
module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444); |
|
MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK"); |
|
module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444); |
|
MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA"); |
|
module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444); |
|
MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support"); |
|
module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444); |
|
MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled"); |
|
module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444); |
|
MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0"); |
|
module_param(microframe_schedule, bool, 0444); |
|
MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler"); |
|
|
|
module_param(fiq_enable, bool, 0444); |
|
MODULE_PARM_DESC(fiq_enable, "Enable the FIQ"); |
|
module_param(nak_holdoff, ushort, 0644); |
|
MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8"); |
|
module_param(fiq_fsm_enable, bool, 0444); |
|
MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask"); |
|
module_param(fiq_fsm_mask, ushort, 0444); |
|
MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n" |
|
"Bit 0 : Non-periodic split transactions\n" |
|
"Bit 1 : Periodic split transactions\n" |
|
"Bit 2 : High-speed multi-transfer isochronous\n" |
|
"All other bits should be set 0."); |
|
module_param(int_ep_interval_min, ushort, 0644); |
|
MODULE_PARM_DESC(int_ep_interval_min, "Clamp high-speed Interrupt endpoints to a minimum polling interval.\n" |
|
"0..1 = Use endpoint default\n" |
|
"2..n = Minimum interval n microframes. Use powers of 2.\n"); |
|
|
|
module_param(cil_force_host, bool, 0644); |
|
MODULE_PARM_DESC(cil_force_host, "On a connector-ID status change, " |
|
"force Host Mode regardless of OTG state."); |
|
|
|
/** @page "Module Parameters" |
|
* |
|
* The following parameters may be specified when starting the module. |
|
* These parameters define how the DWC_otg controller should be |
|
* configured. Parameter values are passed to the CIL initialization |
|
* function dwc_otg_cil_init |
|
* |
|
* Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code> |
|
* |
|
|
|
<table> |
|
<tr><td>Parameter Name</td><td>Meaning</td></tr> |
|
|
|
<tr> |
|
<td>otg_cap</td> |
|
<td>Specifies the OTG capabilities. The driver will automatically detect the |
|
value for this parameter if none is specified. |
|
- 0: HNP and SRP capable (default, if available) |
|
- 1: SRP Only capable |
|
- 2: No HNP/SRP capable |
|
</td></tr> |
|
|
|
<tr> |
|
<td>dma_enable</td> |
|
<td>Specifies whether to use slave or DMA mode for accessing the data FIFOs. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- 0: Slave |
|
- 1: DMA (default, if available) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>dma_burst_size</td> |
|
<td>The DMA Burst size (applicable only for External DMA Mode). |
|
- Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>speed</td> |
|
<td>Specifies the maximum speed of operation in host and device mode. The |
|
actual speed depends on the speed of the attached device and the value of |
|
phy_type. |
|
- 0: High Speed (default) |
|
- 1: Full Speed |
|
</td></tr> |
|
|
|
<tr> |
|
<td>host_support_fs_ls_low_power</td> |
|
<td>Specifies whether low power mode is supported when attached to a Full |
|
Speed or Low Speed device in host mode. |
|
- 0: Don't support low power mode (default) |
|
- 1: Support low power mode |
|
</td></tr> |
|
|
|
<tr> |
|
<td>host_ls_low_power_phy_clk</td> |
|
<td>Specifies the PHY clock rate in low power mode when connected to a Low |
|
Speed device in host mode. This parameter is applicable only if |
|
HOST_SUPPORT_FS_LS_LOW_POWER is enabled. |
|
- 0: 48 MHz (default) |
|
- 1: 6 MHz |
|
</td></tr> |
|
|
|
<tr> |
|
<td>enable_dynamic_fifo</td> |
|
<td> Specifies whether FIFOs may be resized by the driver software. |
|
- 0: Use cC FIFO size parameters |
|
- 1: Allow dynamic FIFO sizing (default) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>data_fifo_size</td> |
|
<td>Total number of 4-byte words in the data FIFO memory. This memory |
|
includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. |
|
- Values: 32 to 32768 (default 8192) |
|
|
|
Note: The total FIFO memory depth in the FPGA configuration is 8192. |
|
</td></tr> |
|
|
|
<tr> |
|
<td>dev_rx_fifo_size</td> |
|
<td>Number of 4-byte words in the Rx FIFO in device mode when dynamic |
|
FIFO sizing is enabled. |
|
- Values: 16 to 32768 (default 1064) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>dev_nperio_tx_fifo_size</td> |
|
<td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when |
|
dynamic FIFO sizing is enabled. |
|
- Values: 16 to 32768 (default 1024) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td> |
|
<td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode |
|
when dynamic FIFO sizing is enabled. |
|
- Values: 4 to 768 (default 256) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>host_rx_fifo_size</td> |
|
<td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO |
|
sizing is enabled. |
|
- Values: 16 to 32768 (default 1024) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>host_nperio_tx_fifo_size</td> |
|
<td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when |
|
dynamic FIFO sizing is enabled in the core. |
|
- Values: 16 to 32768 (default 1024) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>host_perio_tx_fifo_size</td> |
|
<td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO |
|
sizing is enabled. |
|
- Values: 16 to 32768 (default 1024) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>max_transfer_size</td> |
|
<td>The maximum transfer size supported in bytes. |
|
- Values: 2047 to 65,535 (default 65,535) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>max_packet_count</td> |
|
<td>The maximum number of packets in a transfer. |
|
- Values: 15 to 511 (default 511) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>host_channels</td> |
|
<td>The number of host channel registers to use. |
|
- Values: 1 to 16 (default 12) |
|
|
|
Note: The FPGA configuration supports a maximum of 12 host channels. |
|
</td></tr> |
|
|
|
<tr> |
|
<td>dev_endpoints</td> |
|
<td>The number of endpoints in addition to EP0 available for device mode |
|
operations. |
|
- Values: 1 to 15 (default 6 IN and OUT) |
|
|
|
Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in |
|
addition to EP0. |
|
</td></tr> |
|
|
|
<tr> |
|
<td>phy_type</td> |
|
<td>Specifies the type of PHY interface to use. By default, the driver will |
|
automatically detect the phy_type. |
|
- 0: Full Speed |
|
- 1: UTMI+ (default, if available) |
|
- 2: ULPI |
|
</td></tr> |
|
|
|
<tr> |
|
<td>phy_utmi_width</td> |
|
<td>Specifies the UTMI+ Data Width. This parameter is applicable for a |
|
phy_type of UTMI+. Also, this parameter is applicable only if the |
|
OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the |
|
core has been configured to work at either data path width. |
|
- Values: 8 or 16 bits (default 16) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>phy_ulpi_ddr</td> |
|
<td>Specifies whether the ULPI operates at double or single data rate. This |
|
parameter is only applicable if phy_type is ULPI. |
|
- 0: single data rate ULPI interface with 8 bit wide data bus (default) |
|
- 1: double data rate ULPI interface with 4 bit wide data bus |
|
</td></tr> |
|
|
|
<tr> |
|
<td>i2c_enable</td> |
|
<td>Specifies whether to use the I2C interface for full speed PHY. This |
|
parameter is only applicable if PHY_TYPE is FS. |
|
- 0: Disabled (default) |
|
- 1: Enabled |
|
</td></tr> |
|
|
|
<tr> |
|
<td>ulpi_fs_ls</td> |
|
<td>Specifies whether to use ULPI FS/LS mode only. |
|
- 0: Disabled (default) |
|
- 1: Enabled |
|
</td></tr> |
|
|
|
<tr> |
|
<td>ts_dline</td> |
|
<td>Specifies whether term select D-Line pulsing for all PHYs is enabled. |
|
- 0: Disabled (default) |
|
- 1: Enabled |
|
</td></tr> |
|
|
|
<tr> |
|
<td>en_multiple_tx_fifo</td> |
|
<td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- 0: Disabled |
|
- 1: Enabled (default, if available) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>dev_tx_fifo_size_n (n = 1 to 15)</td> |
|
<td>Number of 4-byte words in each of the Tx FIFOs in device mode |
|
when dynamic FIFO sizing is enabled. |
|
- Values: 4 to 768 (default 256) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>tx_thr_length</td> |
|
<td>Transmit Threshold length in 32 bit double words |
|
- Values: 8 to 128 (default 64) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>rx_thr_length</td> |
|
<td>Receive Threshold length in 32 bit double words |
|
- Values: 8 to 128 (default 64) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>thr_ctl</td> |
|
<td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of |
|
this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and |
|
Rx transfers accordingly. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- Values: 0 to 7 (default 0) |
|
Bit values indicate: |
|
- 0: Thresholding disabled |
|
- 1: Thresholding enabled |
|
</td></tr> |
|
|
|
<tr> |
|
<td>dma_desc_enable</td> |
|
<td>Specifies whether to enable Descriptor DMA mode. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- 0: Descriptor DMA disabled |
|
- 1: Descriptor DMA (default, if available) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>mpi_enable</td> |
|
<td>Specifies whether to enable MPI enhancement mode. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- 0: MPI disabled (default) |
|
- 1: MPI enable |
|
</td></tr> |
|
|
|
<tr> |
|
<td>pti_enable</td> |
|
<td>Specifies whether to enable PTI enhancement support. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- 0: PTI disabled (default) |
|
- 1: PTI enable |
|
</td></tr> |
|
|
|
<tr> |
|
<td>lpm_enable</td> |
|
<td>Specifies whether to enable LPM support. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- 0: LPM disabled |
|
- 1: LPM enable (default, if available) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>ic_usb_cap</td> |
|
<td>Specifies whether to enable IC_USB capability. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- 0: IC_USB disabled (default, if available) |
|
- 1: IC_USB enable |
|
</td></tr> |
|
|
|
<tr> |
|
<td>ahb_thr_ratio</td> |
|
<td>Specifies AHB Threshold ratio. |
|
- Values: 0 to 3 (default 0) |
|
</td></tr> |
|
|
|
<tr> |
|
<td>power_down</td> |
|
<td>Specifies Power Down(Hibernation) Mode. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- 0: Power Down disabled (default) |
|
- 2: Power Down enabled |
|
</td></tr> |
|
|
|
<tr> |
|
<td>reload_ctl</td> |
|
<td>Specifies whether dynamic reloading of the HFIR register is allowed during |
|
run time. The driver will automatically detect the value for this parameter if |
|
none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0 |
|
the core might misbehave. |
|
- 0: Reload Control disabled (default) |
|
- 1: Reload Control enabled |
|
</td></tr> |
|
|
|
<tr> |
|
<td>dev_out_nak</td> |
|
<td>Specifies whether Device OUT NAK enhancement enabled or no. |
|
The driver will automatically detect the value for this parameter if |
|
none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1. |
|
- 0: The core does not set NAK after Bulk OUT transfer complete (default) |
|
- 1: The core sets NAK after Bulk OUT transfer complete |
|
</td></tr> |
|
|
|
<tr> |
|
<td>cont_on_bna</td> |
|
<td>Specifies whether Enable Continue on BNA enabled or no. |
|
After receiving BNA interrupt the core disables the endpoint,when the |
|
endpoint is re-enabled by the application the |
|
- 0: Core starts processing from the DOEPDMA descriptor (default) |
|
- 1: Core starts processing from the descriptor which received the BNA. |
|
This parameter is valid only when OTG_EN_DESC_DMA == 1b1. |
|
</td></tr> |
|
|
|
<tr> |
|
<td>ahb_single</td> |
|
<td>This bit when programmed supports SINGLE transfers for remainder data |
|
in a transfer for DMA mode of operation. |
|
- 0: The remainder data will be sent using INCR burst size (default) |
|
- 1: The remainder data will be sent using SINGLE burst size. |
|
</td></tr> |
|
|
|
<tr> |
|
<td>adp_enable</td> |
|
<td>Specifies whether ADP feature is enabled. |
|
The driver will automatically detect the value for this parameter if none is |
|
specified. |
|
- 0: ADP feature disabled (default) |
|
- 1: ADP feature enabled |
|
</td></tr> |
|
|
|
<tr> |
|
<td>otg_ver</td> |
|
<td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3 |
|
USB OTG device. |
|
- 0: OTG 2.0 support disabled (default) |
|
- 1: OTG 2.0 support enabled |
|
</td></tr> |
|
|
|
*/
|
|
|