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477 lines
12 KiB
477 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* c67x00-ll-hpi.c: Cypress C67X00 USB Low level interface using HPI |
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* |
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* Copyright (C) 2006-2008 Barco N.V. |
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* Derived from the Cypress cy7c67200/300 ezusb linux driver and |
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* based on multiple host controller drivers inside the linux kernel. |
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*/ |
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#include <asm/byteorder.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/jiffies.h> |
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#include <linux/usb/c67x00.h> |
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#include "c67x00.h" |
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#define COMM_REGS 14 |
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struct c67x00_lcp_int_data { |
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u16 regs[COMM_REGS]; |
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}; |
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/* -------------------------------------------------------------------------- */ |
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/* Interface definitions */ |
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#define COMM_ACK 0x0FED |
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#define COMM_NAK 0xDEAD |
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#define COMM_RESET 0xFA50 |
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#define COMM_EXEC_INT 0xCE01 |
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#define COMM_INT_NUM 0x01C2 |
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/* Registers 0 to COMM_REGS-1 */ |
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#define COMM_R(x) (0x01C4 + 2 * (x)) |
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#define HUSB_SIE_pCurrentTDPtr(x) ((x) ? 0x01B2 : 0x01B0) |
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#define HUSB_SIE_pTDListDone_Sem(x) ((x) ? 0x01B8 : 0x01B6) |
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#define HUSB_pEOT 0x01B4 |
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/* Software interrupts */ |
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/* 114, 115: */ |
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#define HUSB_SIE_INIT_INT(x) ((x) ? 0x0073 : 0x0072) |
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#define HUSB_RESET_INT 0x0074 |
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#define SUSB_INIT_INT 0x0071 |
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#define SUSB_INIT_INT_LOC (SUSB_INIT_INT * 2) |
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/* ----------------------------------------------------------------------- |
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* HPI implementation |
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* |
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* The c67x00 chip also support control via SPI or HSS serial |
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* interfaces. However, this driver assumes that register access can |
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* be performed from IRQ context. While this is a safe assumption with |
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* the HPI interface, it is not true for the serial interfaces. |
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*/ |
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/* HPI registers */ |
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#define HPI_DATA 0 |
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#define HPI_MAILBOX 1 |
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#define HPI_ADDR 2 |
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#define HPI_STATUS 3 |
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/* |
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* According to CY7C67300 specification (tables 140 and 141) HPI read and |
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* write cycle duration Tcyc must be at least 6T long, where T is 1/48MHz, |
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* which is 125ns. |
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*/ |
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#define HPI_T_CYC_NS 125 |
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static inline u16 hpi_read_reg(struct c67x00_device *dev, int reg) |
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{ |
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ndelay(HPI_T_CYC_NS); |
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return __raw_readw(dev->hpi.base + reg * dev->hpi.regstep); |
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} |
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static inline void hpi_write_reg(struct c67x00_device *dev, int reg, u16 value) |
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{ |
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ndelay(HPI_T_CYC_NS); |
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__raw_writew(value, dev->hpi.base + reg * dev->hpi.regstep); |
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} |
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static inline u16 hpi_read_word_nolock(struct c67x00_device *dev, u16 reg) |
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{ |
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hpi_write_reg(dev, HPI_ADDR, reg); |
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return hpi_read_reg(dev, HPI_DATA); |
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} |
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static u16 hpi_read_word(struct c67x00_device *dev, u16 reg) |
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{ |
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u16 value; |
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unsigned long flags; |
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spin_lock_irqsave(&dev->hpi.lock, flags); |
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value = hpi_read_word_nolock(dev, reg); |
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spin_unlock_irqrestore(&dev->hpi.lock, flags); |
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return value; |
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} |
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static void hpi_write_word_nolock(struct c67x00_device *dev, u16 reg, u16 value) |
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{ |
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hpi_write_reg(dev, HPI_ADDR, reg); |
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hpi_write_reg(dev, HPI_DATA, value); |
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} |
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static void hpi_write_word(struct c67x00_device *dev, u16 reg, u16 value) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&dev->hpi.lock, flags); |
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hpi_write_word_nolock(dev, reg, value); |
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spin_unlock_irqrestore(&dev->hpi.lock, flags); |
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} |
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/* |
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* Only data is little endian, addr has cpu endianess |
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*/ |
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static void hpi_write_words_le16(struct c67x00_device *dev, u16 addr, |
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__le16 *data, u16 count) |
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{ |
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unsigned long flags; |
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int i; |
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spin_lock_irqsave(&dev->hpi.lock, flags); |
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hpi_write_reg(dev, HPI_ADDR, addr); |
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for (i = 0; i < count; i++) |
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hpi_write_reg(dev, HPI_DATA, le16_to_cpu(*data++)); |
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spin_unlock_irqrestore(&dev->hpi.lock, flags); |
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} |
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/* |
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* Only data is little endian, addr has cpu endianess |
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*/ |
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static void hpi_read_words_le16(struct c67x00_device *dev, u16 addr, |
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__le16 *data, u16 count) |
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{ |
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unsigned long flags; |
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int i; |
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spin_lock_irqsave(&dev->hpi.lock, flags); |
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hpi_write_reg(dev, HPI_ADDR, addr); |
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for (i = 0; i < count; i++) |
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*data++ = cpu_to_le16(hpi_read_reg(dev, HPI_DATA)); |
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spin_unlock_irqrestore(&dev->hpi.lock, flags); |
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} |
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static void hpi_set_bits(struct c67x00_device *dev, u16 reg, u16 mask) |
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{ |
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u16 value; |
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unsigned long flags; |
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spin_lock_irqsave(&dev->hpi.lock, flags); |
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value = hpi_read_word_nolock(dev, reg); |
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hpi_write_word_nolock(dev, reg, value | mask); |
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spin_unlock_irqrestore(&dev->hpi.lock, flags); |
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} |
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static void hpi_clear_bits(struct c67x00_device *dev, u16 reg, u16 mask) |
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{ |
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u16 value; |
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unsigned long flags; |
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spin_lock_irqsave(&dev->hpi.lock, flags); |
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value = hpi_read_word_nolock(dev, reg); |
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hpi_write_word_nolock(dev, reg, value & ~mask); |
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spin_unlock_irqrestore(&dev->hpi.lock, flags); |
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} |
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static u16 hpi_recv_mbox(struct c67x00_device *dev) |
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{ |
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u16 value; |
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unsigned long flags; |
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spin_lock_irqsave(&dev->hpi.lock, flags); |
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value = hpi_read_reg(dev, HPI_MAILBOX); |
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spin_unlock_irqrestore(&dev->hpi.lock, flags); |
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return value; |
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} |
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static u16 hpi_send_mbox(struct c67x00_device *dev, u16 value) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&dev->hpi.lock, flags); |
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hpi_write_reg(dev, HPI_MAILBOX, value); |
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spin_unlock_irqrestore(&dev->hpi.lock, flags); |
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return value; |
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} |
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u16 c67x00_ll_hpi_status(struct c67x00_device *dev) |
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{ |
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u16 value; |
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unsigned long flags; |
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spin_lock_irqsave(&dev->hpi.lock, flags); |
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value = hpi_read_reg(dev, HPI_STATUS); |
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spin_unlock_irqrestore(&dev->hpi.lock, flags); |
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return value; |
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} |
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void c67x00_ll_hpi_reg_init(struct c67x00_device *dev) |
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{ |
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int i; |
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hpi_recv_mbox(dev); |
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c67x00_ll_hpi_status(dev); |
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hpi_write_word(dev, HPI_IRQ_ROUTING_REG, 0); |
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for (i = 0; i < C67X00_SIES; i++) { |
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hpi_write_word(dev, SIEMSG_REG(i), 0); |
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hpi_read_word(dev, SIEMSG_REG(i)); |
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} |
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} |
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void c67x00_ll_hpi_enable_sofeop(struct c67x00_sie *sie) |
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{ |
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hpi_set_bits(sie->dev, HPI_IRQ_ROUTING_REG, |
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SOFEOP_TO_HPI_EN(sie->sie_num)); |
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} |
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void c67x00_ll_hpi_disable_sofeop(struct c67x00_sie *sie) |
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{ |
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hpi_clear_bits(sie->dev, HPI_IRQ_ROUTING_REG, |
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SOFEOP_TO_HPI_EN(sie->sie_num)); |
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} |
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/* -------------------------------------------------------------------------- */ |
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/* Transactions */ |
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static inline int ll_recv_msg(struct c67x00_device *dev) |
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{ |
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u16 res; |
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res = wait_for_completion_timeout(&dev->hpi.lcp.msg_received, 5 * HZ); |
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WARN_ON(!res); |
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return (res == 0) ? -EIO : 0; |
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} |
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/* -------------------------------------------------------------------------- */ |
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/* General functions */ |
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u16 c67x00_ll_fetch_siemsg(struct c67x00_device *dev, int sie_num) |
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{ |
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u16 val; |
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val = hpi_read_word(dev, SIEMSG_REG(sie_num)); |
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/* clear register to allow next message */ |
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hpi_write_word(dev, SIEMSG_REG(sie_num), 0); |
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return val; |
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} |
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u16 c67x00_ll_get_usb_ctl(struct c67x00_sie *sie) |
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{ |
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return hpi_read_word(sie->dev, USB_CTL_REG(sie->sie_num)); |
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} |
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/* |
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* c67x00_ll_usb_clear_status - clear the USB status bits |
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*/ |
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void c67x00_ll_usb_clear_status(struct c67x00_sie *sie, u16 bits) |
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{ |
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hpi_write_word(sie->dev, USB_STAT_REG(sie->sie_num), bits); |
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} |
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u16 c67x00_ll_usb_get_status(struct c67x00_sie *sie) |
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{ |
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return hpi_read_word(sie->dev, USB_STAT_REG(sie->sie_num)); |
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} |
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/* -------------------------------------------------------------------------- */ |
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static int c67x00_comm_exec_int(struct c67x00_device *dev, u16 nr, |
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struct c67x00_lcp_int_data *data) |
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{ |
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int i, rc; |
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mutex_lock(&dev->hpi.lcp.mutex); |
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hpi_write_word(dev, COMM_INT_NUM, nr); |
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for (i = 0; i < COMM_REGS; i++) |
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hpi_write_word(dev, COMM_R(i), data->regs[i]); |
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hpi_send_mbox(dev, COMM_EXEC_INT); |
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rc = ll_recv_msg(dev); |
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mutex_unlock(&dev->hpi.lcp.mutex); |
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return rc; |
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} |
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/* -------------------------------------------------------------------------- */ |
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/* Host specific functions */ |
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void c67x00_ll_set_husb_eot(struct c67x00_device *dev, u16 value) |
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{ |
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mutex_lock(&dev->hpi.lcp.mutex); |
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hpi_write_word(dev, HUSB_pEOT, value); |
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mutex_unlock(&dev->hpi.lcp.mutex); |
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} |
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static inline void c67x00_ll_husb_sie_init(struct c67x00_sie *sie) |
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{ |
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struct c67x00_device *dev = sie->dev; |
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struct c67x00_lcp_int_data data; |
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int rc; |
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rc = c67x00_comm_exec_int(dev, HUSB_SIE_INIT_INT(sie->sie_num), &data); |
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BUG_ON(rc); /* No return path for error code; crash spectacularly */ |
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} |
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void c67x00_ll_husb_reset(struct c67x00_sie *sie, int port) |
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{ |
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struct c67x00_device *dev = sie->dev; |
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struct c67x00_lcp_int_data data; |
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int rc; |
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data.regs[0] = 50; /* Reset USB port for 50ms */ |
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data.regs[1] = port | (sie->sie_num << 1); |
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rc = c67x00_comm_exec_int(dev, HUSB_RESET_INT, &data); |
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BUG_ON(rc); /* No return path for error code; crash spectacularly */ |
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} |
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void c67x00_ll_husb_set_current_td(struct c67x00_sie *sie, u16 addr) |
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{ |
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hpi_write_word(sie->dev, HUSB_SIE_pCurrentTDPtr(sie->sie_num), addr); |
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} |
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u16 c67x00_ll_husb_get_current_td(struct c67x00_sie *sie) |
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{ |
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return hpi_read_word(sie->dev, HUSB_SIE_pCurrentTDPtr(sie->sie_num)); |
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} |
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u16 c67x00_ll_husb_get_frame(struct c67x00_sie *sie) |
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{ |
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return hpi_read_word(sie->dev, HOST_FRAME_REG(sie->sie_num)); |
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} |
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void c67x00_ll_husb_init_host_port(struct c67x00_sie *sie) |
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{ |
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/* Set port into host mode */ |
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hpi_set_bits(sie->dev, USB_CTL_REG(sie->sie_num), HOST_MODE); |
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c67x00_ll_husb_sie_init(sie); |
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/* Clear interrupts */ |
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c67x00_ll_usb_clear_status(sie, HOST_STAT_MASK); |
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/* Check */ |
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if (!(hpi_read_word(sie->dev, USB_CTL_REG(sie->sie_num)) & HOST_MODE)) |
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dev_warn(sie_dev(sie), |
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"SIE %d not set to host mode\n", sie->sie_num); |
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} |
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void c67x00_ll_husb_reset_port(struct c67x00_sie *sie, int port) |
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{ |
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/* Clear connect change */ |
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c67x00_ll_usb_clear_status(sie, PORT_CONNECT_CHANGE(port)); |
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/* Enable interrupts */ |
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hpi_set_bits(sie->dev, HPI_IRQ_ROUTING_REG, |
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SOFEOP_TO_CPU_EN(sie->sie_num)); |
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hpi_set_bits(sie->dev, HOST_IRQ_EN_REG(sie->sie_num), |
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SOF_EOP_IRQ_EN | DONE_IRQ_EN); |
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/* Enable pull down transistors */ |
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hpi_set_bits(sie->dev, USB_CTL_REG(sie->sie_num), PORT_RES_EN(port)); |
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} |
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/* -------------------------------------------------------------------------- */ |
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void c67x00_ll_irq(struct c67x00_device *dev, u16 int_status) |
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{ |
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if ((int_status & MBX_OUT_FLG) == 0) |
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return; |
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dev->hpi.lcp.last_msg = hpi_recv_mbox(dev); |
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complete(&dev->hpi.lcp.msg_received); |
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} |
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/* -------------------------------------------------------------------------- */ |
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int c67x00_ll_reset(struct c67x00_device *dev) |
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{ |
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int rc; |
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mutex_lock(&dev->hpi.lcp.mutex); |
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hpi_send_mbox(dev, COMM_RESET); |
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rc = ll_recv_msg(dev); |
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mutex_unlock(&dev->hpi.lcp.mutex); |
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return rc; |
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} |
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/* -------------------------------------------------------------------------- */ |
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/* |
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* c67x00_ll_write_mem_le16 - write into c67x00 memory |
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* Only data is little endian, addr has cpu endianess. |
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*/ |
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void c67x00_ll_write_mem_le16(struct c67x00_device *dev, u16 addr, |
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void *data, int len) |
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{ |
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u8 *buf = data; |
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/* Sanity check */ |
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if (addr + len > 0xffff) { |
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dev_err(&dev->pdev->dev, |
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"Trying to write beyond writable region!\n"); |
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return; |
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} |
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if (addr & 0x01) { |
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/* unaligned access */ |
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u16 tmp; |
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tmp = hpi_read_word(dev, addr - 1); |
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tmp = (tmp & 0x00ff) | (*buf++ << 8); |
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hpi_write_word(dev, addr - 1, tmp); |
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addr++; |
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len--; |
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} |
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hpi_write_words_le16(dev, addr, (__le16 *)buf, len / 2); |
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buf += len & ~0x01; |
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addr += len & ~0x01; |
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len &= 0x01; |
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if (len) { |
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u16 tmp; |
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tmp = hpi_read_word(dev, addr); |
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tmp = (tmp & 0xff00) | *buf; |
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hpi_write_word(dev, addr, tmp); |
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} |
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} |
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/* |
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* c67x00_ll_read_mem_le16 - read from c67x00 memory |
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* Only data is little endian, addr has cpu endianess. |
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*/ |
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void c67x00_ll_read_mem_le16(struct c67x00_device *dev, u16 addr, |
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void *data, int len) |
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{ |
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u8 *buf = data; |
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if (addr & 0x01) { |
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/* unaligned access */ |
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u16 tmp; |
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tmp = hpi_read_word(dev, addr - 1); |
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*buf++ = (tmp >> 8) & 0x00ff; |
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addr++; |
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len--; |
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} |
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hpi_read_words_le16(dev, addr, (__le16 *)buf, len / 2); |
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buf += len & ~0x01; |
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addr += len & ~0x01; |
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len &= 0x01; |
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if (len) { |
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u16 tmp; |
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tmp = hpi_read_word(dev, addr); |
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*buf = tmp & 0x00ff; |
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} |
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} |
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/* -------------------------------------------------------------------------- */ |
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void c67x00_ll_init(struct c67x00_device *dev) |
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{ |
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mutex_init(&dev->hpi.lcp.mutex); |
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init_completion(&dev->hpi.lcp.msg_received); |
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} |
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void c67x00_ll_release(struct c67x00_device *dev) |
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{ |
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}
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