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980 lines
26 KiB
980 lines
26 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Marvell EBU Armada SoCs thermal sensor driver |
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* |
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* Copyright (C) 2013 Marvell |
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*/ |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/of.h> |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/platform_device.h> |
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#include <linux/of_device.h> |
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#include <linux/thermal.h> |
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#include <linux/iopoll.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#include <linux/interrupt.h> |
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#include "thermal_core.h" |
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/* Thermal Manager Control and Status Register */ |
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#define PMU_TDC0_SW_RST_MASK (0x1 << 1) |
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#define PMU_TM_DISABLE_OFFS 0 |
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#define PMU_TM_DISABLE_MASK (0x1 << PMU_TM_DISABLE_OFFS) |
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#define PMU_TDC0_REF_CAL_CNT_OFFS 11 |
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#define PMU_TDC0_REF_CAL_CNT_MASK (0x1ff << PMU_TDC0_REF_CAL_CNT_OFFS) |
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#define PMU_TDC0_OTF_CAL_MASK (0x1 << 30) |
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#define PMU_TDC0_START_CAL_MASK (0x1 << 25) |
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#define A375_UNIT_CONTROL_SHIFT 27 |
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#define A375_UNIT_CONTROL_MASK 0x7 |
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#define A375_READOUT_INVERT BIT(15) |
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#define A375_HW_RESETn BIT(8) |
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/* Errata fields */ |
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#define CONTROL0_TSEN_TC_TRIM_MASK 0x7 |
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#define CONTROL0_TSEN_TC_TRIM_VAL 0x3 |
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#define CONTROL0_TSEN_START BIT(0) |
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#define CONTROL0_TSEN_RESET BIT(1) |
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#define CONTROL0_TSEN_ENABLE BIT(2) |
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#define CONTROL0_TSEN_AVG_BYPASS BIT(6) |
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#define CONTROL0_TSEN_CHAN_SHIFT 13 |
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#define CONTROL0_TSEN_CHAN_MASK 0xF |
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#define CONTROL0_TSEN_OSR_SHIFT 24 |
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#define CONTROL0_TSEN_OSR_MAX 0x3 |
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#define CONTROL0_TSEN_MODE_SHIFT 30 |
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#define CONTROL0_TSEN_MODE_EXTERNAL 0x2 |
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#define CONTROL0_TSEN_MODE_MASK 0x3 |
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#define CONTROL1_TSEN_AVG_MASK 0x7 |
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#define CONTROL1_EXT_TSEN_SW_RESET BIT(7) |
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#define CONTROL1_EXT_TSEN_HW_RESETn BIT(8) |
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#define CONTROL1_TSEN_INT_EN BIT(25) |
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#define CONTROL1_TSEN_SELECT_OFF 21 |
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#define CONTROL1_TSEN_SELECT_MASK 0x3 |
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#define STATUS_POLL_PERIOD_US 1000 |
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#define STATUS_POLL_TIMEOUT_US 100000 |
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#define OVERHEAT_INT_POLL_DELAY_MS 1000 |
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struct armada_thermal_data; |
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/* Marvell EBU Thermal Sensor Dev Structure */ |
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struct armada_thermal_priv { |
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struct device *dev; |
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struct regmap *syscon; |
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char zone_name[THERMAL_NAME_LENGTH]; |
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/* serialize temperature reads/updates */ |
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struct mutex update_lock; |
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struct armada_thermal_data *data; |
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struct thermal_zone_device *overheat_sensor; |
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int interrupt_source; |
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int current_channel; |
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long current_threshold; |
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long current_hysteresis; |
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}; |
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struct armada_thermal_data { |
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/* Initialize the thermal IC */ |
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void (*init)(struct platform_device *pdev, |
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struct armada_thermal_priv *priv); |
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/* Formula coeficients: temp = (b - m * reg) / div */ |
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s64 coef_b; |
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s64 coef_m; |
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u32 coef_div; |
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bool inverted; |
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bool signed_sample; |
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/* Register shift and mask to access the sensor temperature */ |
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unsigned int temp_shift; |
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unsigned int temp_mask; |
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unsigned int thresh_shift; |
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unsigned int hyst_shift; |
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unsigned int hyst_mask; |
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u32 is_valid_bit; |
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/* Syscon access */ |
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unsigned int syscon_control0_off; |
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unsigned int syscon_control1_off; |
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unsigned int syscon_status_off; |
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unsigned int dfx_irq_cause_off; |
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unsigned int dfx_irq_mask_off; |
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unsigned int dfx_overheat_irq; |
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unsigned int dfx_server_irq_mask_off; |
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unsigned int dfx_server_irq_en; |
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/* One sensor is in the thermal IC, the others are in the CPUs if any */ |
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unsigned int cpu_nr; |
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}; |
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struct armada_drvdata { |
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enum drvtype { |
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LEGACY, |
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SYSCON |
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} type; |
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union { |
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struct armada_thermal_priv *priv; |
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struct thermal_zone_device *tz; |
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} data; |
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}; |
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/* |
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* struct armada_thermal_sensor - hold the information of one thermal sensor |
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* @thermal: pointer to the local private structure |
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* @tzd: pointer to the thermal zone device |
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* @id: identifier of the thermal sensor |
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*/ |
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struct armada_thermal_sensor { |
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struct armada_thermal_priv *priv; |
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int id; |
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}; |
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static void armadaxp_init(struct platform_device *pdev, |
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struct armada_thermal_priv *priv) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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u32 reg; |
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regmap_read(priv->syscon, data->syscon_control1_off, ®); |
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reg |= PMU_TDC0_OTF_CAL_MASK; |
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/* Reference calibration value */ |
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reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; |
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reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS); |
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/* Reset the sensor */ |
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reg |= PMU_TDC0_SW_RST_MASK; |
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regmap_write(priv->syscon, data->syscon_control1_off, reg); |
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reg &= ~PMU_TDC0_SW_RST_MASK; |
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regmap_write(priv->syscon, data->syscon_control1_off, reg); |
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/* Enable the sensor */ |
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regmap_read(priv->syscon, data->syscon_status_off, ®); |
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reg &= ~PMU_TM_DISABLE_MASK; |
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regmap_write(priv->syscon, data->syscon_status_off, reg); |
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} |
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static void armada370_init(struct platform_device *pdev, |
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struct armada_thermal_priv *priv) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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u32 reg; |
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regmap_read(priv->syscon, data->syscon_control1_off, ®); |
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reg |= PMU_TDC0_OTF_CAL_MASK; |
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/* Reference calibration value */ |
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reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; |
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reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS); |
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/* Reset the sensor */ |
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reg &= ~PMU_TDC0_START_CAL_MASK; |
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regmap_write(priv->syscon, data->syscon_control1_off, reg); |
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msleep(10); |
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} |
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static void armada375_init(struct platform_device *pdev, |
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struct armada_thermal_priv *priv) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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u32 reg; |
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regmap_read(priv->syscon, data->syscon_control1_off, ®); |
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reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT); |
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reg &= ~A375_READOUT_INVERT; |
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reg &= ~A375_HW_RESETn; |
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regmap_write(priv->syscon, data->syscon_control1_off, reg); |
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msleep(20); |
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reg |= A375_HW_RESETn; |
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regmap_write(priv->syscon, data->syscon_control1_off, reg); |
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msleep(50); |
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} |
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static int armada_wait_sensor_validity(struct armada_thermal_priv *priv) |
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{ |
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u32 reg; |
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return regmap_read_poll_timeout(priv->syscon, |
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priv->data->syscon_status_off, reg, |
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reg & priv->data->is_valid_bit, |
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STATUS_POLL_PERIOD_US, |
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STATUS_POLL_TIMEOUT_US); |
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} |
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static void armada380_init(struct platform_device *pdev, |
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struct armada_thermal_priv *priv) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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u32 reg; |
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/* Disable the HW/SW reset */ |
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regmap_read(priv->syscon, data->syscon_control1_off, ®); |
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reg |= CONTROL1_EXT_TSEN_HW_RESETn; |
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reg &= ~CONTROL1_EXT_TSEN_SW_RESET; |
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regmap_write(priv->syscon, data->syscon_control1_off, reg); |
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/* Set Tsen Tc Trim to correct default value (errata #132698) */ |
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regmap_read(priv->syscon, data->syscon_control0_off, ®); |
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reg &= ~CONTROL0_TSEN_TC_TRIM_MASK; |
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reg |= CONTROL0_TSEN_TC_TRIM_VAL; |
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regmap_write(priv->syscon, data->syscon_control0_off, reg); |
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} |
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static void armada_ap806_init(struct platform_device *pdev, |
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struct armada_thermal_priv *priv) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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u32 reg; |
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regmap_read(priv->syscon, data->syscon_control0_off, ®); |
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reg &= ~CONTROL0_TSEN_RESET; |
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reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE; |
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/* Sample every ~2ms */ |
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reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT; |
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/* Enable average (2 samples by default) */ |
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reg &= ~CONTROL0_TSEN_AVG_BYPASS; |
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regmap_write(priv->syscon, data->syscon_control0_off, reg); |
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} |
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static void armada_cp110_init(struct platform_device *pdev, |
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struct armada_thermal_priv *priv) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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u32 reg; |
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armada380_init(pdev, priv); |
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/* Sample every ~2ms */ |
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regmap_read(priv->syscon, data->syscon_control0_off, ®); |
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reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT; |
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regmap_write(priv->syscon, data->syscon_control0_off, reg); |
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/* Average the output value over 2^1 = 2 samples */ |
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regmap_read(priv->syscon, data->syscon_control1_off, ®); |
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reg &= ~CONTROL1_TSEN_AVG_MASK; |
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reg |= 1; |
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regmap_write(priv->syscon, data->syscon_control1_off, reg); |
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} |
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static bool armada_is_valid(struct armada_thermal_priv *priv) |
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{ |
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u32 reg; |
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if (!priv->data->is_valid_bit) |
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return true; |
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regmap_read(priv->syscon, priv->data->syscon_status_off, ®); |
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return reg & priv->data->is_valid_bit; |
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} |
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static void armada_enable_overheat_interrupt(struct armada_thermal_priv *priv) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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u32 reg; |
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/* Clear DFX temperature IRQ cause */ |
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regmap_read(priv->syscon, data->dfx_irq_cause_off, ®); |
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/* Enable DFX Temperature IRQ */ |
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regmap_read(priv->syscon, data->dfx_irq_mask_off, ®); |
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reg |= data->dfx_overheat_irq; |
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regmap_write(priv->syscon, data->dfx_irq_mask_off, reg); |
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/* Enable DFX server IRQ */ |
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regmap_read(priv->syscon, data->dfx_server_irq_mask_off, ®); |
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reg |= data->dfx_server_irq_en; |
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regmap_write(priv->syscon, data->dfx_server_irq_mask_off, reg); |
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/* Enable overheat interrupt */ |
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regmap_read(priv->syscon, data->syscon_control1_off, ®); |
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reg |= CONTROL1_TSEN_INT_EN; |
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regmap_write(priv->syscon, data->syscon_control1_off, reg); |
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} |
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static void __maybe_unused |
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armada_disable_overheat_interrupt(struct armada_thermal_priv *priv) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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u32 reg; |
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regmap_read(priv->syscon, data->syscon_control1_off, ®); |
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reg &= ~CONTROL1_TSEN_INT_EN; |
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regmap_write(priv->syscon, data->syscon_control1_off, reg); |
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} |
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/* There is currently no board with more than one sensor per channel */ |
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static int armada_select_channel(struct armada_thermal_priv *priv, int channel) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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u32 ctrl0; |
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if (channel < 0 || channel > priv->data->cpu_nr) |
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return -EINVAL; |
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if (priv->current_channel == channel) |
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return 0; |
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/* Stop the measurements */ |
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regmap_read(priv->syscon, data->syscon_control0_off, &ctrl0); |
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ctrl0 &= ~CONTROL0_TSEN_START; |
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regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); |
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/* Reset the mode, internal sensor will be automatically selected */ |
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ctrl0 &= ~(CONTROL0_TSEN_MODE_MASK << CONTROL0_TSEN_MODE_SHIFT); |
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/* Other channels are external and should be selected accordingly */ |
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if (channel) { |
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/* Change the mode to external */ |
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ctrl0 |= CONTROL0_TSEN_MODE_EXTERNAL << |
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CONTROL0_TSEN_MODE_SHIFT; |
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/* Select the sensor */ |
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ctrl0 &= ~(CONTROL0_TSEN_CHAN_MASK << CONTROL0_TSEN_CHAN_SHIFT); |
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ctrl0 |= (channel - 1) << CONTROL0_TSEN_CHAN_SHIFT; |
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} |
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/* Actually set the mode/channel */ |
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regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); |
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priv->current_channel = channel; |
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/* Re-start the measurements */ |
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ctrl0 |= CONTROL0_TSEN_START; |
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regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); |
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/* |
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* The IP has a latency of ~15ms, so after updating the selected source, |
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* we must absolutely wait for the sensor validity bit to ensure we read |
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* actual data. |
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*/ |
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if (armada_wait_sensor_validity(priv)) { |
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dev_err(priv->dev, |
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"Temperature sensor reading not valid\n"); |
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return -EIO; |
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} |
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return 0; |
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} |
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static int armada_read_sensor(struct armada_thermal_priv *priv, int *temp) |
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{ |
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u32 reg, div; |
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s64 sample, b, m; |
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regmap_read(priv->syscon, priv->data->syscon_status_off, ®); |
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reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask; |
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if (priv->data->signed_sample) |
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/* The most significant bit is the sign bit */ |
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sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1); |
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else |
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sample = reg; |
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/* Get formula coeficients */ |
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b = priv->data->coef_b; |
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m = priv->data->coef_m; |
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div = priv->data->coef_div; |
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if (priv->data->inverted) |
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*temp = div_s64((m * sample) - b, div); |
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else |
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*temp = div_s64(b - (m * sample), div); |
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return 0; |
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} |
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static int armada_get_temp_legacy(struct thermal_zone_device *thermal, |
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int *temp) |
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{ |
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struct armada_thermal_priv *priv = thermal->devdata; |
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int ret; |
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/* Valid check */ |
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if (!armada_is_valid(priv)) { |
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dev_err(priv->dev, |
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"Temperature sensor reading not valid\n"); |
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return -EIO; |
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} |
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/* Do the actual reading */ |
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ret = armada_read_sensor(priv, temp); |
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return ret; |
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} |
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static struct thermal_zone_device_ops legacy_ops = { |
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.get_temp = armada_get_temp_legacy, |
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}; |
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static int armada_get_temp(void *_sensor, int *temp) |
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{ |
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struct armada_thermal_sensor *sensor = _sensor; |
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struct armada_thermal_priv *priv = sensor->priv; |
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int ret; |
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mutex_lock(&priv->update_lock); |
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/* Select the desired channel */ |
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ret = armada_select_channel(priv, sensor->id); |
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if (ret) |
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goto unlock_mutex; |
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/* Do the actual reading */ |
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ret = armada_read_sensor(priv, temp); |
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if (ret) |
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goto unlock_mutex; |
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/* |
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* Select back the interrupt source channel from which a potential |
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* critical trip point has been set. |
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*/ |
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ret = armada_select_channel(priv, priv->interrupt_source); |
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unlock_mutex: |
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mutex_unlock(&priv->update_lock); |
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return ret; |
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} |
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static const struct thermal_zone_of_device_ops of_ops = { |
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.get_temp = armada_get_temp, |
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}; |
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static unsigned int armada_mc_to_reg_temp(struct armada_thermal_data *data, |
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unsigned int temp_mc) |
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{ |
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s64 b = data->coef_b; |
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s64 m = data->coef_m; |
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s64 div = data->coef_div; |
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unsigned int sample; |
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if (data->inverted) |
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sample = div_s64(((temp_mc * div) + b), m); |
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else |
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sample = div_s64((b - (temp_mc * div)), m); |
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return sample & data->temp_mask; |
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} |
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/* |
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* The documentation states: |
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* high/low watermark = threshold +/- 0.4761 * 2^(hysteresis + 2) |
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* which is the mathematical derivation for: |
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* 0x0 <=> 1.9°C, 0x1 <=> 3.8°C, 0x2 <=> 7.6°C, 0x3 <=> 15.2°C |
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*/ |
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static unsigned int hyst_levels_mc[] = {1900, 3800, 7600, 15200}; |
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static unsigned int armada_mc_to_reg_hyst(struct armada_thermal_data *data, |
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unsigned int hyst_mc) |
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{ |
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int i; |
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/* |
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* We will always take the smallest possible hysteresis to avoid risking |
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* the hardware integrity by enlarging the threshold by +8°C in the |
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* worst case. |
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*/ |
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for (i = ARRAY_SIZE(hyst_levels_mc) - 1; i > 0; i--) |
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if (hyst_mc >= hyst_levels_mc[i]) |
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break; |
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return i & data->hyst_mask; |
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} |
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static void armada_set_overheat_thresholds(struct armada_thermal_priv *priv, |
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int thresh_mc, int hyst_mc) |
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{ |
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struct armada_thermal_data *data = priv->data; |
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unsigned int threshold = armada_mc_to_reg_temp(data, thresh_mc); |
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unsigned int hysteresis = armada_mc_to_reg_hyst(data, hyst_mc); |
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u32 ctrl1; |
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regmap_read(priv->syscon, data->syscon_control1_off, &ctrl1); |
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/* Set Threshold */ |
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if (thresh_mc >= 0) { |
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ctrl1 &= ~(data->temp_mask << data->thresh_shift); |
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ctrl1 |= threshold << data->thresh_shift; |
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priv->current_threshold = thresh_mc; |
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} |
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/* Set Hysteresis */ |
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if (hyst_mc >= 0) { |
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ctrl1 &= ~(data->hyst_mask << data->hyst_shift); |
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ctrl1 |= hysteresis << data->hyst_shift; |
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priv->current_hysteresis = hyst_mc; |
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} |
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regmap_write(priv->syscon, data->syscon_control1_off, ctrl1); |
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} |
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static irqreturn_t armada_overheat_isr(int irq, void *blob) |
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{ |
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/* |
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* Disable the IRQ and continue in thread context (thermal core |
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* notification and temperature monitoring). |
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*/ |
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disable_irq_nosync(irq); |
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return IRQ_WAKE_THREAD; |
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} |
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static irqreturn_t armada_overheat_isr_thread(int irq, void *blob) |
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{ |
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struct armada_thermal_priv *priv = blob; |
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int low_threshold = priv->current_threshold - priv->current_hysteresis; |
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int temperature; |
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u32 dummy; |
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int ret; |
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/* Notify the core in thread context */ |
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thermal_zone_device_update(priv->overheat_sensor, |
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THERMAL_EVENT_UNSPECIFIED); |
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/* |
|
* The overheat interrupt must be cleared by reading the DFX interrupt |
|
* cause _after_ the temperature has fallen down to the low threshold. |
|
* Otherwise future interrupts might not be served. |
|
*/ |
|
do { |
|
msleep(OVERHEAT_INT_POLL_DELAY_MS); |
|
mutex_lock(&priv->update_lock); |
|
ret = armada_read_sensor(priv, &temperature); |
|
mutex_unlock(&priv->update_lock); |
|
if (ret) |
|
goto enable_irq; |
|
} while (temperature >= low_threshold); |
|
|
|
regmap_read(priv->syscon, priv->data->dfx_irq_cause_off, &dummy); |
|
|
|
/* Notify the thermal core that the temperature is acceptable again */ |
|
thermal_zone_device_update(priv->overheat_sensor, |
|
THERMAL_EVENT_UNSPECIFIED); |
|
|
|
enable_irq: |
|
enable_irq(irq); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static const struct armada_thermal_data armadaxp_data = { |
|
.init = armadaxp_init, |
|
.temp_shift = 10, |
|
.temp_mask = 0x1ff, |
|
.coef_b = 3153000000ULL, |
|
.coef_m = 10000000ULL, |
|
.coef_div = 13825, |
|
.syscon_status_off = 0xb0, |
|
.syscon_control1_off = 0x2d0, |
|
}; |
|
|
|
static const struct armada_thermal_data armada370_data = { |
|
.init = armada370_init, |
|
.is_valid_bit = BIT(9), |
|
.temp_shift = 10, |
|
.temp_mask = 0x1ff, |
|
.coef_b = 3153000000ULL, |
|
.coef_m = 10000000ULL, |
|
.coef_div = 13825, |
|
.syscon_status_off = 0x0, |
|
.syscon_control1_off = 0x4, |
|
}; |
|
|
|
static const struct armada_thermal_data armada375_data = { |
|
.init = armada375_init, |
|
.is_valid_bit = BIT(10), |
|
.temp_shift = 0, |
|
.temp_mask = 0x1ff, |
|
.coef_b = 3171900000ULL, |
|
.coef_m = 10000000ULL, |
|
.coef_div = 13616, |
|
.syscon_status_off = 0x78, |
|
.syscon_control0_off = 0x7c, |
|
.syscon_control1_off = 0x80, |
|
}; |
|
|
|
static const struct armada_thermal_data armada380_data = { |
|
.init = armada380_init, |
|
.is_valid_bit = BIT(10), |
|
.temp_shift = 0, |
|
.temp_mask = 0x3ff, |
|
.coef_b = 1172499100ULL, |
|
.coef_m = 2000096ULL, |
|
.coef_div = 4201, |
|
.inverted = true, |
|
.syscon_control0_off = 0x70, |
|
.syscon_control1_off = 0x74, |
|
.syscon_status_off = 0x78, |
|
}; |
|
|
|
static const struct armada_thermal_data armada_ap806_data = { |
|
.init = armada_ap806_init, |
|
.is_valid_bit = BIT(16), |
|
.temp_shift = 0, |
|
.temp_mask = 0x3ff, |
|
.thresh_shift = 3, |
|
.hyst_shift = 19, |
|
.hyst_mask = 0x3, |
|
.coef_b = -150000LL, |
|
.coef_m = 423ULL, |
|
.coef_div = 1, |
|
.inverted = true, |
|
.signed_sample = true, |
|
.syscon_control0_off = 0x84, |
|
.syscon_control1_off = 0x88, |
|
.syscon_status_off = 0x8C, |
|
.dfx_irq_cause_off = 0x108, |
|
.dfx_irq_mask_off = 0x10C, |
|
.dfx_overheat_irq = BIT(22), |
|
.dfx_server_irq_mask_off = 0x104, |
|
.dfx_server_irq_en = BIT(1), |
|
.cpu_nr = 4, |
|
}; |
|
|
|
static const struct armada_thermal_data armada_cp110_data = { |
|
.init = armada_cp110_init, |
|
.is_valid_bit = BIT(10), |
|
.temp_shift = 0, |
|
.temp_mask = 0x3ff, |
|
.thresh_shift = 16, |
|
.hyst_shift = 26, |
|
.hyst_mask = 0x3, |
|
.coef_b = 1172499100ULL, |
|
.coef_m = 2000096ULL, |
|
.coef_div = 4201, |
|
.inverted = true, |
|
.syscon_control0_off = 0x70, |
|
.syscon_control1_off = 0x74, |
|
.syscon_status_off = 0x78, |
|
.dfx_irq_cause_off = 0x108, |
|
.dfx_irq_mask_off = 0x10C, |
|
.dfx_overheat_irq = BIT(20), |
|
.dfx_server_irq_mask_off = 0x104, |
|
.dfx_server_irq_en = BIT(1), |
|
}; |
|
|
|
static const struct of_device_id armada_thermal_id_table[] = { |
|
{ |
|
.compatible = "marvell,armadaxp-thermal", |
|
.data = &armadaxp_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada370-thermal", |
|
.data = &armada370_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada375-thermal", |
|
.data = &armada375_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada380-thermal", |
|
.data = &armada380_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada-ap806-thermal", |
|
.data = &armada_ap806_data, |
|
}, |
|
{ |
|
.compatible = "marvell,armada-cp110-thermal", |
|
.data = &armada_cp110_data, |
|
}, |
|
{ |
|
/* sentinel */ |
|
}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, armada_thermal_id_table); |
|
|
|
static const struct regmap_config armada_thermal_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.fast_io = true, |
|
}; |
|
|
|
static int armada_thermal_probe_legacy(struct platform_device *pdev, |
|
struct armada_thermal_priv *priv) |
|
{ |
|
struct armada_thermal_data *data = priv->data; |
|
struct resource *res; |
|
void __iomem *base; |
|
|
|
/* First memory region points towards the status register */ |
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
base = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(base)) |
|
return PTR_ERR(base); |
|
|
|
/* |
|
* Fix up from the old individual DT register specification to |
|
* cover all the registers. We do this by adjusting the ioremap() |
|
* result, which should be fine as ioremap() deals with pages. |
|
* However, validate that we do not cross a page boundary while |
|
* making this adjustment. |
|
*/ |
|
if (((unsigned long)base & ~PAGE_MASK) < data->syscon_status_off) |
|
return -EINVAL; |
|
base -= data->syscon_status_off; |
|
|
|
priv->syscon = devm_regmap_init_mmio(&pdev->dev, base, |
|
&armada_thermal_regmap_config); |
|
return PTR_ERR_OR_ZERO(priv->syscon); |
|
} |
|
|
|
static int armada_thermal_probe_syscon(struct platform_device *pdev, |
|
struct armada_thermal_priv *priv) |
|
{ |
|
priv->syscon = syscon_node_to_regmap(pdev->dev.parent->of_node); |
|
return PTR_ERR_OR_ZERO(priv->syscon); |
|
} |
|
|
|
static void armada_set_sane_name(struct platform_device *pdev, |
|
struct armada_thermal_priv *priv) |
|
{ |
|
const char *name = dev_name(&pdev->dev); |
|
char *insane_char; |
|
|
|
if (strlen(name) > THERMAL_NAME_LENGTH) { |
|
/* |
|
* When inside a system controller, the device name has the |
|
* form: f06f8000.system-controller:ap-thermal so stripping |
|
* after the ':' should give us a shorter but meaningful name. |
|
*/ |
|
name = strrchr(name, ':'); |
|
if (!name) |
|
name = "armada_thermal"; |
|
else |
|
name++; |
|
} |
|
|
|
/* Save the name locally */ |
|
strncpy(priv->zone_name, name, THERMAL_NAME_LENGTH - 1); |
|
priv->zone_name[THERMAL_NAME_LENGTH - 1] = '\0'; |
|
|
|
/* Then check there are no '-' or hwmon core will complain */ |
|
do { |
|
insane_char = strpbrk(priv->zone_name, "-"); |
|
if (insane_char) |
|
*insane_char = '_'; |
|
} while (insane_char); |
|
} |
|
|
|
/* |
|
* The IP can manage to trigger interrupts on overheat situation from all the |
|
* sensors. However, the interrupt source changes along with the last selected |
|
* source (ie. the last read sensor), which is an inconsistent behavior. Avoid |
|
* possible glitches by always selecting back only one channel (arbitrarily: the |
|
* first in the DT which has a critical trip point). We also disable sensor |
|
* switch during overheat situations. |
|
*/ |
|
static int armada_configure_overheat_int(struct armada_thermal_priv *priv, |
|
struct thermal_zone_device *tz, |
|
int sensor_id) |
|
{ |
|
/* Retrieve the critical trip point to enable the overheat interrupt */ |
|
const struct thermal_trip *trips = of_thermal_get_trip_points(tz); |
|
int ret; |
|
int i; |
|
|
|
if (!trips) |
|
return -EINVAL; |
|
|
|
for (i = 0; i < of_thermal_get_ntrips(tz); i++) |
|
if (trips[i].type == THERMAL_TRIP_CRITICAL) |
|
break; |
|
|
|
if (i == of_thermal_get_ntrips(tz)) |
|
return -EINVAL; |
|
|
|
ret = armada_select_channel(priv, sensor_id); |
|
if (ret) |
|
return ret; |
|
|
|
armada_set_overheat_thresholds(priv, |
|
trips[i].temperature, |
|
trips[i].hysteresis); |
|
priv->overheat_sensor = tz; |
|
priv->interrupt_source = sensor_id; |
|
|
|
armada_enable_overheat_interrupt(priv); |
|
|
|
return 0; |
|
} |
|
|
|
static int armada_thermal_probe(struct platform_device *pdev) |
|
{ |
|
struct thermal_zone_device *tz; |
|
struct armada_thermal_sensor *sensor; |
|
struct armada_drvdata *drvdata; |
|
const struct of_device_id *match; |
|
struct armada_thermal_priv *priv; |
|
int sensor_id, irq; |
|
int ret; |
|
|
|
match = of_match_device(armada_thermal_id_table, &pdev->dev); |
|
if (!match) |
|
return -ENODEV; |
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); |
|
if (!drvdata) |
|
return -ENOMEM; |
|
|
|
priv->dev = &pdev->dev; |
|
priv->data = (struct armada_thermal_data *)match->data; |
|
|
|
mutex_init(&priv->update_lock); |
|
|
|
/* |
|
* Legacy DT bindings only described "control1" register (also referred |
|
* as "control MSB" on old documentation). Then, bindings moved to cover |
|
* "control0/control LSB" and "control1/control MSB" registers within |
|
* the same resource, which was then of size 8 instead of 4. |
|
* |
|
* The logic of defining sporadic registers is broken. For instance, it |
|
* blocked the addition of the overheat interrupt feature that needed |
|
* another resource somewhere else in the same memory area. One solution |
|
* is to define an overall system controller and put the thermal node |
|
* into it, which requires the use of regmaps across all the driver. |
|
*/ |
|
if (IS_ERR(syscon_node_to_regmap(pdev->dev.parent->of_node))) { |
|
/* Ensure device name is correct for the thermal core */ |
|
armada_set_sane_name(pdev, priv); |
|
|
|
ret = armada_thermal_probe_legacy(pdev, priv); |
|
if (ret) |
|
return ret; |
|
|
|
priv->data->init(pdev, priv); |
|
|
|
/* Wait the sensors to be valid */ |
|
armada_wait_sensor_validity(priv); |
|
|
|
tz = thermal_zone_device_register(priv->zone_name, 0, 0, priv, |
|
&legacy_ops, NULL, 0, 0); |
|
if (IS_ERR(tz)) { |
|
dev_err(&pdev->dev, |
|
"Failed to register thermal zone device\n"); |
|
return PTR_ERR(tz); |
|
} |
|
|
|
ret = thermal_zone_device_enable(tz); |
|
if (ret) { |
|
thermal_zone_device_unregister(tz); |
|
return ret; |
|
} |
|
|
|
drvdata->type = LEGACY; |
|
drvdata->data.tz = tz; |
|
platform_set_drvdata(pdev, drvdata); |
|
|
|
return 0; |
|
} |
|
|
|
ret = armada_thermal_probe_syscon(pdev, priv); |
|
if (ret) |
|
return ret; |
|
|
|
priv->current_channel = -1; |
|
priv->data->init(pdev, priv); |
|
drvdata->type = SYSCON; |
|
drvdata->data.priv = priv; |
|
platform_set_drvdata(pdev, drvdata); |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq == -EPROBE_DEFER) |
|
return irq; |
|
|
|
/* The overheat interrupt feature is not mandatory */ |
|
if (irq > 0) { |
|
ret = devm_request_threaded_irq(&pdev->dev, irq, |
|
armada_overheat_isr, |
|
armada_overheat_isr_thread, |
|
0, NULL, priv); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Cannot request threaded IRQ %d\n", |
|
irq); |
|
return ret; |
|
} |
|
} |
|
|
|
/* |
|
* There is one channel for the IC and one per CPU (if any), each |
|
* channel has one sensor. |
|
*/ |
|
for (sensor_id = 0; sensor_id <= priv->data->cpu_nr; sensor_id++) { |
|
sensor = devm_kzalloc(&pdev->dev, |
|
sizeof(struct armada_thermal_sensor), |
|
GFP_KERNEL); |
|
if (!sensor) |
|
return -ENOMEM; |
|
|
|
/* Register the sensor */ |
|
sensor->priv = priv; |
|
sensor->id = sensor_id; |
|
tz = devm_thermal_zone_of_sensor_register(&pdev->dev, |
|
sensor->id, sensor, |
|
&of_ops); |
|
if (IS_ERR(tz)) { |
|
dev_info(&pdev->dev, "Thermal sensor %d unavailable\n", |
|
sensor_id); |
|
devm_kfree(&pdev->dev, sensor); |
|
continue; |
|
} |
|
|
|
/* |
|
* The first channel that has a critical trip point registered |
|
* in the DT will serve as interrupt source. Others possible |
|
* critical trip points will simply be ignored by the driver. |
|
*/ |
|
if (irq > 0 && !priv->overheat_sensor) |
|
armada_configure_overheat_int(priv, tz, sensor->id); |
|
} |
|
|
|
/* Just complain if no overheat interrupt was set up */ |
|
if (!priv->overheat_sensor) |
|
dev_warn(&pdev->dev, "Overheat interrupt not available\n"); |
|
|
|
return 0; |
|
} |
|
|
|
static int armada_thermal_exit(struct platform_device *pdev) |
|
{ |
|
struct armada_drvdata *drvdata = platform_get_drvdata(pdev); |
|
|
|
if (drvdata->type == LEGACY) |
|
thermal_zone_device_unregister(drvdata->data.tz); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver armada_thermal_driver = { |
|
.probe = armada_thermal_probe, |
|
.remove = armada_thermal_exit, |
|
.driver = { |
|
.name = "armada_thermal", |
|
.of_match_table = armada_thermal_id_table, |
|
}, |
|
}; |
|
|
|
module_platform_driver(armada_thermal_driver); |
|
|
|
MODULE_AUTHOR("Ezequiel Garcia <[email protected]>"); |
|
MODULE_DESCRIPTION("Marvell EBU Armada SoCs thermal driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|