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282 lines
8.8 KiB
282 lines
8.8 KiB
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* * Neither the name of Freescale Semiconductor nor the |
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* names of its contributors may be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation, either version 2 of that License or (at your option) any |
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* later version. |
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* |
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#include "dpaa_sys.h" |
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#include <soc/fsl/qman.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/iommu.h> |
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#if defined(CONFIG_FSL_PAMU) |
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#include <asm/fsl_pamu_stash.h> |
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#endif |
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struct qm_mcr_querywq { |
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u8 verb; |
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u8 result; |
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u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */ |
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u8 __reserved[28]; |
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u32 wq_len[8]; |
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} __packed; |
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static inline u16 qm_mcr_querywq_get_chan(const struct qm_mcr_querywq *wq) |
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{ |
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return wq->channel_wq >> 3; |
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} |
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struct __qm_mcr_querycongestion { |
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u32 state[8]; |
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}; |
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/* "Query Congestion Group State" */ |
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struct qm_mcr_querycongestion { |
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u8 verb; |
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u8 result; |
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u8 __reserved[30]; |
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/* Access this struct using qman_cgrs_get() */ |
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struct __qm_mcr_querycongestion state; |
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} __packed; |
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/* "Query CGR" */ |
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struct qm_mcr_querycgr { |
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u8 verb; |
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u8 result; |
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u16 __reserved1; |
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struct __qm_mc_cgr cgr; /* CGR fields */ |
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u8 __reserved2[6]; |
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u8 i_bcnt_hi; /* high 8-bits of 40-bit "Instant" */ |
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__be32 i_bcnt_lo; /* low 32-bits of 40-bit */ |
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u8 __reserved3[3]; |
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u8 a_bcnt_hi; /* high 8-bits of 40-bit "Average" */ |
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__be32 a_bcnt_lo; /* low 32-bits of 40-bit */ |
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__be32 cscn_targ_swp[4]; |
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} __packed; |
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static inline u64 qm_mcr_querycgr_i_get64(const struct qm_mcr_querycgr *q) |
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{ |
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return ((u64)q->i_bcnt_hi << 32) | be32_to_cpu(q->i_bcnt_lo); |
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} |
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static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q) |
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{ |
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return ((u64)q->a_bcnt_hi << 32) | be32_to_cpu(q->a_bcnt_lo); |
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} |
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/* Congestion Groups */ |
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/* |
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* This wrapper represents a bit-array for the state of the 256 QMan congestion |
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* groups. Is also used as a *mask* for congestion groups, eg. so we ignore |
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* those that don't concern us. We harness the structure and accessor details |
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* already used in the management command to query congestion groups. |
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*/ |
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#define CGR_BITS_PER_WORD 5 |
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#define CGR_WORD(x) ((x) >> CGR_BITS_PER_WORD) |
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#define CGR_BIT(x) (BIT(31) >> ((x) & 0x1f)) |
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#define CGR_NUM (sizeof(struct __qm_mcr_querycongestion) << 3) |
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struct qman_cgrs { |
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struct __qm_mcr_querycongestion q; |
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}; |
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static inline void qman_cgrs_init(struct qman_cgrs *c) |
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{ |
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memset(c, 0, sizeof(*c)); |
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} |
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static inline void qman_cgrs_fill(struct qman_cgrs *c) |
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{ |
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memset(c, 0xff, sizeof(*c)); |
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} |
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static inline int qman_cgrs_get(struct qman_cgrs *c, u8 cgr) |
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{ |
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return c->q.state[CGR_WORD(cgr)] & CGR_BIT(cgr); |
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} |
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static inline void qman_cgrs_cp(struct qman_cgrs *dest, |
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const struct qman_cgrs *src) |
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{ |
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*dest = *src; |
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} |
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static inline void qman_cgrs_and(struct qman_cgrs *dest, |
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const struct qman_cgrs *a, const struct qman_cgrs *b) |
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{ |
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int ret; |
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u32 *_d = dest->q.state; |
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const u32 *_a = a->q.state; |
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const u32 *_b = b->q.state; |
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for (ret = 0; ret < 8; ret++) |
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*_d++ = *_a++ & *_b++; |
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} |
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static inline void qman_cgrs_xor(struct qman_cgrs *dest, |
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const struct qman_cgrs *a, const struct qman_cgrs *b) |
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{ |
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int ret; |
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u32 *_d = dest->q.state; |
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const u32 *_a = a->q.state; |
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const u32 *_b = b->q.state; |
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for (ret = 0; ret < 8; ret++) |
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*_d++ = *_a++ ^ *_b++; |
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} |
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void qman_init_cgr_all(void); |
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struct qm_portal_config { |
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/* Portal addresses */ |
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void *addr_virt_ce; |
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void __iomem *addr_virt_ci; |
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struct device *dev; |
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struct iommu_domain *iommu_domain; |
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/* Allow these to be joined in lists */ |
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struct list_head list; |
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/* User-visible portal configuration settings */ |
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/* portal is affined to this cpu */ |
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int cpu; |
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/* portal interrupt line */ |
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int irq; |
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/* |
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* the portal's dedicated channel id, used initialising |
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* frame queues to target this portal when scheduled |
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*/ |
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u16 channel; |
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/* |
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* mask of pool channels this portal has dequeue access to |
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* (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask) |
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*/ |
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u32 pools; |
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}; |
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/* Revision info (for errata and feature handling) */ |
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#define QMAN_REV11 0x0101 |
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#define QMAN_REV12 0x0102 |
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#define QMAN_REV20 0x0200 |
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#define QMAN_REV30 0x0300 |
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#define QMAN_REV31 0x0301 |
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#define QMAN_REV32 0x0302 |
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extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */ |
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#define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */ |
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extern struct gen_pool *qm_fqalloc; /* FQID allocator */ |
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extern struct gen_pool *qm_qpalloc; /* pool-channel allocator */ |
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extern struct gen_pool *qm_cgralloc; /* CGR ID allocator */ |
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u32 qm_get_pools_sdqcr(void); |
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int qman_wq_alloc(void); |
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#ifdef CONFIG_FSL_PAMU |
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#define qman_liodn_fixup __qman_liodn_fixup |
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#else |
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static inline void qman_liodn_fixup(u16 channel) |
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{ |
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} |
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#endif |
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void __qman_liodn_fixup(u16 channel); |
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void qman_set_sdest(u16 channel, unsigned int cpu_idx); |
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struct qman_portal *qman_create_affine_portal( |
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const struct qm_portal_config *config, |
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const struct qman_cgrs *cgrs); |
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const struct qm_portal_config *qman_destroy_affine_portal(void); |
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/* |
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* qman_query_fq - Queries FQD fields (via h/w query command) |
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* @fq: the frame queue object to be queried |
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* @fqd: storage for the queried FQD fields |
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*/ |
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int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd); |
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int qman_alloc_fq_table(u32 num_fqids); |
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/* QMan s/w corenet portal, low-level i/face */ |
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/* |
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* For qm_dqrr_sdqcr_set(); Choose one SOURCE. Choose one COUNT. Choose one |
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* dequeue TYPE. Choose TOKEN (8-bit). |
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* If SOURCE == CHANNELS, |
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* Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n). |
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* You can choose DEDICATED_PRECEDENCE if the portal channel should have |
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* priority. |
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* If SOURCE == SPECIFICWQ, |
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* Either select the work-queue ID with SPECIFICWQ_WQ(), or select the |
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* channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the |
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* work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the |
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* same value. |
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*/ |
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#define QM_SDQCR_SOURCE_CHANNELS 0x0 |
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#define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000 |
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#define QM_SDQCR_COUNT_EXACT1 0x0 |
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#define QM_SDQCR_COUNT_UPTO3 0x20000000 |
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#define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000 |
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#define QM_SDQCR_TYPE_MASK 0x03000000 |
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#define QM_SDQCR_TYPE_NULL 0x0 |
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#define QM_SDQCR_TYPE_PRIO_QOS 0x01000000 |
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#define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000 |
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#define QM_SDQCR_TYPE_ACTIVE 0x03000000 |
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#define QM_SDQCR_TOKEN_MASK 0x00ff0000 |
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#define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16) |
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#define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff) |
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#define QM_SDQCR_CHANNELS_DEDICATED 0x00008000 |
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#define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7 |
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#define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000 |
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#define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4) |
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#define QM_SDQCR_SPECIFICWQ_WQ(n) (n) |
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/* For qm_dqrr_vdqcr_set(): use FQID(n) to fill in the frame queue ID */ |
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#define QM_VDQCR_FQID_MASK 0x00ffffff |
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#define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK) |
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/* |
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* Used by all portal interrupt registers except 'inhibit' |
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* Channels with frame availability |
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*/ |
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#define QM_PIRQ_DQAVAIL 0x0000ffff |
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/* The DQAVAIL interrupt fields break down into these bits; */ |
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#define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */ |
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#define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */ |
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#define QM_DQAVAIL_MASK 0xffff |
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/* This mask contains all the "irqsource" bits visible to API users */ |
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#define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI) |
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extern struct qman_portal *affine_portals[NR_CPUS]; |
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extern struct qman_portal *qman_dma_portal; |
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const struct qm_portal_config *qman_get_qm_portal_config( |
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struct qman_portal *portal); |
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unsigned int qm_get_fqid_maxcnt(void); |
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int qman_shutdown_fq(u32 fqid); |
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int qman_requires_cleanup(void); |
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void qman_done_cleanup(void); |
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void qman_enable_irqs(void);
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