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192 lines
2.9 KiB
192 lines
2.9 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2016 Broadcom Corporation |
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*/ |
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#include <asm/asm.h> |
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#include <asm/regdef.h> |
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#include <asm/mipsregs.h> |
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#include <asm/stackframe.h> |
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#include "pm.h" |
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.text |
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.set noreorder |
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.align 5 |
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/* |
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* a0: u32 params array |
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*/ |
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LEAF(brcm_pm_do_s2) |
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subu sp, 64 |
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sw ra, 0(sp) |
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sw s0, 4(sp) |
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sw s1, 8(sp) |
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sw s2, 12(sp) |
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sw s3, 16(sp) |
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sw s4, 20(sp) |
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sw s5, 24(sp) |
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sw s6, 28(sp) |
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sw s7, 32(sp) |
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/* |
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* Dereference the params array |
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* s0: AON_CTRL base register |
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* s1: DDR_PHY base register |
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* s2: TIMERS base register |
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* s3: I-Cache line size |
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* s4: Restart vector address |
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* s5: Restart vector size |
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*/ |
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move t0, a0 |
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lw s0, 0(t0) |
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lw s1, 4(t0) |
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lw s2, 8(t0) |
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lw s3, 12(t0) |
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lw s4, 16(t0) |
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lw s5, 20(t0) |
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/* Lock this asm section into the I-cache */ |
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addiu t1, s3, -1 |
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not t1 |
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la t0, brcm_pm_do_s2 |
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and t0, t1 |
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la t2, asm_end |
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and t2, t1 |
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1: cache 0x1c, 0(t0) |
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bne t0, t2, 1b |
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addu t0, s3 |
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/* Lock the interrupt vector into the I-cache */ |
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move t0, zero |
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2: move t1, s4 |
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cache 0x1c, 0(t1) |
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addu t1, s3 |
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addu t0, s3 |
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ble t0, s5, 2b |
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nop |
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sync |
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/* Power down request */ |
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li t0, PM_S2_COMMAND |
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sw zero, AON_CTRL_PM_CTRL(s0) |
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lw zero, AON_CTRL_PM_CTRL(s0) |
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sw t0, AON_CTRL_PM_CTRL(s0) |
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lw t0, AON_CTRL_PM_CTRL(s0) |
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/* Enable CP0 interrupt 2 and wait for interrupt */ |
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mfc0 t0, CP0_STATUS |
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/* Save cp0 sr for restoring later */ |
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move s6, t0 |
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li t1, ~(ST0_IM | ST0_IE) |
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and t0, t1 |
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ori t0, STATUSF_IP2 |
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mtc0 t0, CP0_STATUS |
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nop |
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nop |
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nop |
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ori t0, ST0_IE |
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mtc0 t0, CP0_STATUS |
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/* Wait for interrupt */ |
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wait |
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nop |
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/* Wait for memc0 */ |
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1: lw t0, DDR40_PHY_CONTROL_REGS_0_PLL_STATUS(s1) |
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andi t0, 1 |
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beqz t0, 1b |
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nop |
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/* 1ms delay needed for stable recovery */ |
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/* Use TIMER1 to count 1 ms */ |
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li t0, RESET_TIMER |
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sw t0, TIMER_TIMER1_CTRL(s2) |
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lw t0, TIMER_TIMER1_CTRL(s2) |
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li t0, START_TIMER |
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sw t0, TIMER_TIMER1_CTRL(s2) |
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lw t0, TIMER_TIMER1_CTRL(s2) |
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/* Prepare delay */ |
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li t0, TIMER_MASK |
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lw t1, TIMER_TIMER1_STAT(s2) |
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and t1, t0 |
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/* 1ms delay */ |
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addi t1, 27000 |
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/* Wait for the timer value to exceed t1 */ |
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1: lw t0, TIMER_TIMER1_STAT(s2) |
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sgtu t2, t1, t0 |
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bnez t2, 1b |
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nop |
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/* Power back up */ |
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li t1, 1 |
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sw t1, AON_CTRL_HOST_MISC_CMDS(s0) |
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lw t1, AON_CTRL_HOST_MISC_CMDS(s0) |
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sw zero, AON_CTRL_PM_CTRL(s0) |
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lw zero, AON_CTRL_PM_CTRL(s0) |
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/* Unlock I-cache */ |
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addiu t1, s3, -1 |
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not t1 |
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la t0, brcm_pm_do_s2 |
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and t0, t1 |
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la t2, asm_end |
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and t2, t1 |
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1: cache 0x00, 0(t0) |
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bne t0, t2, 1b |
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addu t0, s3 |
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/* Unlock interrupt vector */ |
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move t0, zero |
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2: move t1, s4 |
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cache 0x00, 0(t1) |
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addu t1, s3 |
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addu t0, s3 |
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ble t0, s5, 2b |
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nop |
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/* Restore cp0 sr */ |
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sync |
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nop |
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mtc0 s6, CP0_STATUS |
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nop |
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/* Set return value to success */ |
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li v0, 0 |
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/* Return to caller */ |
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lw s7, 32(sp) |
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lw s6, 28(sp) |
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lw s5, 24(sp) |
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lw s4, 20(sp) |
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lw s3, 16(sp) |
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lw s2, 12(sp) |
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lw s1, 8(sp) |
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lw s0, 4(sp) |
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lw ra, 0(sp) |
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addiu sp, 64 |
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jr ra |
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nop |
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END(brcm_pm_do_s2) |
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.globl asm_end |
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asm_end: |
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nop |
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