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832 lines
19 KiB
832 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ARM-specific support for Broadcom STB S2/S3/S5 power management |
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* |
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* S2: clock gate CPUs and as many peripherals as possible |
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* S3: power off all of the chip except the Always ON (AON) island; keep DDR is |
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* self-refresh |
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* S5: (a.k.a. S3 cold boot) much like S3, except DDR is powered down, so we |
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* treat this mode like a soft power-off, with wakeup allowed from AON |
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* |
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* Copyright © 2014-2017 Broadcom |
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*/ |
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#define pr_fmt(fmt) "brcmstb-pm: " fmt |
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#include <linux/bitops.h> |
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#include <linux/compiler.h> |
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#include <linux/delay.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/kconfig.h> |
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#include <linux/kernel.h> |
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#include <linux/memblock.h> |
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#include <linux/module.h> |
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#include <linux/notifier.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm.h> |
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#include <linux/printk.h> |
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#include <linux/proc_fs.h> |
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#include <linux/sizes.h> |
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#include <linux/slab.h> |
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#include <linux/sort.h> |
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#include <linux/suspend.h> |
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#include <linux/types.h> |
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#include <linux/uaccess.h> |
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#include <linux/soc/brcmstb/brcmstb.h> |
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#include <asm/fncpy.h> |
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#include <asm/setup.h> |
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#include <asm/suspend.h> |
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#include "pm.h" |
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#include "aon_defs.h" |
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#define SHIMPHY_DDR_PAD_CNTRL 0x8c |
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/* Method #0 */ |
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#define SHIMPHY_PAD_PLL_SEQUENCE BIT(8) |
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#define SHIMPHY_PAD_GATE_PLL_S3 BIT(9) |
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/* Method #1 */ |
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#define PWRDWN_SEQ_NO_SEQUENCING 0 |
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#define PWRDWN_SEQ_HOLD_CHANNEL 1 |
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#define PWRDWN_SEQ_RESET_PLL 2 |
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#define PWRDWN_SEQ_POWERDOWN_PLL 3 |
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#define SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK 0x00f00000 |
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#define SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT 20 |
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#define DDR_FORCE_CKE_RST_N BIT(3) |
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#define DDR_PHY_RST_N BIT(2) |
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#define DDR_PHY_CKE BIT(1) |
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#define DDR_PHY_NO_CHANNEL 0xffffffff |
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#define MAX_NUM_MEMC 3 |
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struct brcmstb_memc { |
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void __iomem *ddr_phy_base; |
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void __iomem *ddr_shimphy_base; |
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void __iomem *ddr_ctrl; |
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}; |
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struct brcmstb_pm_control { |
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void __iomem *aon_ctrl_base; |
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void __iomem *aon_sram; |
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struct brcmstb_memc memcs[MAX_NUM_MEMC]; |
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void __iomem *boot_sram; |
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size_t boot_sram_len; |
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bool support_warm_boot; |
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size_t pll_status_offset; |
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int num_memc; |
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struct brcmstb_s3_params *s3_params; |
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dma_addr_t s3_params_pa; |
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int s3entry_method; |
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u32 warm_boot_offset; |
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u32 phy_a_standby_ctrl_offs; |
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u32 phy_b_standby_ctrl_offs; |
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bool needs_ddr_pad; |
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struct platform_device *pdev; |
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}; |
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enum bsp_initiate_command { |
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BSP_CLOCK_STOP = 0x00, |
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BSP_GEN_RANDOM_KEY = 0x4A, |
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BSP_RESTORE_RANDOM_KEY = 0x55, |
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BSP_GEN_FIXED_KEY = 0x63, |
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}; |
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#define PM_INITIATE 0x01 |
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#define PM_INITIATE_SUCCESS 0x00 |
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#define PM_INITIATE_FAIL 0xfe |
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static struct brcmstb_pm_control ctrl; |
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noinline int brcmstb_pm_s3_finish(void); |
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static int (*brcmstb_pm_do_s2_sram)(void __iomem *aon_ctrl_base, |
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void __iomem *ddr_phy_pll_status); |
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static int brcmstb_init_sram(struct device_node *dn) |
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{ |
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void __iomem *sram; |
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struct resource res; |
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int ret; |
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ret = of_address_to_resource(dn, 0, &res); |
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if (ret) |
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return ret; |
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/* Uncached, executable remapping of SRAM */ |
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sram = __arm_ioremap_exec(res.start, resource_size(&res), false); |
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if (!sram) |
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return -ENOMEM; |
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ctrl.boot_sram = sram; |
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ctrl.boot_sram_len = resource_size(&res); |
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return 0; |
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} |
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static const struct of_device_id sram_dt_ids[] = { |
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{ .compatible = "mmio-sram" }, |
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{ /* sentinel */ } |
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}; |
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static int do_bsp_initiate_command(enum bsp_initiate_command cmd) |
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{ |
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void __iomem *base = ctrl.aon_ctrl_base; |
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int ret; |
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int timeo = 1000 * 1000; /* 1 second */ |
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writel_relaxed(0, base + AON_CTRL_PM_INITIATE); |
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(void)readl_relaxed(base + AON_CTRL_PM_INITIATE); |
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/* Go! */ |
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writel_relaxed((cmd << 1) | PM_INITIATE, base + AON_CTRL_PM_INITIATE); |
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/* |
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* If firmware doesn't support the 'ack', then just assume it's done |
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* after 10ms. Note that this only works for command 0, BSP_CLOCK_STOP |
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*/ |
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if (of_machine_is_compatible("brcm,bcm74371a0")) { |
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(void)readl_relaxed(base + AON_CTRL_PM_INITIATE); |
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mdelay(10); |
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return 0; |
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} |
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for (;;) { |
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ret = readl_relaxed(base + AON_CTRL_PM_INITIATE); |
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if (!(ret & PM_INITIATE)) |
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break; |
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if (timeo <= 0) { |
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pr_err("error: timeout waiting for BSP (%x)\n", ret); |
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break; |
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} |
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timeo -= 50; |
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udelay(50); |
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} |
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return (ret & 0xff) != PM_INITIATE_SUCCESS; |
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} |
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static int brcmstb_pm_handshake(void) |
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{ |
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void __iomem *base = ctrl.aon_ctrl_base; |
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u32 tmp; |
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int ret; |
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/* BSP power handshake, v1 */ |
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tmp = readl_relaxed(base + AON_CTRL_HOST_MISC_CMDS); |
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tmp &= ~1UL; |
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writel_relaxed(tmp, base + AON_CTRL_HOST_MISC_CMDS); |
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(void)readl_relaxed(base + AON_CTRL_HOST_MISC_CMDS); |
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ret = do_bsp_initiate_command(BSP_CLOCK_STOP); |
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if (ret) |
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pr_err("BSP handshake failed\n"); |
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/* |
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* HACK: BSP may have internal race on the CLOCK_STOP command. |
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* Avoid touching the BSP for a few milliseconds. |
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*/ |
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mdelay(3); |
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return ret; |
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} |
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static inline void shimphy_set(u32 value, u32 mask) |
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{ |
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int i; |
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if (!ctrl.needs_ddr_pad) |
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return; |
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for (i = 0; i < ctrl.num_memc; i++) { |
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u32 tmp; |
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tmp = readl_relaxed(ctrl.memcs[i].ddr_shimphy_base + |
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SHIMPHY_DDR_PAD_CNTRL); |
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tmp = value | (tmp & mask); |
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writel_relaxed(tmp, ctrl.memcs[i].ddr_shimphy_base + |
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SHIMPHY_DDR_PAD_CNTRL); |
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} |
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wmb(); /* Complete sequence in order. */ |
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} |
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static inline void ddr_ctrl_set(bool warmboot) |
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{ |
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int i; |
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for (i = 0; i < ctrl.num_memc; i++) { |
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u32 tmp; |
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tmp = readl_relaxed(ctrl.memcs[i].ddr_ctrl + |
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ctrl.warm_boot_offset); |
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if (warmboot) |
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tmp |= 1; |
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else |
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tmp &= ~1; /* Cold boot */ |
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writel_relaxed(tmp, ctrl.memcs[i].ddr_ctrl + |
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ctrl.warm_boot_offset); |
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} |
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/* Complete sequence in order */ |
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wmb(); |
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} |
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static inline void s3entry_method0(void) |
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{ |
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shimphy_set(SHIMPHY_PAD_GATE_PLL_S3 | SHIMPHY_PAD_PLL_SEQUENCE, |
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0xffffffff); |
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} |
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static inline void s3entry_method1(void) |
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{ |
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/* |
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* S3 Entry Sequence |
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* ----------------- |
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* Step 1: SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL [ S3_PWRDWN_SEQ ] = 3 |
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* Step 2: MEMC_DDR_0_WARM_BOOT [ WARM_BOOT ] = 1 |
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*/ |
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shimphy_set((PWRDWN_SEQ_POWERDOWN_PLL << |
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SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT), |
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~SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK); |
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ddr_ctrl_set(true); |
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} |
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static inline void s5entry_method1(void) |
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{ |
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int i; |
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/* |
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* S5 Entry Sequence |
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* ----------------- |
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* Step 1: SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL [ S3_PWRDWN_SEQ ] = 3 |
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* Step 2: MEMC_DDR_0_WARM_BOOT [ WARM_BOOT ] = 0 |
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* Step 3: DDR_PHY_CONTROL_REGS_[AB]_0_STANDBY_CONTROL[ CKE ] = 0 |
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* DDR_PHY_CONTROL_REGS_[AB]_0_STANDBY_CONTROL[ RST_N ] = 0 |
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*/ |
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shimphy_set((PWRDWN_SEQ_POWERDOWN_PLL << |
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SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT), |
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~SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK); |
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ddr_ctrl_set(false); |
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for (i = 0; i < ctrl.num_memc; i++) { |
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u32 tmp; |
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/* Step 3: Channel A (RST_N = CKE = 0) */ |
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tmp = readl_relaxed(ctrl.memcs[i].ddr_phy_base + |
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ctrl.phy_a_standby_ctrl_offs); |
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tmp &= ~(DDR_PHY_RST_N | DDR_PHY_RST_N); |
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writel_relaxed(tmp, ctrl.memcs[i].ddr_phy_base + |
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ctrl.phy_a_standby_ctrl_offs); |
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/* Step 3: Channel B? */ |
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if (ctrl.phy_b_standby_ctrl_offs != DDR_PHY_NO_CHANNEL) { |
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tmp = readl_relaxed(ctrl.memcs[i].ddr_phy_base + |
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ctrl.phy_b_standby_ctrl_offs); |
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tmp &= ~(DDR_PHY_RST_N | DDR_PHY_RST_N); |
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writel_relaxed(tmp, ctrl.memcs[i].ddr_phy_base + |
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ctrl.phy_b_standby_ctrl_offs); |
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} |
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} |
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/* Must complete */ |
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wmb(); |
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} |
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/* |
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* Run a Power Management State Machine (PMSM) shutdown command and put the CPU |
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* into a low-power mode |
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*/ |
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static void brcmstb_do_pmsm_power_down(unsigned long base_cmd, bool onewrite) |
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{ |
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void __iomem *base = ctrl.aon_ctrl_base; |
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if ((ctrl.s3entry_method == 1) && (base_cmd == PM_COLD_CONFIG)) |
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s5entry_method1(); |
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/* pm_start_pwrdn transition 0->1 */ |
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writel_relaxed(base_cmd, base + AON_CTRL_PM_CTRL); |
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if (!onewrite) { |
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(void)readl_relaxed(base + AON_CTRL_PM_CTRL); |
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writel_relaxed(base_cmd | PM_PWR_DOWN, base + AON_CTRL_PM_CTRL); |
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(void)readl_relaxed(base + AON_CTRL_PM_CTRL); |
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} |
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wfi(); |
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} |
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/* Support S5 cold boot out of "poweroff" */ |
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static void brcmstb_pm_poweroff(void) |
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{ |
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brcmstb_pm_handshake(); |
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/* Clear magic S3 warm-boot value */ |
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writel_relaxed(0, ctrl.aon_sram + AON_REG_MAGIC_FLAGS); |
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(void)readl_relaxed(ctrl.aon_sram + AON_REG_MAGIC_FLAGS); |
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/* Skip wait-for-interrupt signal; just use a countdown */ |
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writel_relaxed(0x10, ctrl.aon_ctrl_base + AON_CTRL_PM_CPU_WAIT_COUNT); |
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(void)readl_relaxed(ctrl.aon_ctrl_base + AON_CTRL_PM_CPU_WAIT_COUNT); |
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if (ctrl.s3entry_method == 1) { |
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shimphy_set((PWRDWN_SEQ_POWERDOWN_PLL << |
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SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT), |
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~SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK); |
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ddr_ctrl_set(false); |
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brcmstb_do_pmsm_power_down(M1_PM_COLD_CONFIG, true); |
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return; /* We should never actually get here */ |
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} |
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brcmstb_do_pmsm_power_down(PM_COLD_CONFIG, false); |
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} |
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static void *brcmstb_pm_copy_to_sram(void *fn, size_t len) |
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{ |
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unsigned int size = ALIGN(len, FNCPY_ALIGN); |
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if (ctrl.boot_sram_len < size) { |
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pr_err("standby code will not fit in SRAM\n"); |
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return NULL; |
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} |
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return fncpy(ctrl.boot_sram, fn, size); |
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} |
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/* |
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* S2 suspend/resume picks up where we left off, so we must execute carefully |
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* from SRAM, in order to allow DDR to come back up safely before we continue. |
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*/ |
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static int brcmstb_pm_s2(void) |
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{ |
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/* A previous S3 can set a value hazardous to S2, so make sure. */ |
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if (ctrl.s3entry_method == 1) { |
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shimphy_set((PWRDWN_SEQ_NO_SEQUENCING << |
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SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT), |
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~SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK); |
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ddr_ctrl_set(false); |
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} |
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brcmstb_pm_do_s2_sram = brcmstb_pm_copy_to_sram(&brcmstb_pm_do_s2, |
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brcmstb_pm_do_s2_sz); |
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if (!brcmstb_pm_do_s2_sram) |
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return -EINVAL; |
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return brcmstb_pm_do_s2_sram(ctrl.aon_ctrl_base, |
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ctrl.memcs[0].ddr_phy_base + |
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ctrl.pll_status_offset); |
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} |
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/* |
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* This function is called on a new stack, so don't allow inlining (which will |
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* generate stack references on the old stack). It cannot be made static because |
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* it is referenced from brcmstb_pm_s3() |
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*/ |
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noinline int brcmstb_pm_s3_finish(void) |
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{ |
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struct brcmstb_s3_params *params = ctrl.s3_params; |
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dma_addr_t params_pa = ctrl.s3_params_pa; |
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phys_addr_t reentry = virt_to_phys(&cpu_resume_arm); |
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enum bsp_initiate_command cmd; |
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u32 flags; |
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/* |
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* Clear parameter structure, but not DTU area, which has already been |
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* filled in. We know DTU is a the end, so we can just subtract its |
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* size. |
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*/ |
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memset(params, 0, sizeof(*params) - sizeof(params->dtu)); |
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flags = readl_relaxed(ctrl.aon_sram + AON_REG_MAGIC_FLAGS); |
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flags &= S3_BOOTLOADER_RESERVED; |
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flags |= S3_FLAG_NO_MEM_VERIFY; |
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flags |= S3_FLAG_LOAD_RANDKEY; |
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/* Load random / fixed key */ |
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if (flags & S3_FLAG_LOAD_RANDKEY) |
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cmd = BSP_GEN_RANDOM_KEY; |
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else |
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cmd = BSP_GEN_FIXED_KEY; |
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if (do_bsp_initiate_command(cmd)) { |
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pr_info("key loading failed\n"); |
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return -EIO; |
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} |
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params->magic = BRCMSTB_S3_MAGIC; |
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params->reentry = reentry; |
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/* No more writes to DRAM */ |
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flush_cache_all(); |
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flags |= BRCMSTB_S3_MAGIC_SHORT; |
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writel_relaxed(flags, ctrl.aon_sram + AON_REG_MAGIC_FLAGS); |
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writel_relaxed(lower_32_bits(params_pa), |
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ctrl.aon_sram + AON_REG_CONTROL_LOW); |
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writel_relaxed(upper_32_bits(params_pa), |
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ctrl.aon_sram + AON_REG_CONTROL_HIGH); |
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switch (ctrl.s3entry_method) { |
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case 0: |
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s3entry_method0(); |
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brcmstb_do_pmsm_power_down(PM_WARM_CONFIG, false); |
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break; |
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case 1: |
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s3entry_method1(); |
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brcmstb_do_pmsm_power_down(M1_PM_WARM_CONFIG, true); |
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break; |
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default: |
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return -EINVAL; |
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} |
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/* Must have been interrupted from wfi()? */ |
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return -EINTR; |
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} |
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static int brcmstb_pm_do_s3(unsigned long sp) |
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{ |
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unsigned long save_sp; |
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int ret; |
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asm volatile ( |
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"mov %[save], sp\n" |
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"mov sp, %[new]\n" |
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"bl brcmstb_pm_s3_finish\n" |
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"mov %[ret], r0\n" |
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"mov %[new], sp\n" |
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"mov sp, %[save]\n" |
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: [save] "=&r" (save_sp), [ret] "=&r" (ret) |
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: [new] "r" (sp) |
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); |
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return ret; |
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} |
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static int brcmstb_pm_s3(void) |
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{ |
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void __iomem *sp = ctrl.boot_sram + ctrl.boot_sram_len; |
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return cpu_suspend((unsigned long)sp, brcmstb_pm_do_s3); |
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} |
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static int brcmstb_pm_standby(bool deep_standby) |
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{ |
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int ret; |
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if (brcmstb_pm_handshake()) |
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return -EIO; |
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if (deep_standby) |
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ret = brcmstb_pm_s3(); |
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else |
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ret = brcmstb_pm_s2(); |
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if (ret) |
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pr_err("%s: standby failed\n", __func__); |
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return ret; |
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} |
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static int brcmstb_pm_enter(suspend_state_t state) |
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{ |
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int ret = -EINVAL; |
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switch (state) { |
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case PM_SUSPEND_STANDBY: |
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ret = brcmstb_pm_standby(false); |
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break; |
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case PM_SUSPEND_MEM: |
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ret = brcmstb_pm_standby(true); |
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break; |
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} |
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return ret; |
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} |
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static int brcmstb_pm_valid(suspend_state_t state) |
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{ |
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switch (state) { |
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case PM_SUSPEND_STANDBY: |
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return true; |
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case PM_SUSPEND_MEM: |
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return ctrl.support_warm_boot; |
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default: |
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return false; |
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} |
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} |
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static const struct platform_suspend_ops brcmstb_pm_ops = { |
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.enter = brcmstb_pm_enter, |
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.valid = brcmstb_pm_valid, |
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}; |
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static const struct of_device_id aon_ctrl_dt_ids[] = { |
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{ .compatible = "brcm,brcmstb-aon-ctrl" }, |
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{} |
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}; |
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struct ddr_phy_ofdata { |
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bool supports_warm_boot; |
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size_t pll_status_offset; |
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int s3entry_method; |
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u32 warm_boot_offset; |
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u32 phy_a_standby_ctrl_offs; |
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u32 phy_b_standby_ctrl_offs; |
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}; |
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|
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static struct ddr_phy_ofdata ddr_phy_71_1 = { |
|
.supports_warm_boot = true, |
|
.pll_status_offset = 0x0c, |
|
.s3entry_method = 1, |
|
.warm_boot_offset = 0x2c, |
|
.phy_a_standby_ctrl_offs = 0x198, |
|
.phy_b_standby_ctrl_offs = DDR_PHY_NO_CHANNEL |
|
}; |
|
|
|
static struct ddr_phy_ofdata ddr_phy_72_0 = { |
|
.supports_warm_boot = true, |
|
.pll_status_offset = 0x10, |
|
.s3entry_method = 1, |
|
.warm_boot_offset = 0x40, |
|
.phy_a_standby_ctrl_offs = 0x2a4, |
|
.phy_b_standby_ctrl_offs = 0x8a4 |
|
}; |
|
|
|
static struct ddr_phy_ofdata ddr_phy_225_1 = { |
|
.supports_warm_boot = false, |
|
.pll_status_offset = 0x4, |
|
.s3entry_method = 0 |
|
}; |
|
|
|
static struct ddr_phy_ofdata ddr_phy_240_1 = { |
|
.supports_warm_boot = true, |
|
.pll_status_offset = 0x4, |
|
.s3entry_method = 0 |
|
}; |
|
|
|
static const struct of_device_id ddr_phy_dt_ids[] = { |
|
{ |
|
.compatible = "brcm,brcmstb-ddr-phy-v71.1", |
|
.data = &ddr_phy_71_1, |
|
}, |
|
{ |
|
.compatible = "brcm,brcmstb-ddr-phy-v72.0", |
|
.data = &ddr_phy_72_0, |
|
}, |
|
{ |
|
.compatible = "brcm,brcmstb-ddr-phy-v225.1", |
|
.data = &ddr_phy_225_1, |
|
}, |
|
{ |
|
.compatible = "brcm,brcmstb-ddr-phy-v240.1", |
|
.data = &ddr_phy_240_1, |
|
}, |
|
{ |
|
/* Same as v240.1, for the registers we care about */ |
|
.compatible = "brcm,brcmstb-ddr-phy-v240.2", |
|
.data = &ddr_phy_240_1, |
|
}, |
|
{} |
|
}; |
|
|
|
struct ddr_seq_ofdata { |
|
bool needs_ddr_pad; |
|
u32 warm_boot_offset; |
|
}; |
|
|
|
static const struct ddr_seq_ofdata ddr_seq_b22 = { |
|
.needs_ddr_pad = false, |
|
.warm_boot_offset = 0x2c, |
|
}; |
|
|
|
static const struct ddr_seq_ofdata ddr_seq = { |
|
.needs_ddr_pad = true, |
|
}; |
|
|
|
static const struct of_device_id ddr_shimphy_dt_ids[] = { |
|
{ .compatible = "brcm,brcmstb-ddr-shimphy-v1.0" }, |
|
{} |
|
}; |
|
|
|
static const struct of_device_id brcmstb_memc_of_match[] = { |
|
{ |
|
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1", |
|
.data = &ddr_seq, |
|
}, |
|
{ |
|
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", |
|
.data = &ddr_seq_b22, |
|
}, |
|
{ |
|
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3", |
|
.data = &ddr_seq_b22, |
|
}, |
|
{ |
|
.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", |
|
.data = &ddr_seq_b22, |
|
}, |
|
{ |
|
.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1", |
|
.data = &ddr_seq_b22, |
|
}, |
|
{ |
|
.compatible = "brcm,brcmstb-memc-ddr", |
|
.data = &ddr_seq, |
|
}, |
|
{}, |
|
}; |
|
|
|
static void __iomem *brcmstb_ioremap_match(const struct of_device_id *matches, |
|
int index, const void **ofdata) |
|
{ |
|
struct device_node *dn; |
|
const struct of_device_id *match; |
|
|
|
dn = of_find_matching_node_and_match(NULL, matches, &match); |
|
if (!dn) |
|
return ERR_PTR(-EINVAL); |
|
|
|
if (ofdata) |
|
*ofdata = match->data; |
|
|
|
return of_io_request_and_map(dn, index, dn->full_name); |
|
} |
|
|
|
static int brcmstb_pm_panic_notify(struct notifier_block *nb, |
|
unsigned long action, void *data) |
|
{ |
|
writel_relaxed(BRCMSTB_PANIC_MAGIC, ctrl.aon_sram + AON_REG_PANIC); |
|
|
|
return NOTIFY_DONE; |
|
} |
|
|
|
static struct notifier_block brcmstb_pm_panic_nb = { |
|
.notifier_call = brcmstb_pm_panic_notify, |
|
}; |
|
|
|
static int brcmstb_pm_probe(struct platform_device *pdev) |
|
{ |
|
const struct ddr_phy_ofdata *ddr_phy_data; |
|
const struct ddr_seq_ofdata *ddr_seq_data; |
|
const struct of_device_id *of_id = NULL; |
|
struct device_node *dn; |
|
void __iomem *base; |
|
int ret, i; |
|
|
|
/* AON ctrl registers */ |
|
base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL); |
|
if (IS_ERR(base)) { |
|
pr_err("error mapping AON_CTRL\n"); |
|
return PTR_ERR(base); |
|
} |
|
ctrl.aon_ctrl_base = base; |
|
|
|
/* AON SRAM registers */ |
|
base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 1, NULL); |
|
if (IS_ERR(base)) { |
|
/* Assume standard offset */ |
|
ctrl.aon_sram = ctrl.aon_ctrl_base + |
|
AON_CTRL_SYSTEM_DATA_RAM_OFS; |
|
} else { |
|
ctrl.aon_sram = base; |
|
} |
|
|
|
writel_relaxed(0, ctrl.aon_sram + AON_REG_PANIC); |
|
|
|
/* DDR PHY registers */ |
|
base = brcmstb_ioremap_match(ddr_phy_dt_ids, 0, |
|
(const void **)&ddr_phy_data); |
|
if (IS_ERR(base)) { |
|
pr_err("error mapping DDR PHY\n"); |
|
return PTR_ERR(base); |
|
} |
|
ctrl.support_warm_boot = ddr_phy_data->supports_warm_boot; |
|
ctrl.pll_status_offset = ddr_phy_data->pll_status_offset; |
|
/* Only need DDR PHY 0 for now? */ |
|
ctrl.memcs[0].ddr_phy_base = base; |
|
ctrl.s3entry_method = ddr_phy_data->s3entry_method; |
|
ctrl.phy_a_standby_ctrl_offs = ddr_phy_data->phy_a_standby_ctrl_offs; |
|
ctrl.phy_b_standby_ctrl_offs = ddr_phy_data->phy_b_standby_ctrl_offs; |
|
/* |
|
* Slightly grosss to use the phy ver to get a memc, |
|
* offset but that is the only versioned things so far |
|
* we can test for. |
|
*/ |
|
ctrl.warm_boot_offset = ddr_phy_data->warm_boot_offset; |
|
|
|
/* DDR SHIM-PHY registers */ |
|
for_each_matching_node(dn, ddr_shimphy_dt_ids) { |
|
i = ctrl.num_memc; |
|
if (i >= MAX_NUM_MEMC) { |
|
pr_warn("too many MEMCs (max %d)\n", MAX_NUM_MEMC); |
|
break; |
|
} |
|
|
|
base = of_io_request_and_map(dn, 0, dn->full_name); |
|
if (IS_ERR(base)) { |
|
if (!ctrl.support_warm_boot) |
|
break; |
|
|
|
pr_err("error mapping DDR SHIMPHY %d\n", i); |
|
return PTR_ERR(base); |
|
} |
|
ctrl.memcs[i].ddr_shimphy_base = base; |
|
ctrl.num_memc++; |
|
} |
|
|
|
/* Sequencer DRAM Param and Control Registers */ |
|
i = 0; |
|
for_each_matching_node(dn, brcmstb_memc_of_match) { |
|
base = of_iomap(dn, 0); |
|
if (!base) { |
|
pr_err("error mapping DDR Sequencer %d\n", i); |
|
return -ENOMEM; |
|
} |
|
|
|
of_id = of_match_node(brcmstb_memc_of_match, dn); |
|
if (!of_id) { |
|
iounmap(base); |
|
return -EINVAL; |
|
} |
|
|
|
ddr_seq_data = of_id->data; |
|
ctrl.needs_ddr_pad = ddr_seq_data->needs_ddr_pad; |
|
/* Adjust warm boot offset based on the DDR sequencer */ |
|
if (ddr_seq_data->warm_boot_offset) |
|
ctrl.warm_boot_offset = ddr_seq_data->warm_boot_offset; |
|
|
|
ctrl.memcs[i].ddr_ctrl = base; |
|
i++; |
|
} |
|
|
|
pr_debug("PM: supports warm boot:%d, method:%d, wboffs:%x\n", |
|
ctrl.support_warm_boot, ctrl.s3entry_method, |
|
ctrl.warm_boot_offset); |
|
|
|
dn = of_find_matching_node(NULL, sram_dt_ids); |
|
if (!dn) { |
|
pr_err("SRAM not found\n"); |
|
return -EINVAL; |
|
} |
|
|
|
ret = brcmstb_init_sram(dn); |
|
if (ret) { |
|
pr_err("error setting up SRAM for PM\n"); |
|
return ret; |
|
} |
|
|
|
ctrl.pdev = pdev; |
|
|
|
ctrl.s3_params = kmalloc(sizeof(*ctrl.s3_params), GFP_KERNEL); |
|
if (!ctrl.s3_params) |
|
return -ENOMEM; |
|
ctrl.s3_params_pa = dma_map_single(&pdev->dev, ctrl.s3_params, |
|
sizeof(*ctrl.s3_params), |
|
DMA_TO_DEVICE); |
|
if (dma_mapping_error(&pdev->dev, ctrl.s3_params_pa)) { |
|
pr_err("error mapping DMA memory\n"); |
|
ret = -ENOMEM; |
|
goto out; |
|
} |
|
|
|
atomic_notifier_chain_register(&panic_notifier_list, |
|
&brcmstb_pm_panic_nb); |
|
|
|
pm_power_off = brcmstb_pm_poweroff; |
|
suspend_set_ops(&brcmstb_pm_ops); |
|
|
|
return 0; |
|
|
|
out: |
|
kfree(ctrl.s3_params); |
|
|
|
pr_warn("PM: initialization failed with code %d\n", ret); |
|
|
|
return ret; |
|
} |
|
|
|
static struct platform_driver brcmstb_pm_driver = { |
|
.driver = { |
|
.name = "brcmstb-pm", |
|
.of_match_table = aon_ctrl_dt_ids, |
|
}, |
|
}; |
|
|
|
static int __init brcmstb_pm_init(void) |
|
{ |
|
return platform_driver_probe(&brcmstb_pm_driver, |
|
brcmstb_pm_probe); |
|
} |
|
module_init(brcmstb_pm_init);
|
|
|