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275 lines
6.7 KiB
275 lines
6.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* STM32 Low-Power Timer PWM driver |
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* |
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* Copyright (C) STMicroelectronics 2017 |
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* |
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* Author: Gerald Baeza <[email protected]> |
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* |
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* Inspired by Gerald Baeza's pwm-stm32 driver |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/mfd/stm32-lptimer.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/platform_device.h> |
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#include <linux/pwm.h> |
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struct stm32_pwm_lp { |
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struct pwm_chip chip; |
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struct clk *clk; |
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struct regmap *regmap; |
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}; |
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static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip) |
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{ |
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return container_of(chip, struct stm32_pwm_lp, chip); |
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} |
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/* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */ |
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#define STM32_LPTIM_MAX_PRESCALER 128 |
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static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
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const struct pwm_state *state) |
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{ |
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struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); |
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unsigned long long prd, div, dty; |
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struct pwm_state cstate; |
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u32 val, mask, cfgr, presc = 0; |
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bool reenable; |
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int ret; |
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pwm_get_state(pwm, &cstate); |
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reenable = !cstate.enabled; |
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if (!state->enabled) { |
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if (cstate.enabled) { |
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/* Disable LP timer */ |
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ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); |
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if (ret) |
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return ret; |
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/* disable clock to PWM counter */ |
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clk_disable(priv->clk); |
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} |
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return 0; |
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} |
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/* Calculate the period and prescaler value */ |
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div = (unsigned long long)clk_get_rate(priv->clk) * state->period; |
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do_div(div, NSEC_PER_SEC); |
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if (!div) { |
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/* Clock is too slow to achieve requested period. */ |
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dev_dbg(priv->chip.dev, "Can't reach %llu ns\n", state->period); |
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return -EINVAL; |
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} |
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prd = div; |
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while (div > STM32_LPTIM_MAX_ARR) { |
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presc++; |
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if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) { |
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dev_err(priv->chip.dev, "max prescaler exceeded\n"); |
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return -EINVAL; |
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} |
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div = prd >> presc; |
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} |
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prd = div; |
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/* Calculate the duty cycle */ |
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dty = prd * state->duty_cycle; |
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do_div(dty, state->period); |
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if (!cstate.enabled) { |
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/* enable clock to drive PWM counter */ |
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ret = clk_enable(priv->clk); |
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if (ret) |
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return ret; |
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} |
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ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); |
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if (ret) |
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goto err; |
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if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || |
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(FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) { |
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val = FIELD_PREP(STM32_LPTIM_PRESC, presc); |
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val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); |
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mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL; |
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/* Must disable LP timer to modify CFGR */ |
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reenable = true; |
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ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); |
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if (ret) |
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goto err; |
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ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, |
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val); |
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if (ret) |
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goto err; |
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} |
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if (reenable) { |
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/* Must (re)enable LP timer to modify CMP & ARR */ |
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ret = regmap_write(priv->regmap, STM32_LPTIM_CR, |
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STM32_LPTIM_ENABLE); |
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if (ret) |
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goto err; |
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} |
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ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1); |
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if (ret) |
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goto err; |
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ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty)); |
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if (ret) |
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goto err; |
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/* ensure CMP & ARR registers are properly written */ |
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ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, |
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(val & STM32_LPTIM_CMPOK_ARROK), |
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100, 1000); |
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if (ret) { |
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dev_err(priv->chip.dev, "ARR/CMP registers write issue\n"); |
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goto err; |
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} |
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ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, |
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STM32_LPTIM_CMPOKCF_ARROKCF); |
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if (ret) |
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goto err; |
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if (reenable) { |
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/* Start LP timer in continuous mode */ |
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ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR, |
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STM32_LPTIM_CNTSTRT, |
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STM32_LPTIM_CNTSTRT); |
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if (ret) { |
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regmap_write(priv->regmap, STM32_LPTIM_CR, 0); |
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goto err; |
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} |
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} |
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return 0; |
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err: |
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if (!cstate.enabled) |
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clk_disable(priv->clk); |
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return ret; |
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} |
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static void stm32_pwm_lp_get_state(struct pwm_chip *chip, |
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struct pwm_device *pwm, |
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struct pwm_state *state) |
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{ |
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struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); |
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unsigned long rate = clk_get_rate(priv->clk); |
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u32 val, presc, prd; |
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u64 tmp; |
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regmap_read(priv->regmap, STM32_LPTIM_CR, &val); |
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state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val); |
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/* Keep PWM counter clock refcount in sync with PWM initial state */ |
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if (state->enabled) |
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clk_enable(priv->clk); |
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regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val); |
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presc = FIELD_GET(STM32_LPTIM_PRESC, val); |
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state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val); |
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regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd); |
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tmp = prd + 1; |
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tmp = (tmp << presc) * NSEC_PER_SEC; |
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state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); |
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regmap_read(priv->regmap, STM32_LPTIM_CMP, &val); |
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tmp = prd - val; |
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tmp = (tmp << presc) * NSEC_PER_SEC; |
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); |
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} |
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static const struct pwm_ops stm32_pwm_lp_ops = { |
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.owner = THIS_MODULE, |
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.apply = stm32_pwm_lp_apply, |
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.get_state = stm32_pwm_lp_get_state, |
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}; |
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static int stm32_pwm_lp_probe(struct platform_device *pdev) |
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{ |
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struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent); |
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struct stm32_pwm_lp *priv; |
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int ret; |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->regmap = ddata->regmap; |
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priv->clk = ddata->clk; |
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priv->chip.base = -1; |
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priv->chip.dev = &pdev->dev; |
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priv->chip.ops = &stm32_pwm_lp_ops; |
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priv->chip.npwm = 1; |
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priv->chip.of_xlate = of_pwm_xlate_with_flags; |
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priv->chip.of_pwm_n_cells = 3; |
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ret = pwmchip_add(&priv->chip); |
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if (ret < 0) |
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return ret; |
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platform_set_drvdata(pdev, priv); |
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return 0; |
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} |
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static int stm32_pwm_lp_remove(struct platform_device *pdev) |
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{ |
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struct stm32_pwm_lp *priv = platform_get_drvdata(pdev); |
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pwm_disable(&priv->chip.pwms[0]); |
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return pwmchip_remove(&priv->chip); |
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} |
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static int __maybe_unused stm32_pwm_lp_suspend(struct device *dev) |
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{ |
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struct stm32_pwm_lp *priv = dev_get_drvdata(dev); |
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struct pwm_state state; |
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pwm_get_state(&priv->chip.pwms[0], &state); |
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if (state.enabled) { |
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dev_err(dev, "The consumer didn't stop us (%s)\n", |
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priv->chip.pwms[0].label); |
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return -EBUSY; |
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} |
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return pinctrl_pm_select_sleep_state(dev); |
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} |
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static int __maybe_unused stm32_pwm_lp_resume(struct device *dev) |
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{ |
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return pinctrl_pm_select_default_state(dev); |
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} |
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static SIMPLE_DEV_PM_OPS(stm32_pwm_lp_pm_ops, stm32_pwm_lp_suspend, |
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stm32_pwm_lp_resume); |
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static const struct of_device_id stm32_pwm_lp_of_match[] = { |
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{ .compatible = "st,stm32-pwm-lp", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match); |
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static struct platform_driver stm32_pwm_lp_driver = { |
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.probe = stm32_pwm_lp_probe, |
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.remove = stm32_pwm_lp_remove, |
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.driver = { |
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.name = "stm32-pwm-lp", |
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.of_match_table = of_match_ptr(stm32_pwm_lp_of_match), |
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.pm = &stm32_pwm_lp_pm_ops, |
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}, |
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}; |
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module_platform_driver(stm32_pwm_lp_driver); |
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MODULE_ALIAS("platform:stm32-pwm-lp"); |
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MODULE_DESCRIPTION("STMicroelectronics STM32 PWM LP driver"); |
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MODULE_LICENSE("GPL v2");
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