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196 lines
4.7 KiB
196 lines
4.7 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2012 Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pwm.h> |
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#include <linux/slab.h> |
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#include <linux/stmp_device.h> |
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#define SET 0x4 |
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#define CLR 0x8 |
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#define TOG 0xc |
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#define PWM_CTRL 0x0 |
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#define PWM_ACTIVE0 0x10 |
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#define PWM_PERIOD0 0x20 |
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#define PERIOD_PERIOD(p) ((p) & 0xffff) |
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#define PERIOD_PERIOD_MAX 0x10000 |
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#define PERIOD_ACTIVE_HIGH (3 << 16) |
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#define PERIOD_ACTIVE_LOW (2 << 16) |
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#define PERIOD_INACTIVE_HIGH (3 << 18) |
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#define PERIOD_INACTIVE_LOW (2 << 18) |
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#define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW) |
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#define PERIOD_POLARITY_INVERSE (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH) |
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#define PERIOD_CDIV(div) (((div) & 0x7) << 20) |
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#define PERIOD_CDIV_MAX 8 |
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static const u8 cdiv_shift[PERIOD_CDIV_MAX] = { |
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0, 1, 2, 3, 4, 6, 8, 10 |
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}; |
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struct mxs_pwm_chip { |
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struct pwm_chip chip; |
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struct clk *clk; |
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void __iomem *base; |
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}; |
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#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip) |
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static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
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const struct pwm_state *state) |
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{ |
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struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip); |
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int ret, div = 0; |
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unsigned int period_cycles, duty_cycles; |
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unsigned long rate; |
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unsigned long long c; |
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unsigned int pol_bits; |
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/* |
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* If the PWM channel is disabled, make sure to turn on the |
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* clock before calling clk_get_rate() and writing to the |
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* registers. Otherwise, just keep it enabled. |
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*/ |
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if (!pwm_is_enabled(pwm)) { |
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ret = clk_prepare_enable(mxs->clk); |
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if (ret) |
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return ret; |
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} |
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if (!state->enabled && pwm_is_enabled(pwm)) |
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writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); |
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rate = clk_get_rate(mxs->clk); |
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while (1) { |
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c = rate >> cdiv_shift[div]; |
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c = c * state->period; |
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do_div(c, 1000000000); |
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if (c < PERIOD_PERIOD_MAX) |
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break; |
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div++; |
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if (div >= PERIOD_CDIV_MAX) |
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return -EINVAL; |
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} |
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period_cycles = c; |
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c *= state->duty_cycle; |
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do_div(c, state->period); |
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duty_cycles = c; |
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/* |
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* The data sheet the says registers must be written to in |
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* this order (ACTIVEn, then PERIODn). Also, the new settings |
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* only take effect at the beginning of a new period, avoiding |
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* glitches. |
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*/ |
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pol_bits = state->polarity == PWM_POLARITY_NORMAL ? |
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PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE; |
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writel(duty_cycles << 16, |
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mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); |
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writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div), |
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mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20); |
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if (state->enabled) { |
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if (!pwm_is_enabled(pwm)) { |
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/* |
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* The clock was enabled above. Just enable |
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* the channel in the control register. |
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*/ |
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writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET); |
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} |
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} else { |
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clk_disable_unprepare(mxs->clk); |
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} |
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return 0; |
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} |
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static const struct pwm_ops mxs_pwm_ops = { |
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.apply = mxs_pwm_apply, |
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.owner = THIS_MODULE, |
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}; |
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static int mxs_pwm_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct mxs_pwm_chip *mxs; |
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int ret; |
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mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL); |
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if (!mxs) |
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return -ENOMEM; |
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mxs->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(mxs->base)) |
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return PTR_ERR(mxs->base); |
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mxs->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(mxs->clk)) |
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return PTR_ERR(mxs->clk); |
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mxs->chip.dev = &pdev->dev; |
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mxs->chip.ops = &mxs_pwm_ops; |
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mxs->chip.of_xlate = of_pwm_xlate_with_flags; |
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mxs->chip.of_pwm_n_cells = 3; |
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mxs->chip.base = -1; |
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ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret); |
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return ret; |
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} |
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ret = pwmchip_add(&mxs->chip); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret); |
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return ret; |
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} |
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platform_set_drvdata(pdev, mxs); |
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ret = stmp_reset_block(mxs->base); |
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if (ret) |
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goto pwm_remove; |
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return 0; |
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pwm_remove: |
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pwmchip_remove(&mxs->chip); |
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return ret; |
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} |
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static int mxs_pwm_remove(struct platform_device *pdev) |
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{ |
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struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev); |
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return pwmchip_remove(&mxs->chip); |
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} |
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static const struct of_device_id mxs_pwm_dt_ids[] = { |
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{ .compatible = "fsl,imx23-pwm", }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids); |
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static struct platform_driver mxs_pwm_driver = { |
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.driver = { |
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.name = "mxs-pwm", |
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.of_match_table = mxs_pwm_dt_ids, |
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}, |
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.probe = mxs_pwm_probe, |
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.remove = mxs_pwm_remove, |
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}; |
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module_platform_driver(mxs_pwm_driver); |
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MODULE_ALIAS("platform:mxs-pwm"); |
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MODULE_AUTHOR("Shawn Guo <[email protected]>"); |
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MODULE_DESCRIPTION("Freescale MXS PWM Driver"); |
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MODULE_LICENSE("GPL v2");
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