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271 lines
7.0 KiB
271 lines
7.0 KiB
/* |
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* Atmel AT91 SAM9 & SAMA5 SoCs reset code |
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* |
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* Copyright (C) 2007 Atmel Corporation. |
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* Copyright (C) BitBox Ltd 2010 |
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <[email protected]> |
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* Copyright (C) 2014 Free Electrons |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/reboot.h> |
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#include <soc/at91/at91sam9_ddrsdr.h> |
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#include <soc/at91/at91sam9_sdramc.h> |
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#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ |
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#define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ |
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#define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */ |
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#define AT91_RSTC_EXTRST BIT(3) /* External Reset */ |
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#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ |
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#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */ |
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#define AT91_RSTC_URSTS BIT(0) /* User Reset Status */ |
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#define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */ |
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#define AT91_RSTC_NRSTL BIT(16) /* NRST Pin Level */ |
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#define AT91_RSTC_SRCMP BIT(17) /* Software Reset Command in Progress */ |
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#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */ |
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#define AT91_RSTC_URSTEN BIT(0) /* User Reset Enable */ |
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#define AT91_RSTC_URSTASYNC BIT(2) /* User Reset Asynchronous Control */ |
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#define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ |
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#define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */ |
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enum reset_type { |
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RESET_TYPE_GENERAL = 0, |
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RESET_TYPE_WAKEUP = 1, |
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RESET_TYPE_WATCHDOG = 2, |
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RESET_TYPE_SOFTWARE = 3, |
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RESET_TYPE_USER = 4, |
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RESET_TYPE_CPU_FAIL = 6, |
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RESET_TYPE_XTAL_FAIL = 7, |
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RESET_TYPE_ULP2 = 8, |
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}; |
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struct at91_reset { |
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void __iomem *rstc_base; |
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void __iomem *ramc_base[2]; |
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struct clk *sclk; |
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struct notifier_block nb; |
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u32 args; |
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u32 ramc_lpr; |
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}; |
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/* |
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* unless the SDRAM is cleanly shutdown before we hit the |
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* reset register it can be left driving the data bus and |
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* killing the chance of a subsequent boot from NAND |
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*/ |
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static int at91_reset(struct notifier_block *this, unsigned long mode, |
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void *cmd) |
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{ |
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struct at91_reset *reset = container_of(this, struct at91_reset, nb); |
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asm volatile( |
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/* Align to cache lines */ |
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".balign 32\n\t" |
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/* Disable SDRAM0 accesses */ |
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" tst %0, #0\n\t" |
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" beq 1f\n\t" |
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" str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" |
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/* Power down SDRAM0 */ |
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" str %4, [%0, %6]\n\t" |
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/* Disable SDRAM1 accesses */ |
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"1: tst %1, #0\n\t" |
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" beq 2f\n\t" |
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" strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" |
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/* Power down SDRAM1 */ |
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" strne %4, [%1, %6]\n\t" |
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/* Reset CPU */ |
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"2: str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t" |
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" b .\n\t" |
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: |
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: "r" (reset->ramc_base[0]), |
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"r" (reset->ramc_base[1]), |
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"r" (reset->rstc_base), |
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"r" (1), |
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"r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN), |
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"r" (reset->args), |
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"r" (reset->ramc_lpr) |
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: "r4"); |
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return NOTIFY_DONE; |
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} |
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static void __init at91_reset_status(struct platform_device *pdev, |
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void __iomem *base) |
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{ |
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const char *reason; |
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u32 reg = readl(base + AT91_RSTC_SR); |
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switch ((reg & AT91_RSTC_RSTTYP) >> 8) { |
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case RESET_TYPE_GENERAL: |
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reason = "general reset"; |
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break; |
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case RESET_TYPE_WAKEUP: |
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reason = "wakeup"; |
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break; |
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case RESET_TYPE_WATCHDOG: |
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reason = "watchdog reset"; |
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break; |
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case RESET_TYPE_SOFTWARE: |
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reason = "software reset"; |
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break; |
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case RESET_TYPE_USER: |
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reason = "user reset"; |
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break; |
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case RESET_TYPE_CPU_FAIL: |
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reason = "CPU clock failure detection"; |
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break; |
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case RESET_TYPE_XTAL_FAIL: |
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reason = "32.768 kHz crystal failure detection"; |
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break; |
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case RESET_TYPE_ULP2: |
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reason = "ULP2 reset"; |
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break; |
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default: |
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reason = "unknown reset"; |
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break; |
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} |
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dev_info(&pdev->dev, "Starting after %s\n", reason); |
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} |
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static const struct of_device_id at91_ramc_of_match[] = { |
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{ |
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.compatible = "atmel,at91sam9260-sdramc", |
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.data = (void *)AT91_SDRAMC_LPR, |
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}, |
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{ |
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.compatible = "atmel,at91sam9g45-ddramc", |
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.data = (void *)AT91_DDRSDRC_LPR, |
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}, |
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{ /* sentinel */ } |
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}; |
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static const struct of_device_id at91_reset_of_match[] = { |
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{ |
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.compatible = "atmel,at91sam9260-rstc", |
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.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | |
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AT91_RSTC_PROCRST), |
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}, |
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{ |
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.compatible = "atmel,at91sam9g45-rstc", |
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.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | |
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AT91_RSTC_PROCRST) |
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}, |
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{ |
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.compatible = "atmel,sama5d3-rstc", |
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.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | |
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AT91_RSTC_PROCRST) |
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}, |
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{ |
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.compatible = "atmel,samx7-rstc", |
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.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) |
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}, |
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{ |
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.compatible = "microchip,sam9x60-rstc", |
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.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) |
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}, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, at91_reset_of_match); |
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static int __init at91_reset_probe(struct platform_device *pdev) |
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{ |
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const struct of_device_id *match; |
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struct at91_reset *reset; |
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struct device_node *np; |
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int ret, idx = 0; |
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reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); |
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if (!reset) |
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return -ENOMEM; |
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reset->rstc_base = of_iomap(pdev->dev.of_node, 0); |
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if (!reset->rstc_base) { |
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dev_err(&pdev->dev, "Could not map reset controller address\n"); |
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return -ENODEV; |
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} |
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if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) { |
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/* we need to shutdown the ddr controller, so get ramc base */ |
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for_each_matching_node_and_match(np, at91_ramc_of_match, &match) { |
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reset->ramc_lpr = (u32)match->data; |
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reset->ramc_base[idx] = of_iomap(np, 0); |
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if (!reset->ramc_base[idx]) { |
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dev_err(&pdev->dev, "Could not map ram controller address\n"); |
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of_node_put(np); |
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return -ENODEV; |
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} |
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idx++; |
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} |
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} |
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match = of_match_node(at91_reset_of_match, pdev->dev.of_node); |
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reset->nb.notifier_call = at91_reset; |
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reset->nb.priority = 192; |
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reset->args = (u32)match->data; |
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reset->sclk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(reset->sclk)) |
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return PTR_ERR(reset->sclk); |
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ret = clk_prepare_enable(reset->sclk); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not enable slow clock\n"); |
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return ret; |
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} |
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platform_set_drvdata(pdev, reset); |
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if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) { |
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u32 val = readl(reset->rstc_base + AT91_RSTC_MR); |
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writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val, |
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reset->rstc_base + AT91_RSTC_MR); |
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} |
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ret = register_restart_handler(&reset->nb); |
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if (ret) { |
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clk_disable_unprepare(reset->sclk); |
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return ret; |
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} |
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at91_reset_status(pdev, reset->rstc_base); |
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return 0; |
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} |
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static int __exit at91_reset_remove(struct platform_device *pdev) |
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{ |
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struct at91_reset *reset = platform_get_drvdata(pdev); |
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unregister_restart_handler(&reset->nb); |
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clk_disable_unprepare(reset->sclk); |
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return 0; |
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} |
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static struct platform_driver at91_reset_driver = { |
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.remove = __exit_p(at91_reset_remove), |
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.driver = { |
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.name = "at91-reset", |
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.of_match_table = at91_reset_of_match, |
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}, |
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}; |
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module_platform_driver_probe(at91_reset_driver, at91_reset_probe); |
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MODULE_AUTHOR("Atmel Corporation"); |
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MODULE_DESCRIPTION("Reset driver for Atmel SoCs"); |
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MODULE_LICENSE("GPL v2");
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