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1096 lines
27 KiB
1096 lines
27 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Standard PCI Hot Plug Driver |
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* |
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* Copyright (C) 1995,2001 Compaq Computer Corporation |
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* Copyright (C) 2001 Greg Kroah-Hartman ([email protected]) |
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* Copyright (C) 2001 IBM Corp. |
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* Copyright (C) 2003-2004 Intel Corporation |
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* |
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* All rights reserved. |
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* |
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* Send feedback to <[email protected]>,<[email protected]> |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/interrupt.h> |
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#include "shpchp.h" |
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|
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/* Slot Available Register I field definition */ |
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#define SLOT_33MHZ 0x0000001f |
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#define SLOT_66MHZ_PCIX 0x00001f00 |
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#define SLOT_100MHZ_PCIX 0x001f0000 |
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#define SLOT_133MHZ_PCIX 0x1f000000 |
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|
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/* Slot Available Register II field definition */ |
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#define SLOT_66MHZ 0x0000001f |
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#define SLOT_66MHZ_PCIX_266 0x00000f00 |
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#define SLOT_100MHZ_PCIX_266 0x0000f000 |
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#define SLOT_133MHZ_PCIX_266 0x000f0000 |
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#define SLOT_66MHZ_PCIX_533 0x00f00000 |
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#define SLOT_100MHZ_PCIX_533 0x0f000000 |
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#define SLOT_133MHZ_PCIX_533 0xf0000000 |
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|
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/* Slot Configuration */ |
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#define SLOT_NUM 0x0000001F |
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#define FIRST_DEV_NUM 0x00001F00 |
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#define PSN 0x07FF0000 |
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#define UPDOWN 0x20000000 |
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#define MRLSENSOR 0x40000000 |
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#define ATTN_BUTTON 0x80000000 |
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|
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/* |
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* Interrupt Locator Register definitions |
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*/ |
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#define CMD_INTR_PENDING (1 << 0) |
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#define SLOT_INTR_PENDING(i) (1 << (i + 1)) |
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|
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/* |
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* Controller SERR-INT Register |
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*/ |
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#define GLOBAL_INTR_MASK (1 << 0) |
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#define GLOBAL_SERR_MASK (1 << 1) |
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#define COMMAND_INTR_MASK (1 << 2) |
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#define ARBITER_SERR_MASK (1 << 3) |
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#define COMMAND_DETECTED (1 << 16) |
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#define ARBITER_DETECTED (1 << 17) |
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#define SERR_INTR_RSVDZ_MASK 0xfffc0000 |
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|
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/* |
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* Logical Slot Register definitions |
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*/ |
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#define SLOT_REG(i) (SLOT1 + (4 * i)) |
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|
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#define SLOT_STATE_SHIFT (0) |
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#define SLOT_STATE_MASK (3 << 0) |
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#define SLOT_STATE_PWRONLY (1) |
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#define SLOT_STATE_ENABLED (2) |
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#define SLOT_STATE_DISABLED (3) |
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#define PWR_LED_STATE_SHIFT (2) |
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#define PWR_LED_STATE_MASK (3 << 2) |
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#define ATN_LED_STATE_SHIFT (4) |
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#define ATN_LED_STATE_MASK (3 << 4) |
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#define ATN_LED_STATE_ON (1) |
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#define ATN_LED_STATE_BLINK (2) |
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#define ATN_LED_STATE_OFF (3) |
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#define POWER_FAULT (1 << 6) |
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#define ATN_BUTTON (1 << 7) |
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#define MRL_SENSOR (1 << 8) |
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#define MHZ66_CAP (1 << 9) |
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#define PRSNT_SHIFT (10) |
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#define PRSNT_MASK (3 << 10) |
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#define PCIX_CAP_SHIFT (12) |
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#define PCIX_CAP_MASK_PI1 (3 << 12) |
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#define PCIX_CAP_MASK_PI2 (7 << 12) |
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#define PRSNT_CHANGE_DETECTED (1 << 16) |
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#define ISO_PFAULT_DETECTED (1 << 17) |
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#define BUTTON_PRESS_DETECTED (1 << 18) |
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#define MRL_CHANGE_DETECTED (1 << 19) |
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#define CON_PFAULT_DETECTED (1 << 20) |
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#define PRSNT_CHANGE_INTR_MASK (1 << 24) |
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#define ISO_PFAULT_INTR_MASK (1 << 25) |
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#define BUTTON_PRESS_INTR_MASK (1 << 26) |
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#define MRL_CHANGE_INTR_MASK (1 << 27) |
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#define CON_PFAULT_INTR_MASK (1 << 28) |
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#define MRL_CHANGE_SERR_MASK (1 << 29) |
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#define CON_PFAULT_SERR_MASK (1 << 30) |
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#define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) |
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|
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/* |
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* SHPC Command Code definitions |
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* |
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* Slot Operation 00h - 3Fh |
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* Set Bus Segment Speed/Mode A 40h - 47h |
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* Power-Only All Slots 48h |
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* Enable All Slots 49h |
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* Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh |
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* Reserved Command Codes 60h - BFh |
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* Vendor Specific Commands C0h - FFh |
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*/ |
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#define SET_SLOT_PWR 0x01 /* Slot Operation */ |
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#define SET_SLOT_ENABLE 0x02 |
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#define SET_SLOT_DISABLE 0x03 |
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#define SET_PWR_ON 0x04 |
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#define SET_PWR_BLINK 0x08 |
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#define SET_PWR_OFF 0x0c |
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#define SET_ATTN_ON 0x10 |
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#define SET_ATTN_BLINK 0x20 |
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#define SET_ATTN_OFF 0x30 |
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#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ |
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#define SETA_PCI_66MHZ 0x41 |
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#define SETA_PCIX_66MHZ 0x42 |
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#define SETA_PCIX_100MHZ 0x43 |
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#define SETA_PCIX_133MHZ 0x44 |
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#define SETA_RESERVED1 0x45 |
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#define SETA_RESERVED2 0x46 |
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#define SETA_RESERVED3 0x47 |
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#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ |
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#define SET_ENABLE_ALL 0x49 /* Enable All Slots */ |
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#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ |
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#define SETB_PCI_66MHZ 0x51 |
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#define SETB_PCIX_66MHZ_PM 0x52 |
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#define SETB_PCIX_100MHZ_PM 0x53 |
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#define SETB_PCIX_133MHZ_PM 0x54 |
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#define SETB_PCIX_66MHZ_EM 0x55 |
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#define SETB_PCIX_100MHZ_EM 0x56 |
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#define SETB_PCIX_133MHZ_EM 0x57 |
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#define SETB_PCIX_66MHZ_266 0x58 |
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#define SETB_PCIX_100MHZ_266 0x59 |
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#define SETB_PCIX_133MHZ_266 0x5a |
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#define SETB_PCIX_66MHZ_533 0x5b |
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#define SETB_PCIX_100MHZ_533 0x5c |
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#define SETB_PCIX_133MHZ_533 0x5d |
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#define SETB_RESERVED1 0x5e |
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#define SETB_RESERVED2 0x5f |
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|
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/* |
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* SHPC controller command error code |
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*/ |
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#define SWITCH_OPEN 0x1 |
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#define INVALID_CMD 0x2 |
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#define INVALID_SPEED_MODE 0x4 |
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|
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/* |
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* For accessing SHPC Working Register Set via PCI Configuration Space |
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*/ |
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#define DWORD_SELECT 0x2 |
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#define DWORD_DATA 0x4 |
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|
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/* Field Offset in Logical Slot Register - byte boundary */ |
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#define SLOT_EVENT_LATCH 0x2 |
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#define SLOT_SERR_INT_MASK 0x3 |
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static irqreturn_t shpc_isr(int irq, void *dev_id); |
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static void start_int_poll_timer(struct controller *ctrl, int sec); |
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static int hpc_check_cmd_status(struct controller *ctrl); |
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static inline u8 shpc_readb(struct controller *ctrl, int reg) |
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{ |
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return readb(ctrl->creg + reg); |
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} |
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static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) |
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{ |
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writeb(val, ctrl->creg + reg); |
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} |
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static inline u16 shpc_readw(struct controller *ctrl, int reg) |
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{ |
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return readw(ctrl->creg + reg); |
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} |
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static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) |
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{ |
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writew(val, ctrl->creg + reg); |
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} |
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static inline u32 shpc_readl(struct controller *ctrl, int reg) |
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{ |
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return readl(ctrl->creg + reg); |
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} |
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static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) |
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{ |
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writel(val, ctrl->creg + reg); |
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} |
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static inline int shpc_indirect_read(struct controller *ctrl, int index, |
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u32 *value) |
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{ |
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int rc; |
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u32 cap_offset = ctrl->cap_offset; |
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struct pci_dev *pdev = ctrl->pci_dev; |
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rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); |
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if (rc) |
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return rc; |
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return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); |
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} |
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/* |
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* This is the interrupt polling timeout function. |
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*/ |
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static void int_poll_timeout(struct timer_list *t) |
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{ |
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struct controller *ctrl = from_timer(ctrl, t, poll_timer); |
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/* Poll for interrupt events. regs == NULL => polling */ |
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shpc_isr(0, ctrl); |
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if (!shpchp_poll_time) |
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shpchp_poll_time = 2; /* default polling interval is 2 sec */ |
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start_int_poll_timer(ctrl, shpchp_poll_time); |
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} |
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/* |
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* This function starts the interrupt polling timer. |
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*/ |
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static void start_int_poll_timer(struct controller *ctrl, int sec) |
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{ |
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/* Clamp to sane value */ |
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if ((sec <= 0) || (sec > 60)) |
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sec = 2; |
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ctrl->poll_timer.expires = jiffies + sec * HZ; |
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add_timer(&ctrl->poll_timer); |
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} |
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static inline int is_ctrl_busy(struct controller *ctrl) |
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{ |
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u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); |
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return cmd_status & 0x1; |
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} |
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/* |
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* Returns 1 if SHPC finishes executing a command within 1 sec, |
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* otherwise returns 0. |
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*/ |
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static inline int shpc_poll_ctrl_busy(struct controller *ctrl) |
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{ |
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int i; |
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if (!is_ctrl_busy(ctrl)) |
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return 1; |
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/* Check every 0.1 sec for a total of 1 sec */ |
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for (i = 0; i < 10; i++) { |
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msleep(100); |
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if (!is_ctrl_busy(ctrl)) |
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return 1; |
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} |
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return 0; |
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} |
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static inline int shpc_wait_cmd(struct controller *ctrl) |
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{ |
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int retval = 0; |
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unsigned long timeout = msecs_to_jiffies(1000); |
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int rc; |
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if (shpchp_poll_mode) |
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rc = shpc_poll_ctrl_busy(ctrl); |
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else |
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rc = wait_event_interruptible_timeout(ctrl->queue, |
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!is_ctrl_busy(ctrl), timeout); |
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if (!rc && is_ctrl_busy(ctrl)) { |
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retval = -EIO; |
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ctrl_err(ctrl, "Command not completed in 1000 msec\n"); |
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} else if (rc < 0) { |
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retval = -EINTR; |
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ctrl_info(ctrl, "Command was interrupted by a signal\n"); |
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} |
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return retval; |
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} |
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static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) |
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{ |
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struct controller *ctrl = slot->ctrl; |
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u16 cmd_status; |
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int retval = 0; |
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u16 temp_word; |
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mutex_lock(&slot->ctrl->cmd_lock); |
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if (!shpc_poll_ctrl_busy(ctrl)) { |
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/* After 1 sec and and the controller is still busy */ |
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ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); |
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retval = -EBUSY; |
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goto out; |
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} |
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++t_slot; |
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temp_word = (t_slot << 8) | (cmd & 0xFF); |
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ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); |
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/* To make sure the Controller Busy bit is 0 before we send out the |
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* command. |
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*/ |
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shpc_writew(ctrl, CMD, temp_word); |
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/* |
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* Wait for command completion. |
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*/ |
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retval = shpc_wait_cmd(slot->ctrl); |
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if (retval) |
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goto out; |
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cmd_status = hpc_check_cmd_status(slot->ctrl); |
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if (cmd_status) { |
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ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n", |
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cmd, cmd_status); |
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retval = -EIO; |
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} |
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out: |
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mutex_unlock(&slot->ctrl->cmd_lock); |
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return retval; |
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} |
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static int hpc_check_cmd_status(struct controller *ctrl) |
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{ |
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int retval = 0; |
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u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; |
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switch (cmd_status >> 1) { |
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case 0: |
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retval = 0; |
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break; |
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case 1: |
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retval = SWITCH_OPEN; |
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ctrl_err(ctrl, "Switch opened!\n"); |
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break; |
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case 2: |
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retval = INVALID_CMD; |
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ctrl_err(ctrl, "Invalid HPC command!\n"); |
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break; |
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case 4: |
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retval = INVALID_SPEED_MODE; |
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ctrl_err(ctrl, "Invalid bus speed/mode!\n"); |
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break; |
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default: |
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retval = cmd_status; |
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} |
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return retval; |
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} |
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static int hpc_get_attention_status(struct slot *slot, u8 *status) |
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{ |
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struct controller *ctrl = slot->ctrl; |
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
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u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; |
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switch (state) { |
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case ATN_LED_STATE_ON: |
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*status = 1; /* On */ |
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break; |
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case ATN_LED_STATE_BLINK: |
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*status = 2; /* Blink */ |
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break; |
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case ATN_LED_STATE_OFF: |
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*status = 0; /* Off */ |
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break; |
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default: |
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*status = 0xFF; /* Reserved */ |
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break; |
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} |
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return 0; |
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} |
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static int hpc_get_power_status(struct slot *slot, u8 *status) |
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{ |
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struct controller *ctrl = slot->ctrl; |
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
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u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; |
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switch (state) { |
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case SLOT_STATE_PWRONLY: |
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*status = 2; /* Powered only */ |
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break; |
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case SLOT_STATE_ENABLED: |
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*status = 1; /* Enabled */ |
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break; |
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case SLOT_STATE_DISABLED: |
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*status = 0; /* Disabled */ |
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break; |
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default: |
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*status = 0xFF; /* Reserved */ |
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break; |
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} |
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return 0; |
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} |
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static int hpc_get_latch_status(struct slot *slot, u8 *status) |
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{ |
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struct controller *ctrl = slot->ctrl; |
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
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*status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ |
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return 0; |
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} |
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static int hpc_get_adapter_status(struct slot *slot, u8 *status) |
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{ |
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struct controller *ctrl = slot->ctrl; |
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
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u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; |
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*status = (state != 0x3) ? 1 : 0; |
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return 0; |
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} |
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static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) |
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{ |
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struct controller *ctrl = slot->ctrl; |
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*prog_int = shpc_readb(ctrl, PROG_INTERFACE); |
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return 0; |
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} |
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static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) |
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{ |
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int retval = 0; |
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struct controller *ctrl = slot->ctrl; |
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
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u8 m66_cap = !!(slot_reg & MHZ66_CAP); |
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u8 pi, pcix_cap; |
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retval = hpc_get_prog_int(slot, &pi); |
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if (retval) |
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return retval; |
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switch (pi) { |
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case 1: |
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pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; |
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break; |
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case 2: |
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pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; |
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break; |
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default: |
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return -ENODEV; |
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} |
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ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", |
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__func__, slot_reg, pcix_cap, m66_cap); |
|
|
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switch (pcix_cap) { |
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case 0x0: |
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*value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; |
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break; |
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case 0x1: |
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*value = PCI_SPEED_66MHz_PCIX; |
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break; |
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case 0x3: |
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*value = PCI_SPEED_133MHz_PCIX; |
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break; |
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case 0x4: |
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*value = PCI_SPEED_133MHz_PCIX_266; |
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break; |
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case 0x5: |
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*value = PCI_SPEED_133MHz_PCIX_533; |
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break; |
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case 0x2: |
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default: |
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*value = PCI_SPEED_UNKNOWN; |
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retval = -ENODEV; |
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break; |
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} |
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|
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ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); |
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return retval; |
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} |
|
|
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static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) |
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{ |
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int retval = 0; |
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struct controller *ctrl = slot->ctrl; |
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u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); |
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u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
|
|
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if (pi == 2) { |
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*mode = (sec_bus_status & 0x0100) >> 8; |
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} else { |
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retval = -1; |
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} |
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|
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ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode); |
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return retval; |
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} |
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|
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static int hpc_query_power_fault(struct slot *slot) |
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{ |
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struct controller *ctrl = slot->ctrl; |
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u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
|
|
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/* Note: Logic 0 => fault */ |
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return !(slot_reg & POWER_FAULT); |
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} |
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|
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static int hpc_set_attention_status(struct slot *slot, u8 value) |
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{ |
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u8 slot_cmd = 0; |
|
|
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switch (value) { |
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case 0: |
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slot_cmd = SET_ATTN_OFF; /* OFF */ |
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break; |
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case 1: |
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slot_cmd = SET_ATTN_ON; /* ON */ |
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break; |
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case 2: |
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slot_cmd = SET_ATTN_BLINK; /* BLINK */ |
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break; |
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default: |
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return -1; |
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} |
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|
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return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); |
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} |
|
|
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|
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static void hpc_set_green_led_on(struct slot *slot) |
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{ |
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shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); |
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} |
|
|
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static void hpc_set_green_led_off(struct slot *slot) |
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{ |
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shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); |
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} |
|
|
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static void hpc_set_green_led_blink(struct slot *slot) |
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{ |
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shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); |
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} |
|
|
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static void hpc_release_ctlr(struct controller *ctrl) |
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{ |
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int i; |
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u32 slot_reg, serr_int; |
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|
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/* |
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* Mask event interrupts and SERRs of all slots |
|
*/ |
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for (i = 0; i < ctrl->num_slots; i++) { |
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slot_reg = shpc_readl(ctrl, SLOT_REG(i)); |
|
slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
|
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | |
|
CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | |
|
CON_PFAULT_SERR_MASK); |
|
slot_reg &= ~SLOT_REG_RSVDZ_MASK; |
|
shpc_writel(ctrl, SLOT_REG(i), slot_reg); |
|
} |
|
|
|
cleanup_slots(ctrl); |
|
|
|
/* |
|
* Mask SERR and System Interrupt generation |
|
*/ |
|
serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
|
serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | |
|
COMMAND_INTR_MASK | ARBITER_SERR_MASK); |
|
serr_int &= ~SERR_INTR_RSVDZ_MASK; |
|
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); |
|
|
|
if (shpchp_poll_mode) |
|
del_timer(&ctrl->poll_timer); |
|
else { |
|
free_irq(ctrl->pci_dev->irq, ctrl); |
|
pci_disable_msi(ctrl->pci_dev); |
|
} |
|
|
|
iounmap(ctrl->creg); |
|
release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
|
} |
|
|
|
static int hpc_power_on_slot(struct slot *slot) |
|
{ |
|
int retval; |
|
|
|
retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); |
|
if (retval) |
|
ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
|
|
|
return retval; |
|
} |
|
|
|
static int hpc_slot_enable(struct slot *slot) |
|
{ |
|
int retval; |
|
|
|
/* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ |
|
retval = shpc_write_cmd(slot, slot->hp_slot, |
|
SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); |
|
if (retval) |
|
ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
|
|
|
return retval; |
|
} |
|
|
|
static int hpc_slot_disable(struct slot *slot) |
|
{ |
|
int retval; |
|
|
|
/* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ |
|
retval = shpc_write_cmd(slot, slot->hp_slot, |
|
SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); |
|
if (retval) |
|
ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
|
|
|
return retval; |
|
} |
|
|
|
static int shpc_get_cur_bus_speed(struct controller *ctrl) |
|
{ |
|
int retval = 0; |
|
struct pci_bus *bus = ctrl->pci_dev->subordinate; |
|
enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
|
u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); |
|
u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
|
u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); |
|
|
|
if ((pi == 1) && (speed_mode > 4)) { |
|
retval = -ENODEV; |
|
goto out; |
|
} |
|
|
|
switch (speed_mode) { |
|
case 0x0: |
|
bus_speed = PCI_SPEED_33MHz; |
|
break; |
|
case 0x1: |
|
bus_speed = PCI_SPEED_66MHz; |
|
break; |
|
case 0x2: |
|
bus_speed = PCI_SPEED_66MHz_PCIX; |
|
break; |
|
case 0x3: |
|
bus_speed = PCI_SPEED_100MHz_PCIX; |
|
break; |
|
case 0x4: |
|
bus_speed = PCI_SPEED_133MHz_PCIX; |
|
break; |
|
case 0x5: |
|
bus_speed = PCI_SPEED_66MHz_PCIX_ECC; |
|
break; |
|
case 0x6: |
|
bus_speed = PCI_SPEED_100MHz_PCIX_ECC; |
|
break; |
|
case 0x7: |
|
bus_speed = PCI_SPEED_133MHz_PCIX_ECC; |
|
break; |
|
case 0x8: |
|
bus_speed = PCI_SPEED_66MHz_PCIX_266; |
|
break; |
|
case 0x9: |
|
bus_speed = PCI_SPEED_100MHz_PCIX_266; |
|
break; |
|
case 0xa: |
|
bus_speed = PCI_SPEED_133MHz_PCIX_266; |
|
break; |
|
case 0xb: |
|
bus_speed = PCI_SPEED_66MHz_PCIX_533; |
|
break; |
|
case 0xc: |
|
bus_speed = PCI_SPEED_100MHz_PCIX_533; |
|
break; |
|
case 0xd: |
|
bus_speed = PCI_SPEED_133MHz_PCIX_533; |
|
break; |
|
default: |
|
retval = -ENODEV; |
|
break; |
|
} |
|
|
|
out: |
|
bus->cur_bus_speed = bus_speed; |
|
dbg("Current bus speed = %d\n", bus_speed); |
|
return retval; |
|
} |
|
|
|
|
|
static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value) |
|
{ |
|
int retval; |
|
struct controller *ctrl = slot->ctrl; |
|
u8 pi, cmd; |
|
|
|
pi = shpc_readb(ctrl, PROG_INTERFACE); |
|
if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) |
|
return -EINVAL; |
|
|
|
switch (value) { |
|
case PCI_SPEED_33MHz: |
|
cmd = SETA_PCI_33MHZ; |
|
break; |
|
case PCI_SPEED_66MHz: |
|
cmd = SETA_PCI_66MHZ; |
|
break; |
|
case PCI_SPEED_66MHz_PCIX: |
|
cmd = SETA_PCIX_66MHZ; |
|
break; |
|
case PCI_SPEED_100MHz_PCIX: |
|
cmd = SETA_PCIX_100MHZ; |
|
break; |
|
case PCI_SPEED_133MHz_PCIX: |
|
cmd = SETA_PCIX_133MHZ; |
|
break; |
|
case PCI_SPEED_66MHz_PCIX_ECC: |
|
cmd = SETB_PCIX_66MHZ_EM; |
|
break; |
|
case PCI_SPEED_100MHz_PCIX_ECC: |
|
cmd = SETB_PCIX_100MHZ_EM; |
|
break; |
|
case PCI_SPEED_133MHz_PCIX_ECC: |
|
cmd = SETB_PCIX_133MHZ_EM; |
|
break; |
|
case PCI_SPEED_66MHz_PCIX_266: |
|
cmd = SETB_PCIX_66MHZ_266; |
|
break; |
|
case PCI_SPEED_100MHz_PCIX_266: |
|
cmd = SETB_PCIX_100MHZ_266; |
|
break; |
|
case PCI_SPEED_133MHz_PCIX_266: |
|
cmd = SETB_PCIX_133MHZ_266; |
|
break; |
|
case PCI_SPEED_66MHz_PCIX_533: |
|
cmd = SETB_PCIX_66MHZ_533; |
|
break; |
|
case PCI_SPEED_100MHz_PCIX_533: |
|
cmd = SETB_PCIX_100MHZ_533; |
|
break; |
|
case PCI_SPEED_133MHz_PCIX_533: |
|
cmd = SETB_PCIX_133MHZ_533; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
retval = shpc_write_cmd(slot, 0, cmd); |
|
if (retval) |
|
ctrl_err(ctrl, "%s: Write command failed!\n", __func__); |
|
else |
|
shpc_get_cur_bus_speed(ctrl); |
|
|
|
return retval; |
|
} |
|
|
|
static irqreturn_t shpc_isr(int irq, void *dev_id) |
|
{ |
|
struct controller *ctrl = (struct controller *)dev_id; |
|
u32 serr_int, slot_reg, intr_loc, intr_loc2; |
|
int hp_slot; |
|
|
|
/* Check to see if it was our interrupt */ |
|
intr_loc = shpc_readl(ctrl, INTR_LOC); |
|
if (!intr_loc) |
|
return IRQ_NONE; |
|
|
|
ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); |
|
|
|
if (!shpchp_poll_mode) { |
|
/* |
|
* Mask Global Interrupt Mask - see implementation |
|
* note on p. 139 of SHPC spec rev 1.0 |
|
*/ |
|
serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
|
serr_int |= GLOBAL_INTR_MASK; |
|
serr_int &= ~SERR_INTR_RSVDZ_MASK; |
|
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); |
|
|
|
intr_loc2 = shpc_readl(ctrl, INTR_LOC); |
|
ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); |
|
} |
|
|
|
if (intr_loc & CMD_INTR_PENDING) { |
|
/* |
|
* Command Complete Interrupt Pending |
|
* RO only - clear by writing 1 to the Command Completion |
|
* Detect bit in Controller SERR-INT register |
|
*/ |
|
serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
|
serr_int &= ~SERR_INTR_RSVDZ_MASK; |
|
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); |
|
|
|
wake_up_interruptible(&ctrl->queue); |
|
} |
|
|
|
if (!(intr_loc & ~CMD_INTR_PENDING)) |
|
goto out; |
|
|
|
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
|
/* To find out which slot has interrupt pending */ |
|
if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) |
|
continue; |
|
|
|
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
|
ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", |
|
hp_slot, slot_reg); |
|
|
|
if (slot_reg & MRL_CHANGE_DETECTED) |
|
shpchp_handle_switch_change(hp_slot, ctrl); |
|
|
|
if (slot_reg & BUTTON_PRESS_DETECTED) |
|
shpchp_handle_attention_button(hp_slot, ctrl); |
|
|
|
if (slot_reg & PRSNT_CHANGE_DETECTED) |
|
shpchp_handle_presence_change(hp_slot, ctrl); |
|
|
|
if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) |
|
shpchp_handle_power_fault(hp_slot, ctrl); |
|
|
|
/* Clear all slot events */ |
|
slot_reg &= ~SLOT_REG_RSVDZ_MASK; |
|
shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); |
|
} |
|
out: |
|
if (!shpchp_poll_mode) { |
|
/* Unmask Global Interrupt Mask */ |
|
serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
|
serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); |
|
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int shpc_get_max_bus_speed(struct controller *ctrl) |
|
{ |
|
int retval = 0; |
|
struct pci_bus *bus = ctrl->pci_dev->subordinate; |
|
enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
|
u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
|
u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); |
|
u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); |
|
|
|
if (pi == 2) { |
|
if (slot_avail2 & SLOT_133MHZ_PCIX_533) |
|
bus_speed = PCI_SPEED_133MHz_PCIX_533; |
|
else if (slot_avail2 & SLOT_100MHZ_PCIX_533) |
|
bus_speed = PCI_SPEED_100MHz_PCIX_533; |
|
else if (slot_avail2 & SLOT_66MHZ_PCIX_533) |
|
bus_speed = PCI_SPEED_66MHz_PCIX_533; |
|
else if (slot_avail2 & SLOT_133MHZ_PCIX_266) |
|
bus_speed = PCI_SPEED_133MHz_PCIX_266; |
|
else if (slot_avail2 & SLOT_100MHZ_PCIX_266) |
|
bus_speed = PCI_SPEED_100MHz_PCIX_266; |
|
else if (slot_avail2 & SLOT_66MHZ_PCIX_266) |
|
bus_speed = PCI_SPEED_66MHz_PCIX_266; |
|
} |
|
|
|
if (bus_speed == PCI_SPEED_UNKNOWN) { |
|
if (slot_avail1 & SLOT_133MHZ_PCIX) |
|
bus_speed = PCI_SPEED_133MHz_PCIX; |
|
else if (slot_avail1 & SLOT_100MHZ_PCIX) |
|
bus_speed = PCI_SPEED_100MHz_PCIX; |
|
else if (slot_avail1 & SLOT_66MHZ_PCIX) |
|
bus_speed = PCI_SPEED_66MHz_PCIX; |
|
else if (slot_avail2 & SLOT_66MHZ) |
|
bus_speed = PCI_SPEED_66MHz; |
|
else if (slot_avail1 & SLOT_33MHZ) |
|
bus_speed = PCI_SPEED_33MHz; |
|
else |
|
retval = -ENODEV; |
|
} |
|
|
|
bus->max_bus_speed = bus_speed; |
|
ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); |
|
|
|
return retval; |
|
} |
|
|
|
static const struct hpc_ops shpchp_hpc_ops = { |
|
.power_on_slot = hpc_power_on_slot, |
|
.slot_enable = hpc_slot_enable, |
|
.slot_disable = hpc_slot_disable, |
|
.set_bus_speed_mode = hpc_set_bus_speed_mode, |
|
.set_attention_status = hpc_set_attention_status, |
|
.get_power_status = hpc_get_power_status, |
|
.get_attention_status = hpc_get_attention_status, |
|
.get_latch_status = hpc_get_latch_status, |
|
.get_adapter_status = hpc_get_adapter_status, |
|
|
|
.get_adapter_speed = hpc_get_adapter_speed, |
|
.get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, |
|
.get_prog_int = hpc_get_prog_int, |
|
|
|
.query_power_fault = hpc_query_power_fault, |
|
.green_led_on = hpc_set_green_led_on, |
|
.green_led_off = hpc_set_green_led_off, |
|
.green_led_blink = hpc_set_green_led_blink, |
|
|
|
.release_ctlr = hpc_release_ctlr, |
|
}; |
|
|
|
int shpc_init(struct controller *ctrl, struct pci_dev *pdev) |
|
{ |
|
int rc = -1, num_slots = 0; |
|
u8 hp_slot; |
|
u32 shpc_base_offset; |
|
u32 tempdword, slot_reg, slot_config; |
|
u8 i; |
|
|
|
ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
|
ctrl_dbg(ctrl, "Hotplug Controller:\n"); |
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_AMD && |
|
pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) { |
|
/* amd shpc driver doesn't use Base Offset; assume 0 */ |
|
ctrl->mmio_base = pci_resource_start(pdev, 0); |
|
ctrl->mmio_size = pci_resource_len(pdev, 0); |
|
} else { |
|
ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); |
|
if (!ctrl->cap_offset) { |
|
ctrl_err(ctrl, "Cannot find PCI capability\n"); |
|
goto abort; |
|
} |
|
ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); |
|
|
|
rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); |
|
if (rc) { |
|
ctrl_err(ctrl, "Cannot read base_offset\n"); |
|
goto abort; |
|
} |
|
|
|
rc = shpc_indirect_read(ctrl, 3, &tempdword); |
|
if (rc) { |
|
ctrl_err(ctrl, "Cannot read slot config\n"); |
|
goto abort; |
|
} |
|
num_slots = tempdword & SLOT_NUM; |
|
ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); |
|
|
|
for (i = 0; i < 9 + num_slots; i++) { |
|
rc = shpc_indirect_read(ctrl, i, &tempdword); |
|
if (rc) { |
|
ctrl_err(ctrl, "Cannot read creg (index = %d)\n", |
|
i); |
|
goto abort; |
|
} |
|
ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); |
|
} |
|
|
|
ctrl->mmio_base = |
|
pci_resource_start(pdev, 0) + shpc_base_offset; |
|
ctrl->mmio_size = 0x24 + 0x4 * num_slots; |
|
} |
|
|
|
ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
|
pdev->vendor, pdev->device, pdev->subsystem_vendor, |
|
pdev->subsystem_device); |
|
|
|
rc = pci_enable_device(pdev); |
|
if (rc) { |
|
ctrl_err(ctrl, "pci_enable_device failed\n"); |
|
goto abort; |
|
} |
|
|
|
if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { |
|
ctrl_err(ctrl, "Cannot reserve MMIO region\n"); |
|
rc = -1; |
|
goto abort; |
|
} |
|
|
|
ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); |
|
if (!ctrl->creg) { |
|
ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", |
|
ctrl->mmio_size, ctrl->mmio_base); |
|
release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
|
rc = -1; |
|
goto abort; |
|
} |
|
ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); |
|
|
|
mutex_init(&ctrl->crit_sect); |
|
mutex_init(&ctrl->cmd_lock); |
|
|
|
/* Setup wait queue */ |
|
init_waitqueue_head(&ctrl->queue); |
|
|
|
ctrl->hpc_ops = &shpchp_hpc_ops; |
|
|
|
/* Return PCI Controller Info */ |
|
slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
|
ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; |
|
ctrl->num_slots = slot_config & SLOT_NUM; |
|
ctrl->first_slot = (slot_config & PSN) >> 16; |
|
ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; |
|
|
|
/* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ |
|
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
|
ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
|
tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | |
|
COMMAND_INTR_MASK | ARBITER_SERR_MASK); |
|
tempdword &= ~SERR_INTR_RSVDZ_MASK; |
|
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
|
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
|
ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
|
|
|
/* Mask the MRL sensor SERR Mask of individual slot in |
|
* Slot SERR-INT Mask & clear all the existing event if any |
|
*/ |
|
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
|
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
|
ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
|
hp_slot, slot_reg); |
|
slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
|
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | |
|
CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | |
|
CON_PFAULT_SERR_MASK); |
|
slot_reg &= ~SLOT_REG_RSVDZ_MASK; |
|
shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); |
|
} |
|
|
|
if (shpchp_poll_mode) { |
|
/* Install interrupt polling timer. Start with 10 sec delay */ |
|
timer_setup(&ctrl->poll_timer, int_poll_timeout, 0); |
|
start_int_poll_timer(ctrl, 10); |
|
} else { |
|
/* Installs the interrupt handler */ |
|
rc = pci_enable_msi(pdev); |
|
if (rc) { |
|
ctrl_info(ctrl, "Can't get msi for the hotplug controller\n"); |
|
ctrl_info(ctrl, "Use INTx for the hotplug controller\n"); |
|
} else { |
|
pci_set_master(pdev); |
|
} |
|
|
|
rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, |
|
MY_NAME, (void *)ctrl); |
|
ctrl_dbg(ctrl, "request_irq %d (returns %d)\n", |
|
ctrl->pci_dev->irq, rc); |
|
if (rc) { |
|
ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n", |
|
ctrl->pci_dev->irq); |
|
goto abort_iounmap; |
|
} |
|
} |
|
ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); |
|
|
|
shpc_get_max_bus_speed(ctrl); |
|
shpc_get_cur_bus_speed(ctrl); |
|
|
|
/* |
|
* Unmask all event interrupts of all slots |
|
*/ |
|
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
|
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
|
ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
|
hp_slot, slot_reg); |
|
slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
|
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | |
|
CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); |
|
shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); |
|
} |
|
if (!shpchp_poll_mode) { |
|
/* Unmask all general input interrupts and SERR */ |
|
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
|
tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | |
|
SERR_INTR_RSVDZ_MASK); |
|
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
|
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
|
ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
|
} |
|
|
|
return 0; |
|
|
|
/* We end up here for the many possible ways to fail this API. */ |
|
abort_iounmap: |
|
iounmap(ctrl->creg); |
|
abort: |
|
return rc; |
|
}
|
|
|