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541 lines
14 KiB
541 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* This file is part of wl1251 |
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* |
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* Copyright (C) 2008 Nokia Corporation |
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*/ |
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|
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#include <linux/slab.h> |
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#include "reg.h" |
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#include "boot.h" |
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#include "io.h" |
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#include "spi.h" |
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#include "event.h" |
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#include "acx.h" |
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void wl1251_boot_target_enable_interrupts(struct wl1251 *wl) |
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{ |
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wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask)); |
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wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL); |
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} |
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int wl1251_boot_soft_reset(struct wl1251 *wl) |
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{ |
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unsigned long timeout; |
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u32 boot_data; |
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/* perform soft reset */ |
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wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT); |
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/* SOFT_RESET is self clearing */ |
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timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME); |
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while (1) { |
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boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET); |
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wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data); |
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if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0) |
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break; |
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if (time_after(jiffies, timeout)) { |
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/* 1.2 check pWhalBus->uSelfClearTime if the |
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* timeout was reached */ |
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wl1251_error("soft reset timeout"); |
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return -1; |
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} |
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udelay(SOFT_RESET_STALL_TIME); |
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} |
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/* disable Rx/Tx */ |
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wl1251_reg_write32(wl, ENABLE, 0x0); |
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/* disable auto calibration on start*/ |
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wl1251_reg_write32(wl, SPARE_A2, 0xffff); |
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return 0; |
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} |
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int wl1251_boot_init_seq(struct wl1251 *wl) |
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{ |
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u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq; |
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/* |
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* col #1: INTEGER_DIVIDER |
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* col #2: FRACTIONAL_DIVIDER |
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* col #3: ATTN_BB |
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* col #4: ALPHA_BB |
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* col #5: STOP_TIME_BB |
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* col #6: BB_PLL_LOOP_FILTER |
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*/ |
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static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = { |
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{ 83, 87381, 0xB, 5, 0xF00, 3}, /* REF_FREQ_19_2*/ |
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{ 61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/ |
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{ 41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/ |
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{ 40, 0, 0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/ |
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{ 47, 162280, 0xC, 6, 0x2760, 1} /* REF_FREQ_33_6 */ |
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}; |
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/* read NVS params */ |
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scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6); |
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wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6); |
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/* read ELP_CMD */ |
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elp_cmd = wl1251_reg_read32(wl, ELP_CMD); |
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wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd); |
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/* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */ |
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ref_freq = scr_pad6 & 0x000000FF; |
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wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq); |
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wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9); |
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/* |
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* PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME) |
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*/ |
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wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6); |
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/* |
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* set the clock detect feature to work in the restart wu procedure |
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* (ELP_CFG_MODE[14]) and Select the clock source type |
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* (ELP_CFG_MODE[13:12]) |
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*/ |
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tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000; |
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wl1251_reg_write32(wl, ELP_CFG_MODE, tmp); |
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/* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */ |
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elp_cmd |= 0x00000040; |
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wl1251_reg_write32(wl, ELP_CMD, elp_cmd); |
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/* PG 1.2: Set the BB PLL stable time to be 1000usec |
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* (PLL_STABLE_TIME) */ |
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wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20); |
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/* PG 1.2: read clock request time */ |
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init_data = wl1251_reg_read32(wl, CLK_REQ_TIME); |
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/* |
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* PG 1.2: set the clock request time to be ref_clk_settling_time - |
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* 1ms = 4ms |
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*/ |
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if (init_data > 0x21) |
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tmp = init_data - 0x21; |
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else |
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tmp = 0; |
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wl1251_reg_write32(wl, CLK_REQ_TIME, tmp); |
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/* set BB PLL configurations in RF AFE */ |
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wl1251_reg_write32(wl, 0x003058cc, 0x4B5); |
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/* set RF_AFE_REG_5 */ |
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wl1251_reg_write32(wl, 0x003058d4, 0x50); |
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/* set RF_AFE_CTRL_REG_2 */ |
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wl1251_reg_write32(wl, 0x00305948, 0x11c001); |
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/* |
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* change RF PLL and BB PLL divider for VCO clock and adjust VCO |
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* bais current(RF_AFE_REG_13) |
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*/ |
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wl1251_reg_write32(wl, 0x003058f4, 0x1e); |
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/* set BB PLL configurations */ |
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tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000; |
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wl1251_reg_write32(wl, 0x00305840, tmp); |
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/* set fractional divider according to Appendix C-BB PLL |
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* Calculations |
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*/ |
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tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER]; |
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wl1251_reg_write32(wl, 0x00305844, tmp); |
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/* set the initial data for the sigma delta */ |
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wl1251_reg_write32(wl, 0x00305848, 0x3039); |
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/* |
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* set the accumulator attenuation value, calibration loop1 |
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* (alpha), calibration loop2 (beta), calibration loop3 (gamma) and |
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* the VCO gain |
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*/ |
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tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) | |
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(LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1; |
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wl1251_reg_write32(wl, 0x00305854, tmp); |
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/* |
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* set the calibration stop time after holdoff time expires and set |
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* settling time HOLD_OFF_TIME_BB |
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*/ |
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tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000; |
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wl1251_reg_write32(wl, 0x00305858, tmp); |
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/* |
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* set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL |
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* constant leakage current to linearize PFD to 0uA - |
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* BB_ILOOPF[7:3] |
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*/ |
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tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030; |
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wl1251_reg_write32(wl, 0x003058f8, tmp); |
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/* |
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* set regulator output voltage for n divider to |
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* 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2], |
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* set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB |
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* PLL auto-call to normal mode- BB_CALGAIN_3DB[8] |
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*/ |
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wl1251_reg_write32(wl, 0x003058f0, 0x29); |
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/* enable restart wakeup sequence (ELP_CMD[0]) */ |
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wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1); |
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/* restart sequence completed */ |
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udelay(2000); |
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return 0; |
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} |
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static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag) |
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{ |
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u32 cpu_ctrl; |
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/* 10.5.0 run the firmware (I) */ |
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cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL); |
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/* 10.5.1 run the firmware (II) */ |
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cpu_ctrl &= ~flag; |
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wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); |
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} |
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int wl1251_boot_run_firmware(struct wl1251 *wl) |
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{ |
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int loop, ret; |
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u32 chip_id, acx_intr; |
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wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT); |
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chip_id = wl1251_reg_read32(wl, CHIP_ID_B); |
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wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id); |
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if (chip_id != wl->chip_id) { |
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wl1251_error("chip id doesn't match after firmware boot"); |
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return -EIO; |
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} |
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/* wait for init to complete */ |
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loop = 0; |
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while (loop++ < INIT_LOOP) { |
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udelay(INIT_LOOP_DELAY); |
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acx_intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); |
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if (acx_intr == 0xffffffff) { |
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wl1251_error("error reading hardware complete " |
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"init indication"); |
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return -EIO; |
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} |
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/* check that ACX_INTR_INIT_COMPLETE is enabled */ |
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else if (acx_intr & WL1251_ACX_INTR_INIT_COMPLETE) { |
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wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK, |
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WL1251_ACX_INTR_INIT_COMPLETE); |
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break; |
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} |
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} |
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if (loop > INIT_LOOP) { |
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wl1251_error("timeout waiting for the hardware to " |
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"complete initialization"); |
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return -EIO; |
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} |
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/* get hardware config command mail box */ |
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wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR); |
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/* get hardware config event mail box */ |
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wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR); |
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/* set the working partition to its "running" mode offset */ |
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wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START, |
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WL1251_PART_WORK_MEM_SIZE, |
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WL1251_PART_WORK_REG_START, |
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WL1251_PART_WORK_REG_SIZE); |
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wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x", |
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wl->cmd_box_addr, wl->event_box_addr); |
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wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver)); |
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/* |
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* in case of full asynchronous mode the firmware event must be |
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* ready to receive event from the command mailbox |
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*/ |
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/* enable gpio interrupts */ |
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wl1251_enable_interrupts(wl); |
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/* Enable target's interrupts */ |
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wl->intr_mask = WL1251_ACX_INTR_RX0_DATA | |
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WL1251_ACX_INTR_RX1_DATA | |
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WL1251_ACX_INTR_TX_RESULT | |
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WL1251_ACX_INTR_EVENT_A | |
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WL1251_ACX_INTR_EVENT_B | |
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WL1251_ACX_INTR_INIT_COMPLETE; |
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wl1251_boot_target_enable_interrupts(wl); |
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wl->event_mask = SCAN_COMPLETE_EVENT_ID | BSS_LOSE_EVENT_ID | |
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SYNCHRONIZATION_TIMEOUT_EVENT_ID | |
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ROAMING_TRIGGER_LOW_RSSI_EVENT_ID | |
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ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID | |
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REGAINED_BSS_EVENT_ID | BT_PTA_SENSE_EVENT_ID | |
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BT_PTA_PREDICTION_EVENT_ID | JOIN_EVENT_COMPLETE_ID | |
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PS_REPORT_EVENT_ID; |
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ret = wl1251_event_unmask(wl); |
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if (ret < 0) { |
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wl1251_error("EVENT mask setting failed"); |
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return ret; |
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} |
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wl1251_event_mbox_config(wl); |
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/* firmware startup completed */ |
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return 0; |
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} |
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static int wl1251_boot_upload_firmware(struct wl1251 *wl) |
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{ |
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int addr, chunk_num, partition_limit; |
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size_t fw_data_len, len; |
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u8 *p, *buf; |
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/* whal_FwCtrl_LoadFwImageSm() */ |
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wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x", |
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wl1251_reg_read32(wl, CHIP_ID_B)); |
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/* 10.0 check firmware length and set partition */ |
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fw_data_len = (wl->fw[4] << 24) | (wl->fw[5] << 16) | |
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(wl->fw[6] << 8) | (wl->fw[7]); |
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wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len, |
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CHUNK_SIZE); |
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if ((fw_data_len % 4) != 0) { |
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wl1251_error("firmware length not multiple of four"); |
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return -EIO; |
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} |
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buf = kmalloc(CHUNK_SIZE, GFP_KERNEL); |
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if (!buf) { |
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wl1251_error("allocation for firmware upload chunk failed"); |
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return -ENOMEM; |
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} |
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wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START, |
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WL1251_PART_DOWN_MEM_SIZE, |
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WL1251_PART_DOWN_REG_START, |
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WL1251_PART_DOWN_REG_SIZE); |
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/* 10.1 set partition limit and chunk num */ |
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chunk_num = 0; |
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partition_limit = WL1251_PART_DOWN_MEM_SIZE; |
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while (chunk_num < fw_data_len / CHUNK_SIZE) { |
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/* 10.2 update partition, if needed */ |
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addr = WL1251_PART_DOWN_MEM_START + |
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(chunk_num + 2) * CHUNK_SIZE; |
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if (addr > partition_limit) { |
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addr = WL1251_PART_DOWN_MEM_START + |
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chunk_num * CHUNK_SIZE; |
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partition_limit = chunk_num * CHUNK_SIZE + |
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WL1251_PART_DOWN_MEM_SIZE; |
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wl1251_set_partition(wl, |
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addr, |
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WL1251_PART_DOWN_MEM_SIZE, |
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WL1251_PART_DOWN_REG_START, |
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WL1251_PART_DOWN_REG_SIZE); |
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} |
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/* 10.3 upload the chunk */ |
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addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE; |
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p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE; |
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wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", |
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p, addr); |
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/* need to copy the chunk for dma */ |
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len = CHUNK_SIZE; |
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memcpy(buf, p, len); |
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wl1251_mem_write(wl, addr, buf, len); |
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chunk_num++; |
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} |
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/* 10.4 upload the last chunk */ |
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addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE; |
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p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE; |
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/* need to copy the chunk for dma */ |
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len = fw_data_len % CHUNK_SIZE; |
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memcpy(buf, p, len); |
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wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x", |
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len, p, addr); |
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wl1251_mem_write(wl, addr, buf, len); |
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kfree(buf); |
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return 0; |
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} |
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static int wl1251_boot_upload_nvs(struct wl1251 *wl) |
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{ |
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size_t nvs_len, nvs_bytes_written, burst_len; |
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int nvs_start, i; |
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u32 dest_addr, val; |
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u8 *nvs_ptr, *nvs; |
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nvs = wl->nvs; |
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if (nvs == NULL) |
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return -ENODEV; |
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nvs_ptr = nvs; |
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nvs_len = wl->nvs_len; |
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nvs_start = wl->fw_len; |
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|
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/* |
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* Layout before the actual NVS tables: |
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* 1 byte : burst length. |
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* 2 bytes: destination address. |
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* n bytes: data to burst copy. |
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* |
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* This is ended by a 0 length, then the NVS tables. |
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*/ |
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while (nvs_ptr[0]) { |
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burst_len = nvs_ptr[0]; |
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dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8)); |
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|
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/* We move our pointer to the data */ |
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nvs_ptr += 3; |
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|
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for (i = 0; i < burst_len; i++) { |
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val = (nvs_ptr[0] | (nvs_ptr[1] << 8) |
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| (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24)); |
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|
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wl1251_debug(DEBUG_BOOT, |
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"nvs burst write 0x%x: 0x%x", |
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dest_addr, val); |
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wl1251_mem_write32(wl, dest_addr, val); |
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|
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nvs_ptr += 4; |
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dest_addr += 4; |
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} |
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} |
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|
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/* |
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* We've reached the first zero length, the first NVS table |
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* is 7 bytes further. |
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*/ |
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nvs_ptr += 7; |
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nvs_len -= nvs_ptr - nvs; |
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nvs_len = ALIGN(nvs_len, 4); |
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|
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/* Now we must set the partition correctly */ |
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wl1251_set_partition(wl, nvs_start, |
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WL1251_PART_DOWN_MEM_SIZE, |
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WL1251_PART_DOWN_REG_START, |
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WL1251_PART_DOWN_REG_SIZE); |
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|
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/* And finally we upload the NVS tables */ |
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nvs_bytes_written = 0; |
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while (nvs_bytes_written < nvs_len) { |
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val = (nvs_ptr[0] | (nvs_ptr[1] << 8) |
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| (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24)); |
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|
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wl1251_debug(DEBUG_BOOT, |
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"nvs write table 0x%x: 0x%x", |
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nvs_start, val); |
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wl1251_mem_write32(wl, nvs_start, val); |
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|
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nvs_ptr += 4; |
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nvs_bytes_written += 4; |
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nvs_start += 4; |
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} |
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|
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return 0; |
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} |
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|
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int wl1251_boot(struct wl1251 *wl) |
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{ |
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int ret = 0, minor_minor_e2_ver; |
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u32 tmp, boot_data; |
|
|
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/* halt embedded ARM CPU while loading firmware */ |
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wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT); |
|
|
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ret = wl1251_boot_soft_reset(wl); |
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if (ret < 0) |
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goto out; |
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|
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/* 2. start processing NVS file */ |
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if (wl->use_eeprom) { |
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wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR); |
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/* Wait for EEPROM NVS burst read to complete */ |
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msleep(40); |
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wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM); |
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} else { |
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ret = wl1251_boot_upload_nvs(wl); |
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if (ret < 0) |
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goto out; |
|
|
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/* write firmware's last address (ie. it's length) to |
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* ACX_EEPROMLESS_IND_REG */ |
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wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len); |
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} |
|
|
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/* 6. read the EEPROM parameters */ |
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tmp = wl1251_reg_read32(wl, SCR_PAD2); |
|
|
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/* 7. read bootdata */ |
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wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8; |
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wl->boot_attr.major = (tmp & 0x00FF0000) >> 16; |
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tmp = wl1251_reg_read32(wl, SCR_PAD3); |
|
|
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/* 8. check bootdata and call restart sequence */ |
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wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16; |
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minor_minor_e2_ver = (tmp & 0xFF000000) >> 24; |
|
|
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wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x " |
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"minorE2Ver 0x%x minor_minor_e2_ver 0x%x", |
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wl->boot_attr.radio_type, wl->boot_attr.major, |
|
wl->boot_attr.minor, minor_minor_e2_ver); |
|
|
|
ret = wl1251_boot_init_seq(wl); |
|
if (ret < 0) |
|
goto out; |
|
|
|
/* 9. NVS processing done */ |
|
boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL); |
|
|
|
wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data); |
|
|
|
/* 10. check that ECPU_CONTROL_HALT bits are set in |
|
* pWhalBus->uBootData and start uploading firmware |
|
*/ |
|
if ((boot_data & ECPU_CONTROL_HALT) == 0) { |
|
wl1251_error("boot failed, ECPU_CONTROL_HALT not set"); |
|
ret = -EIO; |
|
goto out; |
|
} |
|
|
|
ret = wl1251_boot_upload_firmware(wl); |
|
if (ret < 0) |
|
goto out; |
|
|
|
/* 10.5 start firmware */ |
|
ret = wl1251_boot_run_firmware(wl); |
|
if (ret < 0) |
|
goto out; |
|
|
|
out: |
|
return ret; |
|
}
|
|
|