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193 lines
5.9 KiB
193 lines
5.9 KiB
/** |
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* Copyright (c) 2014 Redpine Signals Inc. |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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#ifndef __RSI_BOOTPARAMS_HEADER_H__ |
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#define __RSI_BOOTPARAMS_HEADER_H__ |
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#define CRYSTAL_GOOD_TIME BIT(0) |
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#define BOOTUP_MODE_INFO BIT(1) |
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#define WIFI_TAPLL_CONFIGS BIT(5) |
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#define WIFI_PLL960_CONFIGS BIT(6) |
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#define WIFI_AFEPLL_CONFIGS BIT(7) |
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#define WIFI_SWITCH_CLK_CONFIGS BIT(8) |
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#define TA_PLL_M_VAL_20 9 |
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#define TA_PLL_N_VAL_20 0 |
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#define TA_PLL_P_VAL_20 4 |
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#define PLL960_M_VAL_20 0x14 |
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#define PLL960_N_VAL_20 0 |
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#define PLL960_P_VAL_20 5 |
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#define UMAC_CLK_40MHZ 80 |
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#define TA_PLL_M_VAL_40 9 |
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#define TA_PLL_N_VAL_40 0 |
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#define TA_PLL_P_VAL_40 4 |
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#define PLL960_M_VAL_40 0x14 |
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#define PLL960_N_VAL_40 0 |
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#define PLL960_P_VAL_40 5 |
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#define UMAC_CLK_20BW \ |
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(((TA_PLL_M_VAL_20 + 1) * 40) / \ |
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((TA_PLL_N_VAL_20 + 1) * (TA_PLL_P_VAL_20 + 1))) |
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#define VALID_20 \ |
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(WIFI_TAPLL_CONFIGS | WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | \ |
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WIFI_SWITCH_CLK_CONFIGS | BOOTUP_MODE_INFO | CRYSTAL_GOOD_TIME) |
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#define UMAC_CLK_40BW \ |
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(((TA_PLL_M_VAL_40 + 1) * 40) / \ |
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((TA_PLL_N_VAL_40 + 1) * (TA_PLL_P_VAL_40 + 1))) |
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#define VALID_40 \ |
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(WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | WIFI_SWITCH_CLK_CONFIGS | \ |
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WIFI_TAPLL_CONFIGS | CRYSTAL_GOOD_TIME | BOOTUP_MODE_INFO) |
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/* structure to store configs related to TAPLL programming */ |
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struct tapll_info { |
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__le16 pll_reg_1; |
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__le16 pll_reg_2; |
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} __packed; |
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/* structure to store configs related to PLL960 programming */ |
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struct pll960_info { |
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__le16 pll_reg_1; |
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__le16 pll_reg_2; |
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__le16 pll_reg_3; |
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} __packed; |
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/* structure to store configs related to AFEPLL programming */ |
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struct afepll_info { |
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__le16 pll_reg; |
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} __packed; |
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/* structure to store configs related to pll configs */ |
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struct pll_config { |
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struct tapll_info tapll_info_g; |
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struct pll960_info pll960_info_g; |
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struct afepll_info afepll_info_g; |
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} __packed; |
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struct pll_config_9116 { |
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__le16 pll_ctrl_set_reg; |
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__le16 pll_ctrl_clr_reg; |
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__le16 pll_modem_conig_reg; |
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__le16 soc_clk_config_reg; |
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__le16 adc_dac_strm1_config_reg; |
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__le16 adc_dac_strm2_config_reg; |
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} __packed; |
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/* structure to store configs related to UMAC clk programming */ |
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struct switch_clk { |
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__le16 switch_clk_info; |
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/* If switch_bbp_lmac_clk_reg is set then this value will be programmed |
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* into reg |
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*/ |
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__le16 bbp_lmac_clk_reg_val; |
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/* if switch_umac_clk is set then this value will be programmed */ |
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__le16 umac_clock_reg_config; |
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/* if switch_qspi_clk is set then this value will be programmed */ |
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__le16 qspi_uart_clock_reg_config; |
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} __packed; |
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#define RSI_SWITCH_TASS_CLK BIT(0) |
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#define RSI_SWITCH_QSPI_CLK BIT(1) |
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#define RSI_SWITCH_SLP_CLK_2_32 BIT(2) |
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#define RSI_SWITCH_WLAN_BBP_LMAC_CLK_REG BIT(3) |
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#define RSI_SWITCH_ZBBT_BBP_LMAC_CLK_REG BIT(4) |
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#define RSI_SWITCH_BBP_LMAC_CLK_REG BIT(5) |
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#define RSI_MODEM_CLK_160MHZ BIT(6) |
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struct switch_clk_9116 { |
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__le32 switch_clk_info; |
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__le32 tass_clock_reg; |
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__le32 wlan_bbp_lmac_clk_reg_val; |
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__le32 zbbt_bbp_lmac_clk_reg_val; |
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__le32 bbp_lmac_clk_en_val; |
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} __packed; |
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struct device_clk_info { |
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struct pll_config pll_config_g; |
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struct switch_clk switch_clk_g; |
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} __packed; |
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struct device_clk_info_9116 { |
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struct pll_config_9116 pll_config_9116_g; |
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struct switch_clk_9116 switch_clk_9116_g; |
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} __packed; |
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struct bootup_params { |
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__le16 magic_number; |
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__le16 crystal_good_time; |
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__le32 valid; |
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__le32 reserved_for_valids; |
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__le16 bootup_mode_info; |
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/* configuration used for digital loop back */ |
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__le16 digital_loop_back_params; |
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__le16 rtls_timestamp_en; |
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__le16 host_spi_intr_cfg; |
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struct device_clk_info device_clk_info[3]; |
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/* ulp buckboost wait time */ |
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__le32 buckboost_wakeup_cnt; |
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/* pmu wakeup wait time & WDT EN info */ |
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__le16 pmu_wakeup_wait; |
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u8 shutdown_wait_time; |
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/* Sleep clock source selection */ |
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u8 pmu_slp_clkout_sel; |
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/* WDT programming values */ |
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__le32 wdt_prog_value; |
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/* WDT soc reset delay */ |
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__le32 wdt_soc_rst_delay; |
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/* dcdc modes configs */ |
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__le32 dcdc_operation_mode; |
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__le32 soc_reset_wait_cnt; |
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__le32 waiting_time_at_fresh_sleep; |
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__le32 max_threshold_to_avoid_sleep; |
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u8 beacon_resedue_alg_en; |
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} __packed; |
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struct bootup_params_9116 { |
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__le16 magic_number; |
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#define LOADED_TOKEN 0x5AA5 /* Bootup params are installed by host |
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* or OTP/FLASH (Bootloader) |
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*/ |
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#define ROM_TOKEN 0x55AA /* Bootup params are taken from ROM |
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* itself in MCU mode. |
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*/ |
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__le16 crystal_good_time; |
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__le32 valid; |
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__le32 reserved_for_valids; |
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__le16 bootup_mode_info; |
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#define BT_COEXIST BIT(0) |
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#define BOOTUP_MODE (BIT(2) | BIT(1)) |
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#define CUR_DEV_MODE_9116 (bootup_params_9116.bootup_mode_info >> 1) |
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__le16 digital_loop_back_params; |
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__le16 rtls_timestamp_en; |
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__le16 host_spi_intr_cfg; |
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struct device_clk_info_9116 device_clk_info_9116[1]; |
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__le32 buckboost_wakeup_cnt; |
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__le16 pmu_wakeup_wait; |
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u8 shutdown_wait_time; |
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u8 pmu_slp_clkout_sel; |
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__le32 wdt_prog_value; |
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__le32 wdt_soc_rst_delay; |
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__le32 dcdc_operation_mode; |
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__le32 soc_reset_wait_cnt; |
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__le32 waiting_time_at_fresh_sleep; |
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__le32 max_threshold_to_avoid_sleep; |
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u8 beacon_resedue_alg_en; |
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} __packed; |
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#endif
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