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522 lines
22 KiB
522 lines
22 KiB
/****************************************************************************** |
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* |
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* This file is provided under a dual BSD/GPLv2 license. When using or |
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* redistributing this file, you may do so under either license. |
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* |
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* GPL LICENSE SUMMARY |
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* |
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* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of version 2 of the GNU General Public License as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
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* USA |
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* |
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* The full GNU General Public License is included in this distribution |
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* in the file called LICENSE.GPL. |
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* |
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* Contact Information: |
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* Intel Linux Wireless <[email protected]> |
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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* |
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* BSD LICENSE |
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* |
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* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* * Neither the name Intel Corporation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*****************************************************************************/ |
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#ifndef __il_prph_h__ |
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#define __il_prph_h__ |
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/* |
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* Registers in this file are internal, not PCI bus memory mapped. |
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* Driver accesses these via HBUS_TARG_PRPH_* registers. |
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*/ |
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#define PRPH_BASE (0x00000) |
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#define PRPH_END (0xFFFFF) |
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/* APMG (power management) constants */ |
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#define APMG_BASE (PRPH_BASE + 0x3000) |
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#define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) |
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#define APMG_CLK_EN_REG (APMG_BASE + 0x0004) |
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#define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) |
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#define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) |
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#define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) |
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#define APMG_RFKILL_REG (APMG_BASE + 0x0014) |
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#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) |
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#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) |
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#define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058) |
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#define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C) |
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#define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) |
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#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) |
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#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) |
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#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) |
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#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) |
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#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) |
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#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) |
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#define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */ |
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#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) |
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#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ |
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#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) |
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#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) |
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/** |
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* BSM (Bootstrap State Machine) |
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* |
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* The Bootstrap State Machine (BSM) stores a short bootstrap uCode program |
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* in special SRAM that does not power down when the embedded control |
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* processor is sleeping (e.g. for periodic power-saving shutdowns of radio). |
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* |
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* When powering back up after sleeps (or during initial uCode load), the BSM |
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* internally loads the short bootstrap program from the special SRAM into the |
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* embedded processor's instruction SRAM, and starts the processor so it runs |
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* the bootstrap program. |
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* |
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* This bootstrap program loads (via PCI busmaster DMA) instructions and data |
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* images for a uCode program from host DRAM locations. The host driver |
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* indicates DRAM locations and sizes for instruction and data images via the |
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* four BSM_DRAM_* registers. Once the bootstrap program loads the new program, |
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* the new program starts automatically. |
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* |
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* The uCode used for open-source drivers includes two programs: |
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* |
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* 1) Initialization -- performs hardware calibration and sets up some |
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* internal data, then notifies host via "initialize alive" notification |
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* (struct il_init_alive_resp) that it has completed all of its work. |
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* After signal from host, it then loads and starts the runtime program. |
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* The initialization program must be used when initially setting up the |
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* NIC after loading the driver. |
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* |
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* 2) Runtime/Protocol -- performs all normal runtime operations. This |
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* notifies host via "alive" notification (struct il_alive_resp) that it |
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* is ready to be used. |
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* |
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* When initializing the NIC, the host driver does the following procedure: |
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* |
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* 1) Load bootstrap program (instructions only, no data image for bootstrap) |
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* into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND |
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* |
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* 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction |
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* images in host DRAM. |
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* |
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* 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked: |
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* BSM_WR_MEM_SRC_REG = 0 |
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* BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND |
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* BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image |
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* |
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* 4) Load bootstrap into instruction SRAM: |
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* BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START |
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* |
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* 5) Wait for load completion: |
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* Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0 |
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* |
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* 6) Enable future boot loads whenever NIC's power management triggers it: |
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* BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN |
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* |
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* 7) Start the NIC by removing all reset bits: |
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* CSR_RESET = 0 |
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* |
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* The bootstrap uCode (already in instruction SRAM) loads initialization |
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* uCode. Initialization uCode performs data initialization, sends |
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* "initialize alive" notification to host, and waits for a signal from |
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* host to load runtime code. |
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* |
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* 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction |
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* images in host DRAM. The last register loaded must be the instruction |
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* byte count register ("1" in MSbit tells initialization uCode to load |
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* the runtime uCode): |
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* BSM_DRAM_INST_BYTECOUNT_REG = byte count | BSM_DRAM_INST_LOAD |
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* |
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* 5) Wait for "alive" notification, then issue normal runtime commands. |
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* |
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* Data caching during power-downs: |
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* |
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* Just before the embedded controller powers down (e.g for automatic |
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* power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA) |
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* a current snapshot of the embedded processor's data SRAM into host DRAM. |
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* This caches the data while the embedded processor's memory is powered down. |
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* Location and size are controlled by BSM_DRAM_DATA_* registers. |
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* |
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* NOTE: Instruction SRAM does not need to be saved, since that doesn't |
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* change during operation; the original image (from uCode distribution |
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* file) can be used for reload. |
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* |
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* When powering back up, the BSM loads the bootstrap program. Bootstrap looks |
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* at the BSM_DRAM_* registers, which now point to the runtime instruction |
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* image and the cached (modified) runtime data (*not* the initialization |
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* uCode). Bootstrap reloads these runtime images into SRAM, and restarts the |
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* uCode from where it left off before the power-down. |
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* |
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* NOTE: Initialization uCode does *not* run as part of the save/restore |
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* procedure. |
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* |
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* This save/restore method is mostly for autonomous power management during |
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* normal operation (result of C_POWER_TBL). Platform suspend/resume and |
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* RFKILL should use complete restarts (with total re-initialization) of uCode, |
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* allowing total shutdown (including BSM memory). |
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* |
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* Note that, during normal operation, the host DRAM that held the initial |
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* startup data for the runtime code is now being used as a backup data cache |
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* for modified data! If you need to completely re-initialize the NIC, make |
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* sure that you use the runtime data image from the uCode distribution file, |
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* not the modified/saved runtime data. You may want to store a separate |
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* "clean" runtime data image in DRAM to avoid disk reads of distribution file. |
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*/ |
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/* BSM bit fields */ |
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#define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */ |
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#define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup */ |
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#define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */ |
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/* BSM addresses */ |
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#define BSM_BASE (PRPH_BASE + 0x3400) |
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#define BSM_END (PRPH_BASE + 0x3800) |
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#define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */ |
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#define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */ |
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#define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */ |
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#define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */ |
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#define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */ |
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/* |
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* Pointers and size regs for bootstrap load and data SRAM save/restore. |
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* NOTE: 3945 pointers use bits 31:0 of DRAM address. |
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* 4965 pointers use bits 35:4 of DRAM address. |
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*/ |
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#define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090) |
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#define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094) |
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#define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098) |
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#define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C) |
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/* |
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* BSM special memory, stays powered on during power-save sleeps. |
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* Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1) |
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*/ |
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#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800) |
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#define BSM_SRAM_SIZE (1024) /* bytes */ |
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/* 3945 Tx scheduler registers */ |
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#define ALM_SCD_BASE (PRPH_BASE + 0x2E00) |
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#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000) |
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#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004) |
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#define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010) |
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#define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014) |
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#define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020) |
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#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C) |
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#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030) |
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/** |
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* Tx Scheduler |
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* |
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* The Tx Scheduler selects the next frame to be transmitted, choosing TFDs |
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* (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in |
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* host DRAM. It steers each frame's Tx command (which contains the frame |
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* data) into one of up to 7 prioritized Tx DMA FIFO channels within the |
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* device. A queue maps to only one (selectable by driver) Tx DMA channel, |
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* but one DMA channel may take input from several queues. |
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* |
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* Tx DMA FIFOs have dedicated purposes. For 4965, they are used as follows |
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* (cf. default_queue_to_tx_fifo in 4965.c): |
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* |
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* 0 -- EDCA BK (background) frames, lowest priority |
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* 1 -- EDCA BE (best effort) frames, normal priority |
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* 2 -- EDCA VI (video) frames, higher priority |
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* 3 -- EDCA VO (voice) and management frames, highest priority |
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* 4 -- Commands (e.g. RXON, etc.) |
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* 5 -- unused (HCCA) |
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* 6 -- unused (HCCA) |
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* 7 -- not used by driver (device-internal only) |
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* |
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* |
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* Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. |
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* In addition, driver can map the remaining queues to Tx DMA/FIFO |
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* channels 0-3 to support 11n aggregation via EDCA DMA channels. |
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* |
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* The driver sets up each queue to work in one of two modes: |
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* |
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* 1) Scheduler-Ack, in which the scheduler automatically supports a |
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* block-ack (BA) win of up to 64 TFDs. In this mode, each queue |
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* contains TFDs for a unique combination of Recipient Address (RA) |
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* and Traffic Identifier (TID), that is, traffic of a given |
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* Quality-Of-Service (QOS) priority, destined for a single station. |
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* |
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* In scheduler-ack mode, the scheduler keeps track of the Tx status of |
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* each frame within the BA win, including whether it's been transmitted, |
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* and whether it's been acknowledged by the receiving station. The device |
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* automatically processes block-acks received from the receiving STA, |
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* and reschedules un-acked frames to be retransmitted (successful |
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* Tx completion may end up being out-of-order). |
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* |
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* The driver must maintain the queue's Byte Count table in host DRAM |
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* (struct il4965_sched_queue_byte_cnt_tbl) for this mode. |
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* This mode does not support fragmentation. |
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* |
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* 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. |
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* The device may automatically retry Tx, but will retry only one frame |
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* at a time, until receiving ACK from receiving station, or reaching |
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* retry limit and giving up. |
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* |
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* The command queue (#4/#9) must use this mode! |
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* This mode does not require use of the Byte Count table in host DRAM. |
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* |
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* Driver controls scheduler operation via 3 means: |
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* 1) Scheduler registers |
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* 2) Shared scheduler data base in internal 4956 SRAM |
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* 3) Shared data in host DRAM |
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* |
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* Initialization: |
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* |
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* When loading, driver should allocate memory for: |
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* 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. |
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* 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory |
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* (1024 bytes for each queue). |
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* |
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* After receiving "Alive" response from uCode, driver must initialize |
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* the scheduler (especially for queue #4/#9, the command queue, otherwise |
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* the driver can't issue commands!): |
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*/ |
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/** |
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* Max Tx win size is the max number of contiguous TFDs that the scheduler |
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* can keep track of at one time when creating block-ack chains of frames. |
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* Note that "64" matches the number of ack bits in a block-ack packet. |
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* Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize |
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* IL49_SCD_CONTEXT_QUEUE_OFFSET(x) values. |
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*/ |
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#define SCD_WIN_SIZE 64 |
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#define SCD_FRAME_LIMIT 64 |
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/* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */ |
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#define IL49_SCD_START_OFFSET 0xa02c00 |
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/* |
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* 4965 tells driver SRAM address for internal scheduler structs via this reg. |
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* Value is valid only after "Alive" response from uCode. |
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*/ |
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#define IL49_SCD_SRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x0) |
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/* |
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* Driver may need to update queue-empty bits after changing queue's |
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* write and read pointers (idxes) during (re-)initialization (i.e. when |
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* scheduler is not tracking what's happening). |
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* Bit fields: |
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* 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit |
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* 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty |
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* NOTE: This register is not used by Linux driver. |
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*/ |
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#define IL49_SCD_EMPTY_BITS (IL49_SCD_START_OFFSET + 0x4) |
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/* |
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* Physical base address of array of byte count (BC) circular buffers (CBs). |
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* Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode. |
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* This register points to BC CB for queue 0, must be on 1024-byte boundary. |
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* Others are spaced by 1024 bytes. |
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* Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. |
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* (Index into a queue's BC CB) = (idx into queue's TFD CB) = (SSN & 0xff). |
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* Bit fields: |
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* 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned. |
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*/ |
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#define IL49_SCD_DRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x10) |
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/* |
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* Enables any/all Tx DMA/FIFO channels. |
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* Scheduler generates requests for only the active channels. |
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* Set this to 0xff to enable all 8 channels (normal usage). |
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* Bit fields: |
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* 7- 0: Enable (1), disable (0), one bit for each channel 0-7 |
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*/ |
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#define IL49_SCD_TXFACT (IL49_SCD_START_OFFSET + 0x1c) |
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/* |
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* Queue (x) Write Pointers (idxes, really!), one for each Tx queue. |
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* Initialized and updated by driver as new TFDs are added to queue. |
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* NOTE: If using Block Ack, idx must correspond to frame's |
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* Start Sequence Number; idx = (SSN & 0xff) |
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* NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses? |
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*/ |
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#define IL49_SCD_QUEUE_WRPTR(x) (IL49_SCD_START_OFFSET + 0x24 + (x) * 4) |
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/* |
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* Queue (x) Read Pointers (idxes, really!), one for each Tx queue. |
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* For FIFO mode, idx indicates next frame to transmit. |
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* For Scheduler-ACK mode, idx indicates first frame in Tx win. |
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* Initialized by driver, updated by scheduler. |
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*/ |
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#define IL49_SCD_QUEUE_RDPTR(x) (IL49_SCD_START_OFFSET + 0x64 + (x) * 4) |
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/* |
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* Select which queues work in chain mode (1) vs. not (0). |
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* Use chain mode to build chains of aggregated frames. |
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* Bit fields: |
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* 31-16: Reserved |
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* 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time |
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* NOTE: If driver sets up queue for chain mode, it should be also set up |
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* Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x). |
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*/ |
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#define IL49_SCD_QUEUECHAIN_SEL (IL49_SCD_START_OFFSET + 0xd0) |
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/* |
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* Select which queues interrupt driver when scheduler increments |
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* a queue's read pointer (idx). |
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* Bit fields: |
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* 31-16: Reserved |
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* 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled |
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* NOTE: This functionality is apparently a no-op; driver relies on interrupts |
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* from Rx queue to read Tx command responses and update Tx queues. |
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*/ |
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#define IL49_SCD_INTERRUPT_MASK (IL49_SCD_START_OFFSET + 0xe4) |
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/* |
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* Queue search status registers. One for each queue. |
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* Sets up queue mode and assigns queue to Tx DMA channel. |
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* Bit fields: |
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* 19-10: Write mask/enable bits for bits 0-9 |
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* 9: Driver should init to "0" |
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* 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0). |
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* Driver should init to "1" for aggregation mode, or "0" otherwise. |
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* 7-6: Driver should init to "0" |
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* 5: Window Size Left; indicates whether scheduler can request |
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* another TFD, based on win size, etc. Driver should init |
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* this bit to "1" for aggregation mode, or "0" for non-agg. |
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* 4-1: Tx FIFO to use (range 0-7). |
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* 0: Queue is active (1), not active (0). |
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* Other bits should be written as "0" |
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* |
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* NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled |
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* via SCD_QUEUECHAIN_SEL. |
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*/ |
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#define IL49_SCD_QUEUE_STATUS_BITS(x)\ |
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(IL49_SCD_START_OFFSET + 0x104 + (x) * 4) |
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|
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/* Bit field positions */ |
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#define IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE (0) |
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#define IL49_SCD_QUEUE_STTS_REG_POS_TXF (1) |
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#define IL49_SCD_QUEUE_STTS_REG_POS_WSL (5) |
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#define IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) |
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|
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/* Write masks */ |
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#define IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) |
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#define IL49_SCD_QUEUE_STTS_REG_MSK (0x0007FC00) |
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/** |
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* 4965 internal SRAM structures for scheduler, shared with driver ... |
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* |
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* Driver should clear and initialize the following areas after receiving |
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* "Alive" response from 4965 uCode, i.e. after initial |
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* uCode load, or after a uCode load done for error recovery: |
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* |
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* SCD_CONTEXT_DATA_OFFSET (size 128 bytes) |
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* SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes) |
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* SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) |
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* |
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* Driver accesses SRAM via HBUS_TARG_MEM_* registers. |
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* Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR. |
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* All OFFSET values must be added to this base address. |
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*/ |
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|
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/* |
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* Queue context. One 8-byte entry for each of 16 queues. |
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* |
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* Driver should clear this entire area (size 0x80) to 0 after receiving |
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* "Alive" notification from uCode. Additionally, driver should init |
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* each queue's entry as follows: |
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* |
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* LS Dword bit fields: |
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* 0-06: Max Tx win size for Scheduler-ACK. Driver should init to 64. |
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* |
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* MS Dword bit fields: |
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* 16-22: Frame limit. Driver should init to 10 (0xa). |
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* |
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* Driver should init all other bits to 0. |
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* |
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* Init must be done after driver receives "Alive" response from 4965 uCode, |
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* and when setting up queue for aggregation. |
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*/ |
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#define IL49_SCD_CONTEXT_DATA_OFFSET 0x380 |
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#define IL49_SCD_CONTEXT_QUEUE_OFFSET(x) \ |
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(IL49_SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) |
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|
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#define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) |
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#define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) |
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#define IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) |
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#define IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) |
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|
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/* |
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* Tx Status Bitmap |
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* |
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* Driver should clear this entire area (size 0x100) to 0 after receiving |
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* "Alive" notification from uCode. Area is used only by device itself; |
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* no other support (besides clearing) is required from driver. |
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*/ |
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#define IL49_SCD_TX_STTS_BITMAP_OFFSET 0x400 |
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|
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/* |
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* RAxTID to queue translation mapping. |
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* |
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* When queue is in Scheduler-ACK mode, frames placed in a that queue must be |
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* for only one combination of receiver address (RA) and traffic ID (TID), i.e. |
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* one QOS priority level destined for one station (for this wireless link, |
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* not final destination). The SCD_TRANSLATE_TBL area provides 16 16-bit |
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* mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK |
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* mode, the device ignores the mapping value. |
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* |
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* Bit fields, for each 16-bit map: |
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* 15-9: Reserved, set to 0 |
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* 8-4: Index into device's station table for recipient station |
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* 3-0: Traffic ID (tid), range 0-15 |
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* |
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* Driver should clear this entire area (size 32 bytes) to 0 after receiving |
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* "Alive" notification from uCode. To update a 16-bit map value, driver |
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* must read a dword-aligned value from device SRAM, replace the 16-bit map |
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* value of interest, and write the dword value back into device SRAM. |
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*/ |
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#define IL49_SCD_TRANSLATE_TBL_OFFSET 0x500 |
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|
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/* Find translation table dword to read/write for given queue */ |
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#define IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ |
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((IL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) |
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|
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#define IL_SCD_TXFIFO_POS_TID (0) |
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#define IL_SCD_TXFIFO_POS_RA (4) |
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#define IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) |
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|
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/*********************** END TX SCHEDULER *************************************/ |
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|
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#endif /* __il_prph_h__ */
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