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419 lines
18 KiB
419 lines
18 KiB
/****************************************************************************** |
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* |
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* This file is provided under a dual BSD/GPLv2 license. When using or |
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* redistributing this file, you may do so under either license. |
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* |
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* GPL LICENSE SUMMARY |
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* |
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* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of version 2 of the GNU General Public License as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
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* USA |
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* |
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* The full GNU General Public License is included in this distribution |
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* in the file called LICENSE.GPL. |
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* |
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* Contact Information: |
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* Intel Linux Wireless <[email protected]> |
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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* |
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* BSD LICENSE |
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* |
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* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* * Neither the name Intel Corporation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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*****************************************************************************/ |
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#ifndef __il_csr_h__ |
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#define __il_csr_h__ |
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/* |
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* CSR (control and status registers) |
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* |
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* CSR registers are mapped directly into PCI bus space, and are accessible |
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* whenever platform supplies power to device, even when device is in |
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* low power states due to driver-invoked device resets |
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* (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. |
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* |
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* Use _il_wr() and _il_rd() family to access these registers; |
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* these provide simple PCI bus access, without waking up the MAC. |
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* Do not use il_wr() family for these registers; |
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* no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. |
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* The MAC (uCode processor, etc.) does not need to be powered up for accessing |
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* the CSR registers. |
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* |
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* NOTE: Device does need to be awake in order to read this memory |
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* via CSR_EEPROM register |
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*/ |
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#define CSR_BASE (0x000) |
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#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ |
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#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ |
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#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ |
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#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ |
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#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */ |
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#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ |
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#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */ |
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#define CSR_GP_CNTRL (CSR_BASE+0x024) |
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/* 2nd byte of CSR_INT_COALESCING, not accessible via _il_wr()! */ |
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#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) |
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/* |
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* Hardware revision info |
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* Bit fields: |
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* 31-8: Reserved |
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* 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions |
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* 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D |
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* 1-0: "Dash" (-) value, as in A-1, etc. |
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* |
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* NOTE: Revision step affects calculation of CCK txpower for 4965. |
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* NOTE: See also CSR_HW_REV_WA_REG (work-around for bug in 4965). |
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*/ |
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#define CSR_HW_REV (CSR_BASE+0x028) |
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/* |
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* EEPROM memory reads |
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* |
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* NOTE: Device must be awake, initialized via apm_ops.init(), |
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* in order to read. |
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*/ |
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#define CSR_EEPROM_REG (CSR_BASE+0x02c) |
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#define CSR_EEPROM_GP (CSR_BASE+0x030) |
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#define CSR_GIO_REG (CSR_BASE+0x03C) |
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#define CSR_GP_UCODE_REG (CSR_BASE+0x048) |
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#define CSR_GP_DRIVER_REG (CSR_BASE+0x050) |
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/* |
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* UCODE-DRIVER GP (general purpose) mailbox registers. |
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* SET/CLR registers set/clear bit(s) if "1" is written. |
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*/ |
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#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) |
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#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) |
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#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) |
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#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) |
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#define CSR_LED_REG (CSR_BASE+0x094) |
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#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) |
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/* GIO Chicken Bits (PCI Express bus link power management) */ |
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#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |
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/* Analog phase-lock-loop configuration */ |
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#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) |
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/* |
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* CSR Hardware Revision Workaround Register. Indicates hardware rev; |
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* "step" determines CCK backoff for txpower calculation. Used for 4965 only. |
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* See also CSR_HW_REV register. |
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* Bit fields: |
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* 3-2: 0 = A, 1 = B, 2 = C, 3 = D step |
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* 1-0: "Dash" (-) value, as in C-1, etc. |
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*/ |
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#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) |
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#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) |
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#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) |
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/* Bits for CSR_HW_IF_CONFIG_REG */ |
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#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) |
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#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) |
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#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) |
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#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) |
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#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100) |
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#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200) |
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#define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) |
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#define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) |
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#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) |
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#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) |
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#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) |
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#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) |
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#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ |
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#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ |
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#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ |
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#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int */ |
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#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec */ |
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/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), |
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* acknowledged (reset) by host writing "1" to flagged bits. */ |
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#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ |
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#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ |
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#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ |
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#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ |
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#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ |
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#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ |
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#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ |
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#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ |
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#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */ |
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#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ |
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#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ |
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#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ |
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CSR_INT_BIT_HW_ERR | \ |
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CSR_INT_BIT_FH_TX | \ |
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CSR_INT_BIT_SW_ERR | \ |
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CSR_INT_BIT_RF_KILL | \ |
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CSR_INT_BIT_SW_RX | \ |
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CSR_INT_BIT_WAKEUP | \ |
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CSR_INT_BIT_ALIVE) |
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/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ |
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#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ |
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#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ |
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#define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */ |
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#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ |
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#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ |
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#define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */ |
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#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ |
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#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ |
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#define CSR39_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ |
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CSR39_FH_INT_BIT_RX_CHNL2 | \ |
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CSR_FH_INT_BIT_RX_CHNL1 | \ |
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CSR_FH_INT_BIT_RX_CHNL0) |
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#define CSR39_FH_INT_TX_MASK (CSR39_FH_INT_BIT_TX_CHNL6 | \ |
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CSR_FH_INT_BIT_TX_CHNL1 | \ |
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CSR_FH_INT_BIT_TX_CHNL0) |
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#define CSR49_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ |
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CSR_FH_INT_BIT_RX_CHNL1 | \ |
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CSR_FH_INT_BIT_RX_CHNL0) |
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#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ |
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CSR_FH_INT_BIT_TX_CHNL0) |
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/* GPIO */ |
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#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) |
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#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) |
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#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) |
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/* RESET */ |
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#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) |
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#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) |
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#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) |
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#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) |
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#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) |
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#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) |
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/* |
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* GP (general purpose) CONTROL REGISTER |
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* Bit fields: |
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* 27: HW_RF_KILL_SW |
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* Indicates state of (platform's) hardware RF-Kill switch |
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* 26-24: POWER_SAVE_TYPE |
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* Indicates current power-saving mode: |
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* 000 -- No power saving |
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* 001 -- MAC power-down |
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* 010 -- PHY (radio) power-down |
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* 011 -- Error |
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* 9-6: SYS_CONFIG |
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* Indicates current system configuration, reflecting pins on chip |
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* as forced high/low by device circuit board. |
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* 4: GOING_TO_SLEEP |
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* Indicates MAC is entering a power-saving sleep power-down. |
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* Not a good time to access device-internal resources. |
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* 3: MAC_ACCESS_REQ |
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* Host sets this to request and maintain MAC wakeup, to allow host |
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* access to device-internal resources. Host must wait for |
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* MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR |
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* device registers. |
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* 2: INIT_DONE |
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* Host sets this to put device into fully operational D0 power mode. |
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* Host resets this after SW_RESET to put device into low power mode. |
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* 0: MAC_CLOCK_READY |
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* Indicates MAC (ucode processor, etc.) is powered up and can run. |
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* Internal resources are accessible. |
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* NOTE: This does not indicate that the processor is actually running. |
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* NOTE: This does not indicate that 4965 or 3945 has completed |
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* init or post-power-down restore of internal SRAM memory. |
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* Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that |
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* SRAM is restored and uCode is in normal operation mode. |
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* Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and |
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* do not need to save/restore it. |
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* NOTE: After device reset, this bit remains "0" until host sets |
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* INIT_DONE |
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*/ |
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#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) |
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#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) |
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#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) |
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#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) |
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#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) |
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#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) |
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#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) |
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#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) |
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/* EEPROM REG */ |
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#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) |
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#define CSR_EEPROM_REG_BIT_CMD (0x00000002) |
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#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) |
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#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) |
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/* EEPROM GP */ |
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#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ |
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#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) |
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#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) |
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#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) |
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/* GP REG */ |
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#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ |
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#define CSR_GP_REG_NO_POWER_SAVE (0x00000000) |
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#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) |
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#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) |
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#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) |
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/* CSR GIO */ |
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#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) |
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/* |
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* UCODE-DRIVER GP (general purpose) mailbox register 1 |
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* Host driver and uCode write and/or read this register to communicate with |
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* each other. |
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* Bit fields: |
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* 4: UCODE_DISABLE |
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* Host sets this to request permanent halt of uCode, same as |
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* sending CARD_STATE command with "halt" bit set. |
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* 3: CT_KILL_EXIT |
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* Host sets this to request exit from CT_KILL state, i.e. host thinks |
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* device temperature is low enough to continue normal operation. |
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* 2: CMD_BLOCKED |
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* Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) |
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* to release uCode to clear all Tx and command queues, enter |
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* unassociated mode, and power down. |
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* NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. |
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* 1: SW_BIT_RFKILL |
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* Host sets this when issuing CARD_STATE command to request |
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* device sleep. |
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* 0: MAC_SLEEP |
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* uCode sets this when preparing a power-saving power-down. |
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* uCode resets this when power-up is complete and SRAM is sane. |
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* NOTE: 3945/4965 saves internal SRAM data to host when powering down, |
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* and must restore this data after powering back up. |
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* MAC_SLEEP is the best indication that restore is complete. |
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* Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and |
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* do not need to save/restore it. |
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*/ |
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#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) |
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#define CSR_UCODE_SW_BIT_RFKILL (0x00000002) |
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#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) |
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#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) |
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/* GIO Chicken Bits (PCI Express bus link power management) */ |
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) |
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/* LED */ |
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#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) |
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#define CSR_LED_REG_TRUN_ON (0x78) |
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#define CSR_LED_REG_TRUN_OFF (0x38) |
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/* ANA_PLL */ |
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#define CSR39_ANA_PLL_CFG_VAL (0x01000000) |
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/* HPET MEM debug */ |
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#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) |
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/* DRAM INT TBL */ |
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#define CSR_DRAM_INT_TBL_ENABLE (1 << 31) |
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#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) |
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/* |
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* HBUS (Host-side Bus) |
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* |
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* HBUS registers are mapped directly into PCI bus space, but are used |
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* to indirectly access device's internal memory or registers that |
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* may be powered-down. |
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* |
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* Use il_wr()/il_rd() family |
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* for these registers; |
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* host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ |
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* to make sure the MAC (uCode processor, etc.) is powered up for accessing |
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* internal resources. |
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* |
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* Do not use _il_wr()/_il_rd() family to access these registers; |
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* these provide only simple PCI bus access, without waking up the MAC. |
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*/ |
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#define HBUS_BASE (0x400) |
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/* |
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* Registers for accessing device's internal SRAM memory (e.g. SCD SRAM |
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* structures, error log, event log, verifying uCode load). |
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* First write to address register, then read from or write to data register |
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* to complete the job. Once the address register is set up, accesses to |
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* data registers auto-increment the address by one dword. |
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* Bit usage for address registers (read or write): |
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* 0-31: memory address within device |
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*/ |
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#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) |
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#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) |
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#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) |
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#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) |
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/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ |
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#define HBUS_TARG_MBX_C (HBUS_BASE+0x030) |
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#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) |
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/* |
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* Registers for accessing device's internal peripheral registers |
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* (e.g. SCD, BSM, etc.). First write to address register, |
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* then read from or write to data register to complete the job. |
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* Bit usage for address registers (read or write): |
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* 0-15: register address (offset) within device |
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* 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) |
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*/ |
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#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) |
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#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) |
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#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) |
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#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) |
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/* |
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* Per-Tx-queue write pointer (idx, really!) |
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* Indicates idx to next TFD that driver will fill (1 past latest filled). |
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* Bit usage: |
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* 0-7: queue write idx |
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* 11-8: queue selector |
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*/ |
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#define HBUS_TARG_WRPTR (HBUS_BASE+0x060) |
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#endif /* !__il_csr_h__ */
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