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179 lines
4.4 KiB
179 lines
4.4 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Marvell 88E6xxx System Management Interface (SMI) support |
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* |
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* Copyright (c) 2008 Marvell Semiconductor |
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* |
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* Copyright (c) 2019 Vivien Didelot <[email protected]> |
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*/ |
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#include "chip.h" |
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#include "smi.h" |
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/* The switch ADDR[4:1] configuration pins define the chip SMI device address |
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* (ADDR[0] is always zero, thus only even SMI addresses can be strapped). |
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* |
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* When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it |
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* is the only device connected to the SMI master. In this mode it responds to |
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* all 32 possible SMI addresses, and thus maps directly the internal devices. |
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* |
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* When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing |
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* multiple devices to share the SMI interface. In this mode it responds to only |
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* 2 registers, used to indirectly access the internal SMI devices. |
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* |
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* Some chips use a different scheme: Only the ADDR4 pin is used for |
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* configuration, and the device responds to 16 of the 32 SMI |
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* addresses, allowing two to coexist on the same SMI interface. |
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*/ |
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static int mv88e6xxx_smi_direct_read(struct mv88e6xxx_chip *chip, |
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int dev, int reg, u16 *data) |
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{ |
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int ret; |
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ret = mdiobus_read_nested(chip->bus, dev, reg); |
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if (ret < 0) |
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return ret; |
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*data = ret & 0xffff; |
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return 0; |
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} |
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static int mv88e6xxx_smi_direct_write(struct mv88e6xxx_chip *chip, |
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int dev, int reg, u16 data) |
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{ |
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int ret; |
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ret = mdiobus_write_nested(chip->bus, dev, reg, data); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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static int mv88e6xxx_smi_direct_wait(struct mv88e6xxx_chip *chip, |
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int dev, int reg, int bit, int val) |
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{ |
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u16 data; |
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int err; |
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int i; |
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for (i = 0; i < 16; i++) { |
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err = mv88e6xxx_smi_direct_read(chip, dev, reg, &data); |
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if (err) |
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return err; |
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if (!!(data & BIT(bit)) == !!val) |
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return 0; |
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usleep_range(1000, 2000); |
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} |
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return -ETIMEDOUT; |
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} |
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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_direct_ops = { |
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.read = mv88e6xxx_smi_direct_read, |
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.write = mv88e6xxx_smi_direct_write, |
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}; |
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static int mv88e6xxx_smi_dual_direct_read(struct mv88e6xxx_chip *chip, |
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int dev, int reg, u16 *data) |
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{ |
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return mv88e6xxx_smi_direct_read(chip, chip->sw_addr + dev, reg, data); |
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} |
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static int mv88e6xxx_smi_dual_direct_write(struct mv88e6xxx_chip *chip, |
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int dev, int reg, u16 data) |
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{ |
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return mv88e6xxx_smi_direct_write(chip, chip->sw_addr + dev, reg, data); |
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} |
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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_dual_direct_ops = { |
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.read = mv88e6xxx_smi_dual_direct_read, |
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.write = mv88e6xxx_smi_dual_direct_write, |
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}; |
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/* Offset 0x00: SMI Command Register |
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* Offset 0x01: SMI Data Register |
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*/ |
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static int mv88e6xxx_smi_indirect_read(struct mv88e6xxx_chip *chip, |
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int dev, int reg, u16 *data) |
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{ |
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int err; |
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err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, |
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MV88E6XXX_SMI_CMD, 15, 0); |
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if (err) |
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return err; |
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err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr, |
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MV88E6XXX_SMI_CMD, |
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MV88E6XXX_SMI_CMD_BUSY | |
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MV88E6XXX_SMI_CMD_MODE_22 | |
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MV88E6XXX_SMI_CMD_OP_22_READ | |
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(dev << 5) | reg); |
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if (err) |
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return err; |
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err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, |
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MV88E6XXX_SMI_CMD, 15, 0); |
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if (err) |
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return err; |
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return mv88e6xxx_smi_direct_read(chip, chip->sw_addr, |
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MV88E6XXX_SMI_DATA, data); |
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} |
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static int mv88e6xxx_smi_indirect_write(struct mv88e6xxx_chip *chip, |
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int dev, int reg, u16 data) |
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{ |
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int err; |
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err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, |
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MV88E6XXX_SMI_CMD, 15, 0); |
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if (err) |
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return err; |
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err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr, |
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MV88E6XXX_SMI_DATA, data); |
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if (err) |
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return err; |
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err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr, |
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MV88E6XXX_SMI_CMD, |
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MV88E6XXX_SMI_CMD_BUSY | |
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MV88E6XXX_SMI_CMD_MODE_22 | |
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MV88E6XXX_SMI_CMD_OP_22_WRITE | |
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(dev << 5) | reg); |
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if (err) |
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return err; |
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return mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, |
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MV88E6XXX_SMI_CMD, 15, 0); |
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} |
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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_indirect_ops = { |
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.read = mv88e6xxx_smi_indirect_read, |
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.write = mv88e6xxx_smi_indirect_write, |
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}; |
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int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, |
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struct mii_bus *bus, int sw_addr) |
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{ |
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if (chip->info->dual_chip) |
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chip->smi_ops = &mv88e6xxx_smi_dual_direct_ops; |
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else if (sw_addr == 0) |
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chip->smi_ops = &mv88e6xxx_smi_direct_ops; |
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else if (chip->info->multi_chip) |
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chip->smi_ops = &mv88e6xxx_smi_indirect_ops; |
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else |
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return -EINVAL; |
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chip->bus = bus; |
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chip->sw_addr = sw_addr; |
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return 0; |
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}
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