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514 lines
14 KiB
514 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Marvell 88E6xxx Switch PTP support |
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* |
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* Copyright (c) 2008 Marvell Semiconductor |
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* |
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* Copyright (c) 2017 National Instruments |
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* Erik Hons <[email protected]> |
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* Brandon Streiff <[email protected]> |
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* Dane Wagner <[email protected]> |
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*/ |
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#include "chip.h" |
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#include "global2.h" |
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#include "hwtstamp.h" |
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#include "ptp.h" |
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#define MV88E6XXX_MAX_ADJ_PPB 1000000 |
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|
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/* Family MV88E6250: |
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* Raw timestamps are in units of 10-ns clock periods. |
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* |
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* clkadj = scaled_ppm * 10*2^28 / (10^6 * 2^16) |
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* simplifies to |
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* clkadj = scaled_ppm * 2^7 / 5^5 |
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*/ |
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#define MV88E6250_CC_SHIFT 28 |
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#define MV88E6250_CC_MULT (10 << MV88E6250_CC_SHIFT) |
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#define MV88E6250_CC_MULT_NUM (1 << 7) |
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#define MV88E6250_CC_MULT_DEM 3125ULL |
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/* Other families: |
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* Raw timestamps are in units of 8-ns clock periods. |
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* |
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* clkadj = scaled_ppm * 8*2^28 / (10^6 * 2^16) |
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* simplifies to |
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* clkadj = scaled_ppm * 2^9 / 5^6 |
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*/ |
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#define MV88E6XXX_CC_SHIFT 28 |
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#define MV88E6XXX_CC_MULT (8 << MV88E6XXX_CC_SHIFT) |
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#define MV88E6XXX_CC_MULT_NUM (1 << 9) |
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#define MV88E6XXX_CC_MULT_DEM 15625ULL |
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#define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100) |
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#define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc) |
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#define dw_overflow_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \ |
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overflow_work) |
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#define dw_tai_event_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \ |
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tai_event_work) |
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static int mv88e6xxx_tai_read(struct mv88e6xxx_chip *chip, int addr, |
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u16 *data, int len) |
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{ |
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if (!chip->info->ops->avb_ops->tai_read) |
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return -EOPNOTSUPP; |
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return chip->info->ops->avb_ops->tai_read(chip, addr, data, len); |
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} |
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static int mv88e6xxx_tai_write(struct mv88e6xxx_chip *chip, int addr, u16 data) |
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{ |
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if (!chip->info->ops->avb_ops->tai_write) |
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return -EOPNOTSUPP; |
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return chip->info->ops->avb_ops->tai_write(chip, addr, data); |
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} |
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/* TODO: places where this are called should be using pinctrl */ |
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static int mv88e6352_set_gpio_func(struct mv88e6xxx_chip *chip, int pin, |
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int func, int input) |
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{ |
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int err; |
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if (!chip->info->ops->gpio_ops) |
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return -EOPNOTSUPP; |
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err = chip->info->ops->gpio_ops->set_dir(chip, pin, input); |
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if (err) |
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return err; |
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return chip->info->ops->gpio_ops->set_pctl(chip, pin, func); |
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} |
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static u64 mv88e6352_ptp_clock_read(const struct cyclecounter *cc) |
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{ |
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struct mv88e6xxx_chip *chip = cc_to_chip(cc); |
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u16 phc_time[2]; |
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int err; |
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err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_TIME_LO, phc_time, |
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ARRAY_SIZE(phc_time)); |
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if (err) |
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return 0; |
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else |
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return ((u32)phc_time[1] << 16) | phc_time[0]; |
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} |
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static u64 mv88e6165_ptp_clock_read(const struct cyclecounter *cc) |
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{ |
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struct mv88e6xxx_chip *chip = cc_to_chip(cc); |
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u16 phc_time[2]; |
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int err; |
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err = mv88e6xxx_tai_read(chip, MV88E6XXX_PTP_GC_TIME_LO, phc_time, |
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ARRAY_SIZE(phc_time)); |
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if (err) |
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return 0; |
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else |
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return ((u32)phc_time[1] << 16) | phc_time[0]; |
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} |
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/* mv88e6352_config_eventcap - configure TAI event capture |
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* @event: PTP_CLOCK_PPS (internal) or PTP_CLOCK_EXTTS (external) |
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* @rising: zero for falling-edge trigger, else rising-edge trigger |
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* |
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* This will also reset the capture sequence counter. |
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*/ |
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static int mv88e6352_config_eventcap(struct mv88e6xxx_chip *chip, int event, |
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int rising) |
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{ |
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u16 global_config; |
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u16 cap_config; |
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int err; |
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chip->evcap_config = MV88E6XXX_TAI_CFG_CAP_OVERWRITE | |
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MV88E6XXX_TAI_CFG_CAP_CTR_START; |
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if (!rising) |
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chip->evcap_config |= MV88E6XXX_TAI_CFG_EVREQ_FALLING; |
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global_config = (chip->evcap_config | chip->trig_config); |
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err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_CFG, global_config); |
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if (err) |
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return err; |
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if (event == PTP_CLOCK_PPS) { |
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cap_config = MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG; |
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} else if (event == PTP_CLOCK_EXTTS) { |
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/* if STATUS_CAP_TRIG is unset we capture PTP_EVREQ events */ |
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cap_config = 0; |
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} else { |
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return -EINVAL; |
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} |
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/* Write the capture config; this also clears the capture counter */ |
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err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, |
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cap_config); |
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return err; |
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} |
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static void mv88e6352_tai_event_work(struct work_struct *ugly) |
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{ |
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struct delayed_work *dw = to_delayed_work(ugly); |
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struct mv88e6xxx_chip *chip = dw_tai_event_to_chip(dw); |
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struct ptp_clock_event ev; |
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u16 status[4]; |
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u32 raw_ts; |
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int err; |
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mv88e6xxx_reg_lock(chip); |
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err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_EVENT_STATUS, |
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status, ARRAY_SIZE(status)); |
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mv88e6xxx_reg_unlock(chip); |
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if (err) { |
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dev_err(chip->dev, "failed to read TAI status register\n"); |
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return; |
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} |
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if (status[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR) { |
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dev_warn(chip->dev, "missed event capture\n"); |
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return; |
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} |
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if (!(status[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID)) |
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goto out; |
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raw_ts = ((u32)status[2] << 16) | status[1]; |
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/* Clear the valid bit so the next timestamp can come in */ |
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status[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID; |
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mv88e6xxx_reg_lock(chip); |
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err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, status[0]); |
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mv88e6xxx_reg_unlock(chip); |
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/* This is an external timestamp */ |
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ev.type = PTP_CLOCK_EXTTS; |
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/* We only have one timestamping channel. */ |
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ev.index = 0; |
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mv88e6xxx_reg_lock(chip); |
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ev.timestamp = timecounter_cyc2time(&chip->tstamp_tc, raw_ts); |
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mv88e6xxx_reg_unlock(chip); |
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ptp_clock_event(chip->ptp_clock, &ev); |
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out: |
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schedule_delayed_work(&chip->tai_event_work, TAI_EVENT_WORK_INTERVAL); |
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} |
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static int mv88e6xxx_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) |
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{ |
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struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); |
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const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops; |
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int neg_adj = 0; |
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u32 diff, mult; |
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u64 adj; |
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if (scaled_ppm < 0) { |
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neg_adj = 1; |
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scaled_ppm = -scaled_ppm; |
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} |
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mult = ptp_ops->cc_mult; |
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adj = ptp_ops->cc_mult_num; |
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adj *= scaled_ppm; |
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diff = div_u64(adj, ptp_ops->cc_mult_dem); |
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mv88e6xxx_reg_lock(chip); |
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timecounter_read(&chip->tstamp_tc); |
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chip->tstamp_cc.mult = neg_adj ? mult - diff : mult + diff; |
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mv88e6xxx_reg_unlock(chip); |
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return 0; |
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} |
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static int mv88e6xxx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) |
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{ |
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struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); |
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mv88e6xxx_reg_lock(chip); |
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timecounter_adjtime(&chip->tstamp_tc, delta); |
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mv88e6xxx_reg_unlock(chip); |
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return 0; |
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} |
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static int mv88e6xxx_ptp_gettime(struct ptp_clock_info *ptp, |
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struct timespec64 *ts) |
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{ |
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struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); |
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u64 ns; |
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mv88e6xxx_reg_lock(chip); |
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ns = timecounter_read(&chip->tstamp_tc); |
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mv88e6xxx_reg_unlock(chip); |
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*ts = ns_to_timespec64(ns); |
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return 0; |
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} |
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static int mv88e6xxx_ptp_settime(struct ptp_clock_info *ptp, |
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const struct timespec64 *ts) |
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{ |
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struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); |
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u64 ns; |
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ns = timespec64_to_ns(ts); |
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mv88e6xxx_reg_lock(chip); |
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timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, ns); |
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mv88e6xxx_reg_unlock(chip); |
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return 0; |
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} |
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static int mv88e6352_ptp_enable_extts(struct mv88e6xxx_chip *chip, |
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struct ptp_clock_request *rq, int on) |
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{ |
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int rising = (rq->extts.flags & PTP_RISING_EDGE); |
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int func; |
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int pin; |
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int err; |
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/* Reject requests with unsupported flags */ |
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if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | |
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PTP_RISING_EDGE | |
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PTP_FALLING_EDGE | |
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PTP_STRICT_FLAGS)) |
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return -EOPNOTSUPP; |
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/* Reject requests to enable time stamping on both edges. */ |
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if ((rq->extts.flags & PTP_STRICT_FLAGS) && |
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(rq->extts.flags & PTP_ENABLE_FEATURE) && |
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(rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) |
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return -EOPNOTSUPP; |
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pin = ptp_find_pin(chip->ptp_clock, PTP_PF_EXTTS, rq->extts.index); |
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if (pin < 0) |
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return -EBUSY; |
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mv88e6xxx_reg_lock(chip); |
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if (on) { |
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func = MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ; |
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err = mv88e6352_set_gpio_func(chip, pin, func, true); |
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if (err) |
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goto out; |
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schedule_delayed_work(&chip->tai_event_work, |
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TAI_EVENT_WORK_INTERVAL); |
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err = mv88e6352_config_eventcap(chip, PTP_CLOCK_EXTTS, rising); |
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} else { |
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func = MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO; |
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err = mv88e6352_set_gpio_func(chip, pin, func, true); |
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cancel_delayed_work_sync(&chip->tai_event_work); |
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} |
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out: |
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mv88e6xxx_reg_unlock(chip); |
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return err; |
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} |
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static int mv88e6352_ptp_enable(struct ptp_clock_info *ptp, |
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struct ptp_clock_request *rq, int on) |
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{ |
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struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); |
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switch (rq->type) { |
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case PTP_CLK_REQ_EXTTS: |
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return mv88e6352_ptp_enable_extts(chip, rq, on); |
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default: |
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return -EOPNOTSUPP; |
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} |
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} |
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static int mv88e6352_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin, |
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enum ptp_pin_function func, unsigned int chan) |
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{ |
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switch (func) { |
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case PTP_PF_NONE: |
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case PTP_PF_EXTTS: |
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break; |
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case PTP_PF_PEROUT: |
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case PTP_PF_PHYSYNC: |
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return -EOPNOTSUPP; |
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} |
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return 0; |
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} |
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const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = { |
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.clock_read = mv88e6165_ptp_clock_read, |
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.global_enable = mv88e6165_global_enable, |
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.global_disable = mv88e6165_global_disable, |
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.arr0_sts_reg = MV88E6165_PORT_PTP_ARR0_STS, |
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.arr1_sts_reg = MV88E6165_PORT_PTP_ARR1_STS, |
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.dep_sts_reg = MV88E6165_PORT_PTP_DEP_STS, |
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.rx_filters = (1 << HWTSTAMP_FILTER_NONE) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ), |
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.cc_shift = MV88E6XXX_CC_SHIFT, |
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.cc_mult = MV88E6XXX_CC_MULT, |
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.cc_mult_num = MV88E6XXX_CC_MULT_NUM, |
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.cc_mult_dem = MV88E6XXX_CC_MULT_DEM, |
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}; |
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const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops = { |
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.clock_read = mv88e6352_ptp_clock_read, |
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.ptp_enable = mv88e6352_ptp_enable, |
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.ptp_verify = mv88e6352_ptp_verify, |
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.event_work = mv88e6352_tai_event_work, |
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.port_enable = mv88e6352_hwtstamp_port_enable, |
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.port_disable = mv88e6352_hwtstamp_port_disable, |
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.n_ext_ts = 1, |
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.arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS, |
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.arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS, |
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.dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS, |
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.rx_filters = (1 << HWTSTAMP_FILTER_NONE) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ), |
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.cc_shift = MV88E6250_CC_SHIFT, |
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.cc_mult = MV88E6250_CC_MULT, |
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.cc_mult_num = MV88E6250_CC_MULT_NUM, |
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.cc_mult_dem = MV88E6250_CC_MULT_DEM, |
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}; |
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const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = { |
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.clock_read = mv88e6352_ptp_clock_read, |
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.ptp_enable = mv88e6352_ptp_enable, |
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.ptp_verify = mv88e6352_ptp_verify, |
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.event_work = mv88e6352_tai_event_work, |
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.port_enable = mv88e6352_hwtstamp_port_enable, |
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.port_disable = mv88e6352_hwtstamp_port_disable, |
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.n_ext_ts = 1, |
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.arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS, |
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.arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS, |
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.dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS, |
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.rx_filters = (1 << HWTSTAMP_FILTER_NONE) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | |
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(1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ), |
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.cc_shift = MV88E6XXX_CC_SHIFT, |
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.cc_mult = MV88E6XXX_CC_MULT, |
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.cc_mult_num = MV88E6XXX_CC_MULT_NUM, |
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.cc_mult_dem = MV88E6XXX_CC_MULT_DEM, |
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}; |
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static u64 mv88e6xxx_ptp_clock_read(const struct cyclecounter *cc) |
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{ |
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struct mv88e6xxx_chip *chip = cc_to_chip(cc); |
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if (chip->info->ops->ptp_ops->clock_read) |
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return chip->info->ops->ptp_ops->clock_read(cc); |
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return 0; |
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} |
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/* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3 |
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* seconds; this task forces periodic reads so that we don't miss any. |
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*/ |
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#define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16) |
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static void mv88e6xxx_ptp_overflow_check(struct work_struct *work) |
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{ |
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struct delayed_work *dw = to_delayed_work(work); |
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struct mv88e6xxx_chip *chip = dw_overflow_to_chip(dw); |
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struct timespec64 ts; |
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mv88e6xxx_ptp_gettime(&chip->ptp_clock_info, &ts); |
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schedule_delayed_work(&chip->overflow_work, |
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MV88E6XXX_TAI_OVERFLOW_PERIOD); |
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} |
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int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) |
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{ |
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const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops; |
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int i; |
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|
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/* Set up the cycle counter */ |
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memset(&chip->tstamp_cc, 0, sizeof(chip->tstamp_cc)); |
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chip->tstamp_cc.read = mv88e6xxx_ptp_clock_read; |
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chip->tstamp_cc.mask = CYCLECOUNTER_MASK(32); |
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chip->tstamp_cc.mult = ptp_ops->cc_mult; |
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chip->tstamp_cc.shift = ptp_ops->cc_shift; |
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timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, |
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ktime_to_ns(ktime_get_real())); |
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INIT_DELAYED_WORK(&chip->overflow_work, mv88e6xxx_ptp_overflow_check); |
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if (ptp_ops->event_work) |
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INIT_DELAYED_WORK(&chip->tai_event_work, ptp_ops->event_work); |
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|
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chip->ptp_clock_info.owner = THIS_MODULE; |
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snprintf(chip->ptp_clock_info.name, sizeof(chip->ptp_clock_info.name), |
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"%s", dev_name(chip->dev)); |
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|
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chip->ptp_clock_info.n_ext_ts = ptp_ops->n_ext_ts; |
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chip->ptp_clock_info.n_per_out = 0; |
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chip->ptp_clock_info.n_pins = mv88e6xxx_num_gpio(chip); |
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chip->ptp_clock_info.pps = 0; |
|
|
|
for (i = 0; i < chip->ptp_clock_info.n_pins; ++i) { |
|
struct ptp_pin_desc *ppd = &chip->pin_config[i]; |
|
|
|
snprintf(ppd->name, sizeof(ppd->name), "mv88e6xxx_gpio%d", i); |
|
ppd->index = i; |
|
ppd->func = PTP_PF_NONE; |
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} |
|
chip->ptp_clock_info.pin_config = chip->pin_config; |
|
|
|
chip->ptp_clock_info.max_adj = MV88E6XXX_MAX_ADJ_PPB; |
|
chip->ptp_clock_info.adjfine = mv88e6xxx_ptp_adjfine; |
|
chip->ptp_clock_info.adjtime = mv88e6xxx_ptp_adjtime; |
|
chip->ptp_clock_info.gettime64 = mv88e6xxx_ptp_gettime; |
|
chip->ptp_clock_info.settime64 = mv88e6xxx_ptp_settime; |
|
chip->ptp_clock_info.enable = ptp_ops->ptp_enable; |
|
chip->ptp_clock_info.verify = ptp_ops->ptp_verify; |
|
chip->ptp_clock_info.do_aux_work = mv88e6xxx_hwtstamp_work; |
|
|
|
chip->ptp_clock = ptp_clock_register(&chip->ptp_clock_info, chip->dev); |
|
if (IS_ERR(chip->ptp_clock)) |
|
return PTR_ERR(chip->ptp_clock); |
|
|
|
schedule_delayed_work(&chip->overflow_work, |
|
MV88E6XXX_TAI_OVERFLOW_PERIOD); |
|
|
|
return 0; |
|
} |
|
|
|
void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) |
|
{ |
|
if (chip->ptp_clock) { |
|
cancel_delayed_work_sync(&chip->overflow_work); |
|
if (chip->info->ops->ptp_ops->event_work) |
|
cancel_delayed_work_sync(&chip->tai_event_work); |
|
|
|
ptp_clock_unregister(chip->ptp_clock); |
|
chip->ptp_clock = NULL; |
|
} |
|
}
|
|
|