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637 lines
13 KiB
637 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Marvell 88E6xxx VLAN [Spanning Tree] Translation Unit (VTU [STU]) support |
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* |
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* Copyright (c) 2008 Marvell Semiconductor |
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* Copyright (c) 2015 CMC Electronics, Inc. |
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* Copyright (c) 2017 Savoir-faire Linux, Inc. |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/interrupt.h> |
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#include <linux/irqdomain.h> |
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#include "chip.h" |
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#include "global1.h" |
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/* Offset 0x02: VTU FID Register */ |
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static int mv88e6xxx_g1_vtu_fid_read(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 val; |
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int err; |
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err = mv88e6xxx_g1_read(chip, MV88E6352_G1_VTU_FID, &val); |
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if (err) |
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return err; |
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entry->fid = val & MV88E6352_G1_VTU_FID_MASK; |
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return 0; |
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} |
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static int mv88e6xxx_g1_vtu_fid_write(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 val = entry->fid & MV88E6352_G1_VTU_FID_MASK; |
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return mv88e6xxx_g1_write(chip, MV88E6352_G1_VTU_FID, val); |
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} |
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/* Offset 0x03: VTU SID Register */ |
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static int mv88e6xxx_g1_vtu_sid_read(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 val; |
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int err; |
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err = mv88e6xxx_g1_read(chip, MV88E6352_G1_VTU_SID, &val); |
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if (err) |
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return err; |
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entry->sid = val & MV88E6352_G1_VTU_SID_MASK; |
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return 0; |
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} |
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static int mv88e6xxx_g1_vtu_sid_write(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 val = entry->sid & MV88E6352_G1_VTU_SID_MASK; |
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return mv88e6xxx_g1_write(chip, MV88E6352_G1_VTU_SID, val); |
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} |
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/* Offset 0x05: VTU Operation Register */ |
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static int mv88e6xxx_g1_vtu_op_wait(struct mv88e6xxx_chip *chip) |
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{ |
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int bit = __bf_shf(MV88E6XXX_G1_VTU_OP_BUSY); |
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return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_VTU_OP, bit, 0); |
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} |
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static int mv88e6xxx_g1_vtu_op(struct mv88e6xxx_chip *chip, u16 op) |
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{ |
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int err; |
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_OP, |
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MV88E6XXX_G1_VTU_OP_BUSY | op); |
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if (err) |
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return err; |
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return mv88e6xxx_g1_vtu_op_wait(chip); |
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} |
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/* Offset 0x06: VTU VID Register */ |
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static int mv88e6xxx_g1_vtu_vid_read(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 val; |
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int err; |
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_VID, &val); |
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if (err) |
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return err; |
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entry->vid = val & 0xfff; |
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if (val & MV88E6390_G1_VTU_VID_PAGE) |
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entry->vid |= 0x1000; |
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entry->valid = !!(val & MV88E6XXX_G1_VTU_VID_VALID); |
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return 0; |
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} |
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static int mv88e6xxx_g1_vtu_vid_write(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 val = entry->vid & 0xfff; |
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if (entry->vid & 0x1000) |
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val |= MV88E6390_G1_VTU_VID_PAGE; |
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if (entry->valid) |
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val |= MV88E6XXX_G1_VTU_VID_VALID; |
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return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_VID, val); |
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} |
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/* Offset 0x07: VTU/STU Data Register 1 |
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* Offset 0x08: VTU/STU Data Register 2 |
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* Offset 0x09: VTU/STU Data Register 3 |
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*/ |
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static int mv88e6185_g1_vtu_stu_data_read(struct mv88e6xxx_chip *chip, |
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u16 *regs) |
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{ |
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int i; |
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/* Read all 3 VTU/STU Data registers */ |
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for (i = 0; i < 3; ++i) { |
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u16 *reg = ®s[i]; |
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int err; |
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); |
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if (err) |
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return err; |
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} |
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return 0; |
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} |
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static int mv88e6185_g1_vtu_data_read(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 regs[3]; |
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int err; |
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int i; |
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err = mv88e6185_g1_vtu_stu_data_read(chip, regs); |
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if (err) |
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return err; |
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/* Extract MemberTag data */ |
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for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
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unsigned int member_offset = (i % 4) * 4; |
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entry->member[i] = (regs[i / 4] >> member_offset) & 0x3; |
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} |
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return 0; |
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} |
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static int mv88e6185_g1_stu_data_read(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 regs[3]; |
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int err; |
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int i; |
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err = mv88e6185_g1_vtu_stu_data_read(chip, regs); |
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if (err) |
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return err; |
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/* Extract PortState data */ |
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for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
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unsigned int state_offset = (i % 4) * 4 + 2; |
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entry->state[i] = (regs[i / 4] >> state_offset) & 0x3; |
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} |
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return 0; |
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} |
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static int mv88e6185_g1_vtu_data_write(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 regs[3] = { 0 }; |
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int i; |
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/* Insert MemberTag and PortState data */ |
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for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
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unsigned int member_offset = (i % 4) * 4; |
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unsigned int state_offset = member_offset + 2; |
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regs[i / 4] |= (entry->member[i] & 0x3) << member_offset; |
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regs[i / 4] |= (entry->state[i] & 0x3) << state_offset; |
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} |
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/* Write all 3 VTU/STU Data registers */ |
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for (i = 0; i < 3; ++i) { |
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u16 reg = regs[i]; |
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int err; |
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); |
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if (err) |
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return err; |
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} |
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return 0; |
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} |
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static int mv88e6390_g1_vtu_data_read(struct mv88e6xxx_chip *chip, u8 *data) |
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{ |
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u16 regs[2]; |
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int i; |
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/* Read the 2 VTU/STU Data registers */ |
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for (i = 0; i < 2; ++i) { |
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u16 *reg = ®s[i]; |
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int err; |
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); |
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if (err) |
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return err; |
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} |
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/* Extract data */ |
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for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
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unsigned int offset = (i % 8) * 2; |
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data[i] = (regs[i / 8] >> offset) & 0x3; |
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} |
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return 0; |
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} |
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static int mv88e6390_g1_vtu_data_write(struct mv88e6xxx_chip *chip, u8 *data) |
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{ |
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u16 regs[2] = { 0 }; |
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int i; |
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/* Insert data */ |
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for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
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unsigned int offset = (i % 8) * 2; |
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regs[i / 8] |= (data[i] & 0x3) << offset; |
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} |
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/* Write the 2 VTU/STU Data registers */ |
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for (i = 0; i < 2; ++i) { |
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u16 reg = regs[i]; |
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int err; |
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err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); |
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if (err) |
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return err; |
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} |
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return 0; |
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} |
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/* VLAN Translation Unit Operations */ |
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static int mv88e6xxx_g1_vtu_stu_getnext(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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int err; |
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err = mv88e6xxx_g1_vtu_sid_write(chip, entry); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_STU_GET_NEXT); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_sid_read(chip, entry); |
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if (err) |
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return err; |
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return mv88e6xxx_g1_vtu_vid_read(chip, entry); |
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} |
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static int mv88e6xxx_g1_vtu_stu_get(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *vtu) |
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{ |
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struct mv88e6xxx_vtu_entry stu; |
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int err; |
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err = mv88e6xxx_g1_vtu_sid_read(chip, vtu); |
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if (err) |
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return err; |
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stu.sid = vtu->sid - 1; |
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err = mv88e6xxx_g1_vtu_stu_getnext(chip, &stu); |
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if (err) |
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return err; |
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if (stu.sid != vtu->sid || !stu.valid) |
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return -EINVAL; |
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return 0; |
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} |
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int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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int err; |
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err = mv88e6xxx_g1_vtu_op_wait(chip); |
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if (err) |
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return err; |
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/* To get the next higher active VID, the VTU GetNext operation can be |
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* started again without setting the VID registers since it already |
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* contains the last VID. |
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* |
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* To save a few hardware accesses and abstract this to the caller, |
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* write the VID only once, when the entry is given as invalid. |
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*/ |
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if (!entry->valid) { |
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err = mv88e6xxx_g1_vtu_vid_write(chip, entry); |
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if (err) |
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return err; |
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} |
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err = mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT); |
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if (err) |
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return err; |
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return mv88e6xxx_g1_vtu_vid_read(chip, entry); |
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} |
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int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 val; |
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int err; |
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err = mv88e6xxx_g1_vtu_getnext(chip, entry); |
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if (err) |
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return err; |
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if (entry->valid) { |
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err = mv88e6185_g1_vtu_data_read(chip, entry); |
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if (err) |
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return err; |
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err = mv88e6185_g1_stu_data_read(chip, entry); |
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if (err) |
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return err; |
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/* VTU DBNum[3:0] are located in VTU Operation 3:0 |
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* VTU DBNum[7:4] ([5:4] for 6250) are located in VTU Operation 11:8 (9:8) |
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*/ |
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_OP, &val); |
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if (err) |
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return err; |
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entry->fid = val & 0x000f; |
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entry->fid |= (val & 0x0f00) >> 4; |
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entry->fid &= mv88e6xxx_num_databases(chip) - 1; |
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} |
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return 0; |
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} |
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int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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int err; |
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/* Fetch VLAN MemberTag data from the VTU */ |
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err = mv88e6xxx_g1_vtu_getnext(chip, entry); |
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if (err) |
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return err; |
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if (entry->valid) { |
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err = mv88e6185_g1_vtu_data_read(chip, entry); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_fid_read(chip, entry); |
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if (err) |
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return err; |
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/* Fetch VLAN PortState data from the STU */ |
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err = mv88e6xxx_g1_vtu_stu_get(chip, entry); |
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if (err) |
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return err; |
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err = mv88e6185_g1_stu_data_read(chip, entry); |
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if (err) |
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return err; |
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} |
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return 0; |
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} |
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int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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int err; |
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/* Fetch VLAN MemberTag data from the VTU */ |
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err = mv88e6xxx_g1_vtu_getnext(chip, entry); |
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if (err) |
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return err; |
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if (entry->valid) { |
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err = mv88e6390_g1_vtu_data_read(chip, entry->member); |
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if (err) |
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return err; |
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/* Fetch VLAN PortState data from the STU */ |
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err = mv88e6xxx_g1_vtu_stu_get(chip, entry); |
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if (err) |
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return err; |
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err = mv88e6390_g1_vtu_data_read(chip, entry->state); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_fid_read(chip, entry); |
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if (err) |
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return err; |
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} |
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return 0; |
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} |
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int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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u16 op = MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE; |
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int err; |
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err = mv88e6xxx_g1_vtu_op_wait(chip); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_vid_write(chip, entry); |
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if (err) |
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return err; |
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if (entry->valid) { |
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err = mv88e6185_g1_vtu_data_write(chip, entry); |
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if (err) |
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return err; |
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/* VTU DBNum[3:0] are located in VTU Operation 3:0 |
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* VTU DBNum[7:4] are located in VTU Operation 11:8 |
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* |
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* For the 6250/6220, the latter are really [5:4] and |
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* 9:8, but in those cases bits 7:6 of entry->fid are |
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* 0 since they have num_databases = 64. |
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*/ |
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op |= entry->fid & 0x000f; |
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op |= (entry->fid & 0x00f0) << 4; |
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} |
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return mv88e6xxx_g1_vtu_op(chip, op); |
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} |
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int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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int err; |
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err = mv88e6xxx_g1_vtu_op_wait(chip); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_vid_write(chip, entry); |
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if (err) |
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return err; |
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if (entry->valid) { |
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/* Write MemberTag and PortState data */ |
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err = mv88e6185_g1_vtu_data_write(chip, entry); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_sid_write(chip, entry); |
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if (err) |
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return err; |
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/* Load STU entry */ |
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err = mv88e6xxx_g1_vtu_op(chip, |
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MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_fid_write(chip, entry); |
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if (err) |
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return err; |
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} |
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/* Load/Purge VTU entry */ |
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return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE); |
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} |
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int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry) |
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{ |
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int err; |
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err = mv88e6xxx_g1_vtu_op_wait(chip); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_vid_write(chip, entry); |
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if (err) |
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return err; |
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if (entry->valid) { |
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/* Write PortState data */ |
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err = mv88e6390_g1_vtu_data_write(chip, entry->state); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_sid_write(chip, entry); |
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if (err) |
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return err; |
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/* Load STU entry */ |
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err = mv88e6xxx_g1_vtu_op(chip, |
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MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE); |
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if (err) |
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return err; |
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/* Write MemberTag data */ |
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err = mv88e6390_g1_vtu_data_write(chip, entry->member); |
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if (err) |
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return err; |
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err = mv88e6xxx_g1_vtu_fid_write(chip, entry); |
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if (err) |
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return err; |
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} |
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/* Load/Purge VTU entry */ |
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return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE); |
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} |
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int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip) |
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{ |
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int err; |
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err = mv88e6xxx_g1_vtu_op_wait(chip); |
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if (err) |
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return err; |
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|
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return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_FLUSH_ALL); |
|
} |
|
|
|
static irqreturn_t mv88e6xxx_g1_vtu_prob_irq_thread_fn(int irq, void *dev_id) |
|
{ |
|
struct mv88e6xxx_chip *chip = dev_id; |
|
struct mv88e6xxx_vtu_entry entry; |
|
int spid; |
|
int err; |
|
u16 val; |
|
|
|
mv88e6xxx_reg_lock(chip); |
|
|
|
err = mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION); |
|
if (err) |
|
goto out; |
|
|
|
err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_OP, &val); |
|
if (err) |
|
goto out; |
|
|
|
err = mv88e6xxx_g1_vtu_vid_read(chip, &entry); |
|
if (err) |
|
goto out; |
|
|
|
spid = val & MV88E6XXX_G1_VTU_OP_SPID_MASK; |
|
|
|
if (val & MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION) { |
|
dev_err_ratelimited(chip->dev, "VTU member violation for vid %d, source port %d\n", |
|
entry.vid, spid); |
|
chip->ports[spid].vtu_member_violation++; |
|
} |
|
|
|
if (val & MV88E6XXX_G1_VTU_OP_MISS_VIOLATION) { |
|
dev_dbg_ratelimited(chip->dev, "VTU miss violation for vid %d, source port %d\n", |
|
entry.vid, spid); |
|
chip->ports[spid].vtu_miss_violation++; |
|
} |
|
|
|
mv88e6xxx_reg_unlock(chip); |
|
|
|
return IRQ_HANDLED; |
|
|
|
out: |
|
mv88e6xxx_reg_unlock(chip); |
|
|
|
dev_err(chip->dev, "VTU problem: error %d while handling interrupt\n", |
|
err); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip) |
|
{ |
|
int err; |
|
|
|
chip->vtu_prob_irq = irq_find_mapping(chip->g1_irq.domain, |
|
MV88E6XXX_G1_STS_IRQ_VTU_PROB); |
|
if (chip->vtu_prob_irq < 0) |
|
return chip->vtu_prob_irq; |
|
|
|
snprintf(chip->vtu_prob_irq_name, sizeof(chip->vtu_prob_irq_name), |
|
"mv88e6xxx-%s-g1-vtu-prob", dev_name(chip->dev)); |
|
|
|
err = request_threaded_irq(chip->vtu_prob_irq, NULL, |
|
mv88e6xxx_g1_vtu_prob_irq_thread_fn, |
|
IRQF_ONESHOT, chip->vtu_prob_irq_name, |
|
chip); |
|
if (err) |
|
irq_dispose_mapping(chip->vtu_prob_irq); |
|
|
|
return err; |
|
} |
|
|
|
void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip) |
|
{ |
|
free_irq(chip->vtu_prob_irq, chip); |
|
irq_dispose_mapping(chip->vtu_prob_irq); |
|
}
|
|
|