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727 lines
20 KiB
727 lines
20 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Marvell 88E6xxx Ethernet switch single-chip definition |
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* |
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* Copyright (c) 2008 Marvell Semiconductor |
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*/ |
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#ifndef _MV88E6XXX_CHIP_H |
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#define _MV88E6XXX_CHIP_H |
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#include <linux/idr.h> |
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#include <linux/if_vlan.h> |
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#include <linux/irq.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/kthread.h> |
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#include <linux/phy.h> |
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#include <linux/ptp_clock_kernel.h> |
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#include <linux/timecounter.h> |
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#include <net/dsa.h> |
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#define MV88E6XXX_N_FID 4096 |
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/* PVT limits for 4-bit port and 5-bit switch */ |
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#define MV88E6XXX_MAX_PVT_SWITCHES 32 |
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#define MV88E6XXX_MAX_PVT_PORTS 16 |
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#define MV88E6XXX_MAX_GPIO 16 |
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enum mv88e6xxx_egress_mode { |
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MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
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MV88E6XXX_EGRESS_MODE_UNTAGGED, |
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MV88E6XXX_EGRESS_MODE_TAGGED, |
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MV88E6XXX_EGRESS_MODE_ETHERTYPE, |
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}; |
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enum mv88e6xxx_egress_direction { |
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MV88E6XXX_EGRESS_DIR_INGRESS, |
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MV88E6XXX_EGRESS_DIR_EGRESS, |
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}; |
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enum mv88e6xxx_frame_mode { |
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MV88E6XXX_FRAME_MODE_NORMAL, |
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MV88E6XXX_FRAME_MODE_DSA, |
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MV88E6XXX_FRAME_MODE_PROVIDER, |
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MV88E6XXX_FRAME_MODE_ETHERTYPE, |
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}; |
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/* List of supported models */ |
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enum mv88e6xxx_model { |
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MV88E6085, |
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MV88E6095, |
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MV88E6097, |
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MV88E6123, |
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MV88E6131, |
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MV88E6141, |
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MV88E6161, |
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MV88E6165, |
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MV88E6171, |
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MV88E6172, |
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MV88E6175, |
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MV88E6176, |
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MV88E6185, |
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MV88E6190, |
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MV88E6190X, |
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MV88E6191, |
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MV88E6220, |
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MV88E6240, |
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MV88E6250, |
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MV88E6290, |
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MV88E6320, |
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MV88E6321, |
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MV88E6341, |
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MV88E6350, |
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MV88E6351, |
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MV88E6352, |
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MV88E6390, |
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MV88E6390X, |
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}; |
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enum mv88e6xxx_family { |
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MV88E6XXX_FAMILY_NONE, |
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MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ |
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MV88E6XXX_FAMILY_6095, /* 6092 6095 */ |
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MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ |
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MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ |
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MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ |
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MV88E6XXX_FAMILY_6250, /* 6220 6250 */ |
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MV88E6XXX_FAMILY_6320, /* 6320 6321 */ |
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MV88E6XXX_FAMILY_6341, /* 6141 6341 */ |
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MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ |
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MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ |
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MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ |
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}; |
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struct mv88e6xxx_ops; |
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struct mv88e6xxx_info { |
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enum mv88e6xxx_family family; |
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u16 prod_num; |
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const char *name; |
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unsigned int num_databases; |
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unsigned int num_macs; |
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unsigned int num_ports; |
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unsigned int num_internal_phys; |
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unsigned int num_gpio; |
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unsigned int max_vid; |
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unsigned int port_base_addr; |
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unsigned int phy_base_addr; |
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unsigned int global1_addr; |
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unsigned int global2_addr; |
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unsigned int age_time_coeff; |
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unsigned int g1_irqs; |
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unsigned int g2_irqs; |
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bool pvt; |
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/* Mark certain ports as invalid. This is required for example for the |
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* MV88E6220 (which is in general a MV88E6250 with 7 ports) but the |
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* ports 2-4 are not routet to pins. |
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*/ |
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unsigned int invalid_port_mask; |
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/* Multi-chip Addressing Mode. |
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* Some chips respond to only 2 registers of its own SMI device address |
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* when it is non-zero, and use indirect access to internal registers. |
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*/ |
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bool multi_chip; |
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/* Dual-chip Addressing Mode |
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* Some chips respond to only half of the 32 SMI addresses, |
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* allowing two to coexist on the same SMI interface. |
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*/ |
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bool dual_chip; |
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enum dsa_tag_protocol tag_protocol; |
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/* Mask for FromPort and ToPort value of PortVec used in ATU Move |
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* operation. 0 means that the ATU Move operation is not supported. |
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*/ |
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u8 atu_move_port_mask; |
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const struct mv88e6xxx_ops *ops; |
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/* Supports PTP */ |
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bool ptp_support; |
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}; |
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struct mv88e6xxx_atu_entry { |
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u8 state; |
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bool trunk; |
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u16 portvec; |
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u8 mac[ETH_ALEN]; |
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}; |
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struct mv88e6xxx_vtu_entry { |
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u16 vid; |
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u16 fid; |
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u8 sid; |
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bool valid; |
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u8 member[DSA_MAX_PORTS]; |
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u8 state[DSA_MAX_PORTS]; |
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}; |
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struct mv88e6xxx_bus_ops; |
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struct mv88e6xxx_irq_ops; |
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struct mv88e6xxx_gpio_ops; |
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struct mv88e6xxx_avb_ops; |
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struct mv88e6xxx_ptp_ops; |
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struct mv88e6xxx_irq { |
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u16 masked; |
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struct irq_chip chip; |
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struct irq_domain *domain; |
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int nirqs; |
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}; |
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/* state flags for mv88e6xxx_port_hwtstamp::state */ |
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enum { |
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MV88E6XXX_HWTSTAMP_ENABLED, |
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MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, |
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}; |
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struct mv88e6xxx_port_hwtstamp { |
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/* Port index */ |
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int port_id; |
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/* Timestamping state */ |
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unsigned long state; |
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/* Resources for receive timestamping */ |
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struct sk_buff_head rx_queue; |
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struct sk_buff_head rx_queue2; |
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/* Resources for transmit timestamping */ |
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unsigned long tx_tstamp_start; |
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struct sk_buff *tx_skb; |
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u16 tx_seq_id; |
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/* Current timestamp configuration */ |
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struct hwtstamp_config tstamp_config; |
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}; |
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enum mv88e6xxx_policy_mapping { |
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MV88E6XXX_POLICY_MAPPING_DA, |
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MV88E6XXX_POLICY_MAPPING_SA, |
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MV88E6XXX_POLICY_MAPPING_VTU, |
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MV88E6XXX_POLICY_MAPPING_ETYPE, |
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MV88E6XXX_POLICY_MAPPING_PPPOE, |
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MV88E6XXX_POLICY_MAPPING_VBAS, |
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MV88E6XXX_POLICY_MAPPING_OPT82, |
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MV88E6XXX_POLICY_MAPPING_UDP, |
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}; |
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enum mv88e6xxx_policy_action { |
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MV88E6XXX_POLICY_ACTION_NORMAL, |
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MV88E6XXX_POLICY_ACTION_MIRROR, |
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MV88E6XXX_POLICY_ACTION_TRAP, |
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MV88E6XXX_POLICY_ACTION_DISCARD, |
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}; |
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struct mv88e6xxx_policy { |
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enum mv88e6xxx_policy_mapping mapping; |
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enum mv88e6xxx_policy_action action; |
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struct ethtool_rx_flow_spec fs; |
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u8 addr[ETH_ALEN]; |
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int port; |
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u16 vid; |
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}; |
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struct mv88e6xxx_port { |
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struct mv88e6xxx_chip *chip; |
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int port; |
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u64 serdes_stats[2]; |
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u64 atu_member_violation; |
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u64 atu_miss_violation; |
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u64 atu_full_violation; |
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u64 vtu_member_violation; |
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u64 vtu_miss_violation; |
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phy_interface_t interface; |
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u8 cmode; |
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bool mirror_ingress; |
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bool mirror_egress; |
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unsigned int serdes_irq; |
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char serdes_irq_name[64]; |
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struct devlink_region *region; |
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}; |
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enum mv88e6xxx_region_id { |
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MV88E6XXX_REGION_GLOBAL1 = 0, |
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MV88E6XXX_REGION_GLOBAL2, |
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MV88E6XXX_REGION_ATU, |
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MV88E6XXX_REGION_VTU, |
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_MV88E6XXX_REGION_MAX, |
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}; |
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struct mv88e6xxx_region_priv { |
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enum mv88e6xxx_region_id id; |
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}; |
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struct mv88e6xxx_chip { |
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const struct mv88e6xxx_info *info; |
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/* The dsa_switch this private structure is related to */ |
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struct dsa_switch *ds; |
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/* The device this structure is associated to */ |
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struct device *dev; |
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/* This mutex protects the access to the switch registers */ |
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struct mutex reg_lock; |
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/* The MII bus and the address on the bus that is used to |
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* communication with the switch |
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*/ |
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const struct mv88e6xxx_bus_ops *smi_ops; |
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struct mii_bus *bus; |
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int sw_addr; |
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/* Handles automatic disabling and re-enabling of the PHY |
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* polling unit. |
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*/ |
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const struct mv88e6xxx_bus_ops *phy_ops; |
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struct mutex ppu_mutex; |
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int ppu_disabled; |
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struct work_struct ppu_work; |
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struct timer_list ppu_timer; |
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/* This mutex serialises access to the statistics unit. |
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* Hold this mutex over snapshot + dump sequences. |
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*/ |
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struct mutex stats_mutex; |
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/* A switch may have a GPIO line tied to its reset pin. Parse |
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* this from the device tree, and use it before performing |
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* switch soft reset. |
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*/ |
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struct gpio_desc *reset; |
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/* set to size of eeprom if supported by the switch */ |
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u32 eeprom_len; |
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/* List of mdio busses */ |
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struct list_head mdios; |
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/* Policy Control List IDs and rules */ |
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struct idr policies; |
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/* There can be two interrupt controllers, which are chained |
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* off a GPIO as interrupt source |
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*/ |
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struct mv88e6xxx_irq g1_irq; |
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struct mv88e6xxx_irq g2_irq; |
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int irq; |
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char irq_name[64]; |
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int device_irq; |
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char device_irq_name[64]; |
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int watchdog_irq; |
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char watchdog_irq_name[64]; |
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int atu_prob_irq; |
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char atu_prob_irq_name[64]; |
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int vtu_prob_irq; |
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char vtu_prob_irq_name[64]; |
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struct kthread_worker *kworker; |
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struct kthread_delayed_work irq_poll_work; |
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/* GPIO resources */ |
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u8 gpio_data[2]; |
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/* This cyclecounter abstracts the switch PTP time. |
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* reg_lock must be held for any operation that read()s. |
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*/ |
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struct cyclecounter tstamp_cc; |
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struct timecounter tstamp_tc; |
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struct delayed_work overflow_work; |
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struct ptp_clock *ptp_clock; |
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struct ptp_clock_info ptp_clock_info; |
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struct delayed_work tai_event_work; |
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struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; |
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u16 trig_config; |
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u16 evcap_config; |
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u16 enable_count; |
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/* Current ingress and egress monitor ports */ |
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int egress_dest_port; |
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int ingress_dest_port; |
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/* Per-port timestamping resources. */ |
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struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; |
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/* Array of port structures. */ |
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struct mv88e6xxx_port ports[DSA_MAX_PORTS]; |
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/* devlink regions */ |
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struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; |
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}; |
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struct mv88e6xxx_bus_ops { |
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int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); |
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int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); |
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}; |
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struct mv88e6xxx_mdio_bus { |
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struct mii_bus *bus; |
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struct mv88e6xxx_chip *chip; |
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struct list_head list; |
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bool external; |
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}; |
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struct mv88e6xxx_ops { |
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/* Switch Setup Errata, called early in the switch setup to |
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* allow any errata actions to be performed |
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*/ |
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int (*setup_errata)(struct mv88e6xxx_chip *chip); |
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int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); |
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int (*ip_pri_map)(struct mv88e6xxx_chip *chip); |
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/* Ingress Rate Limit unit (IRL) operations */ |
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int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); |
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int (*get_eeprom)(struct mv88e6xxx_chip *chip, |
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struct ethtool_eeprom *eeprom, u8 *data); |
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int (*set_eeprom)(struct mv88e6xxx_chip *chip, |
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struct ethtool_eeprom *eeprom, u8 *data); |
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int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); |
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int (*phy_read)(struct mv88e6xxx_chip *chip, |
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struct mii_bus *bus, |
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int addr, int reg, u16 *val); |
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int (*phy_write)(struct mv88e6xxx_chip *chip, |
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struct mii_bus *bus, |
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int addr, int reg, u16 val); |
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/* Priority Override Table operations */ |
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int (*pot_clear)(struct mv88e6xxx_chip *chip); |
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/* PHY Polling Unit (PPU) operations */ |
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int (*ppu_enable)(struct mv88e6xxx_chip *chip); |
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int (*ppu_disable)(struct mv88e6xxx_chip *chip); |
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/* Switch Software Reset */ |
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int (*reset)(struct mv88e6xxx_chip *chip); |
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/* RGMII Receive/Transmit Timing Control |
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* Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. |
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*/ |
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int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, |
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phy_interface_t mode); |
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#define LINK_FORCED_DOWN 0 |
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#define LINK_FORCED_UP 1 |
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#define LINK_UNFORCED -2 |
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/* Port's MAC link state |
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* Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, |
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* or LINK_UNFORCED for normal link detection. |
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*/ |
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int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); |
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/* Synchronise the port link state with that of the SERDES |
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*/ |
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int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); |
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#define PAUSE_ON 1 |
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#define PAUSE_OFF 0 |
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/* Enable/disable sending Pause */ |
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int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, |
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int pause); |
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#define SPEED_MAX INT_MAX |
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#define SPEED_UNFORCED -2 |
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#define DUPLEX_UNFORCED -2 |
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/* Port's MAC speed (in Mbps) and MAC duplex mode |
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* |
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* Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. |
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* Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. |
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* |
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* Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, |
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* or DUPLEX_UNFORCED for normal duplex detection. |
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*/ |
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int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, |
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int speed, int duplex); |
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/* What interface mode should be used for maximum speed? */ |
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phy_interface_t (*port_max_speed_mode)(int port); |
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int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); |
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int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, |
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enum mv88e6xxx_policy_mapping mapping, |
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enum mv88e6xxx_policy_action action); |
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int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, |
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enum mv88e6xxx_frame_mode mode); |
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int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, |
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bool unicast); |
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int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, |
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bool multicast); |
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int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, |
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u16 etype); |
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int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, |
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size_t size); |
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int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); |
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int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, |
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u8 out); |
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int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); |
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int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); |
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int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); |
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/* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. |
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* Some chips allow this to be configured on specific ports. |
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*/ |
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int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, |
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phy_interface_t mode); |
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int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); |
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/* Some devices have a per port register indicating what is |
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* the upstream port this port should forward to. |
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*/ |
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int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, |
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int upstream_port); |
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/* Snapshot the statistics for a port. The statistics can then |
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* be read back a leisure but still with a consistent view. |
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*/ |
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int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); |
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/* Set the histogram mode for statistics, when the control registers |
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* are separated out of the STATS_OP register. |
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*/ |
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int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); |
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/* Return the number of strings describing statistics */ |
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int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); |
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int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); |
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int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, |
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uint64_t *data); |
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int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); |
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int (*set_egress_port)(struct mv88e6xxx_chip *chip, |
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enum mv88e6xxx_egress_direction direction, |
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int port); |
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#define MV88E6XXX_CASCADE_PORT_NONE 0xe |
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#define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf |
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int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); |
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const struct mv88e6xxx_irq_ops *watchdog_ops; |
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int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); |
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/* Power on/off a SERDES interface */ |
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int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane, |
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bool up); |
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/* SERDES lane mapping */ |
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u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); |
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int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, |
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u8 lane, struct phylink_link_state *state); |
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int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, |
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u8 lane, unsigned int mode, |
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phy_interface_t interface, |
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const unsigned long *advertise); |
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int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, |
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u8 lane); |
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int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, |
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u8 lane, int speed, int duplex); |
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/* SERDES interrupt handling */ |
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unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, |
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int port); |
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int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane, |
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bool enable); |
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irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, |
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u8 lane); |
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/* Statistics from the SERDES interface */ |
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int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); |
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int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, |
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uint8_t *data); |
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int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, |
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uint64_t *data); |
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/* SERDES registers for ethtool */ |
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int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); |
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void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, |
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void *_p); |
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/* Address Translation Unit operations */ |
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int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); |
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int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); |
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/* VLAN Translation Unit operations */ |
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int (*vtu_getnext)(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry); |
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int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, |
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struct mv88e6xxx_vtu_entry *entry); |
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/* GPIO operations */ |
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const struct mv88e6xxx_gpio_ops *gpio_ops; |
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/* Interface to the AVB/PTP registers */ |
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const struct mv88e6xxx_avb_ops *avb_ops; |
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/* Remote Management Unit operations */ |
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int (*rmu_disable)(struct mv88e6xxx_chip *chip); |
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/* Precision Time Protocol operations */ |
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const struct mv88e6xxx_ptp_ops *ptp_ops; |
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/* Phylink */ |
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void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, |
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unsigned long *mask, |
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struct phylink_link_state *state); |
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/* Max Frame Size */ |
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int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); |
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}; |
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struct mv88e6xxx_irq_ops { |
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/* Action to be performed when the interrupt happens */ |
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int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); |
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/* Setup the hardware to generate the interrupt */ |
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int (*irq_setup)(struct mv88e6xxx_chip *chip); |
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/* Reset the hardware to stop generating the interrupt */ |
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void (*irq_free)(struct mv88e6xxx_chip *chip); |
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}; |
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struct mv88e6xxx_gpio_ops { |
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/* Get/set data on GPIO pin */ |
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int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); |
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int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, |
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int value); |
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/* get/set GPIO direction */ |
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int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); |
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int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, |
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bool input); |
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/* get/set GPIO pin control */ |
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int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, |
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int *func); |
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int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, |
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int func); |
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}; |
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struct mv88e6xxx_avb_ops { |
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/* Access port-scoped Precision Time Protocol registers */ |
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int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, |
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u16 *data, int len); |
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int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, |
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u16 data); |
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/* Access global Precision Time Protocol registers */ |
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int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, |
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int len); |
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int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); |
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/* Access global Time Application Interface registers */ |
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int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, |
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int len); |
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int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); |
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}; |
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struct mv88e6xxx_ptp_ops { |
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u64 (*clock_read)(const struct cyclecounter *cc); |
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int (*ptp_enable)(struct ptp_clock_info *ptp, |
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struct ptp_clock_request *rq, int on); |
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int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, |
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enum ptp_pin_function func, unsigned int chan); |
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void (*event_work)(struct work_struct *ugly); |
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int (*port_enable)(struct mv88e6xxx_chip *chip, int port); |
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int (*port_disable)(struct mv88e6xxx_chip *chip, int port); |
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int (*global_enable)(struct mv88e6xxx_chip *chip); |
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int (*global_disable)(struct mv88e6xxx_chip *chip); |
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int n_ext_ts; |
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int arr0_sts_reg; |
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int arr1_sts_reg; |
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int dep_sts_reg; |
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u32 rx_filters; |
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u32 cc_shift; |
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u32 cc_mult; |
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u32 cc_mult_num; |
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u32 cc_mult_dem; |
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}; |
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#define STATS_TYPE_PORT BIT(0) |
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#define STATS_TYPE_BANK0 BIT(1) |
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#define STATS_TYPE_BANK1 BIT(2) |
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struct mv88e6xxx_hw_stat { |
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char string[ETH_GSTRING_LEN]; |
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size_t size; |
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int reg; |
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int type; |
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}; |
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static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) |
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{ |
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return chip->info->pvt; |
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} |
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static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) |
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{ |
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return !!chip->info->global2_addr; |
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} |
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static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) |
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{ |
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return chip->info->num_databases; |
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} |
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static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) |
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{ |
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return chip->info->num_macs; |
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} |
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static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) |
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{ |
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return chip->info->num_ports; |
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} |
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static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) |
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{ |
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return chip->info->max_vid; |
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} |
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static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) |
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{ |
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return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); |
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} |
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static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) |
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{ |
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return chip->info->num_gpio; |
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} |
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static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) |
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{ |
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return (chip->info->invalid_port_mask & BIT(port)) != 0; |
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} |
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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); |
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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); |
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int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, |
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u16 mask, u16 val); |
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int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, |
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int bit, int val); |
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struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); |
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static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) |
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{ |
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mutex_lock(&chip->reg_lock); |
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} |
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static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) |
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{ |
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mutex_unlock(&chip->reg_lock); |
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} |
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int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); |
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#endif /* _MV88E6XXX_CHIP_H */
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