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452 lines
12 KiB
452 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* CAN bus driver for the Freescale MPC5xxx embedded CPU. |
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* |
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* Copyright (C) 2004-2005 Andrey Volkov <[email protected]>, |
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* Varma Electronics Oy |
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* Copyright (C) 2008-2009 Wolfgang Grandegger <[email protected]> |
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* Copyright (C) 2009 Wolfram Sang, Pengutronix <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/interrupt.h> |
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#include <linux/platform_device.h> |
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#include <linux/netdevice.h> |
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#include <linux/can/dev.h> |
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#include <linux/of_platform.h> |
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#include <sysdev/fsl_soc.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <asm/mpc52xx.h> |
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#include "mscan.h" |
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#define DRV_NAME "mpc5xxx_can" |
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struct mpc5xxx_can_data { |
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unsigned int type; |
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u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name, |
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int *mscan_clksrc); |
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void (*put_clock)(struct platform_device *ofdev); |
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}; |
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#ifdef CONFIG_PPC_MPC52xx |
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static const struct of_device_id mpc52xx_cdm_ids[] = { |
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{ .compatible = "fsl,mpc5200-cdm", }, |
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{} |
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}; |
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static u32 mpc52xx_can_get_clock(struct platform_device *ofdev, |
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const char *clock_name, int *mscan_clksrc) |
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{ |
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unsigned int pvr; |
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struct mpc52xx_cdm __iomem *cdm; |
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struct device_node *np_cdm; |
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unsigned int freq; |
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u32 val; |
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pvr = mfspr(SPRN_PVR); |
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|
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/* |
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* Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock |
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* (IP_CLK) can be selected as MSCAN clock source. According to |
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* the MPC5200 user's manual, the oscillator clock is the better |
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* choice as it has less jitter. For this reason, it is selected |
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* by default. Unfortunately, it can not be selected for the old |
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* MPC5200 Rev. A chips due to a hardware bug (check errata). |
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*/ |
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if (clock_name && strcmp(clock_name, "ip") == 0) |
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*mscan_clksrc = MSCAN_CLKSRC_BUS; |
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else |
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*mscan_clksrc = MSCAN_CLKSRC_XTAL; |
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freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); |
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if (!freq) |
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return 0; |
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if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011) |
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return freq; |
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/* Determine SYS_XTAL_IN frequency from the clock domain settings */ |
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np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids); |
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if (!np_cdm) { |
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dev_err(&ofdev->dev, "can't get clock node!\n"); |
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return 0; |
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} |
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cdm = of_iomap(np_cdm, 0); |
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if (!cdm) { |
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of_node_put(np_cdm); |
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dev_err(&ofdev->dev, "can't map clock node!\n"); |
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return 0; |
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} |
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if (in_8(&cdm->ipb_clk_sel) & 0x1) |
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freq *= 2; |
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val = in_be32(&cdm->rstcfg); |
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freq *= (val & (1 << 5)) ? 8 : 4; |
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freq /= (val & (1 << 6)) ? 12 : 16; |
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of_node_put(np_cdm); |
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iounmap(cdm); |
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return freq; |
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} |
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#else /* !CONFIG_PPC_MPC52xx */ |
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static u32 mpc52xx_can_get_clock(struct platform_device *ofdev, |
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const char *clock_name, int *mscan_clksrc) |
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{ |
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return 0; |
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} |
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#endif /* CONFIG_PPC_MPC52xx */ |
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#ifdef CONFIG_PPC_MPC512x |
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static u32 mpc512x_can_get_clock(struct platform_device *ofdev, |
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const char *clock_source, int *mscan_clksrc) |
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{ |
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struct device_node *np; |
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u32 clockdiv; |
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enum { |
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CLK_FROM_AUTO, |
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CLK_FROM_IPS, |
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CLK_FROM_SYS, |
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CLK_FROM_REF, |
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} clk_from; |
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struct clk *clk_in, *clk_can; |
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unsigned long freq_calc; |
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struct mscan_priv *priv; |
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struct clk *clk_ipg; |
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/* the caller passed in the clock source spec that was read from |
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* the device tree, get the optional clock divider as well |
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*/ |
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np = ofdev->dev.of_node; |
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clockdiv = 1; |
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of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv); |
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dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n", |
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clock_source ? clock_source : "<NULL>", clockdiv); |
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/* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to |
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* get set, and the 'ips' clock is the input to the MSCAN |
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* component |
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* |
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* for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC] |
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* bit needs to get cleared, an optional clock-divider may have |
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* been specified (the default value is 1), the appropriate |
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* MSCAN related MCLK is the input to the MSCAN component |
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* |
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* in the absence of a clock-source spec, first an optimal clock |
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* gets determined based on the 'sys' clock, if that fails the |
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* 'ref' clock is used |
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*/ |
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clk_from = CLK_FROM_AUTO; |
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if (clock_source) { |
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/* interpret the device tree's spec for the clock source */ |
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if (!strcmp(clock_source, "ip")) |
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clk_from = CLK_FROM_IPS; |
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else if (!strcmp(clock_source, "sys")) |
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clk_from = CLK_FROM_SYS; |
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else if (!strcmp(clock_source, "ref")) |
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clk_from = CLK_FROM_REF; |
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else |
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goto err_invalid; |
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dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from); |
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} |
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if (clk_from == CLK_FROM_AUTO) { |
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/* no spec so far, try the 'sys' clock; round to the |
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* next MHz and see if we can get a multiple of 16MHz |
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*/ |
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dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n"); |
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clk_in = devm_clk_get(&ofdev->dev, "sys"); |
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if (IS_ERR(clk_in)) |
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goto err_notavail; |
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freq_calc = clk_get_rate(clk_in); |
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freq_calc += 499999; |
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freq_calc /= 1000000; |
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freq_calc *= 1000000; |
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if ((freq_calc % 16000000) == 0) { |
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clk_from = CLK_FROM_SYS; |
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clockdiv = freq_calc / 16000000; |
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dev_dbg(&ofdev->dev, |
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"clk fit, sys[%lu] div[%d] freq[%lu]\n", |
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freq_calc, clockdiv, freq_calc / clockdiv); |
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} |
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} |
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if (clk_from == CLK_FROM_AUTO) { |
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/* no spec so far, use the 'ref' clock */ |
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dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n"); |
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clk_in = devm_clk_get(&ofdev->dev, "ref"); |
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if (IS_ERR(clk_in)) |
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goto err_notavail; |
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clk_from = CLK_FROM_REF; |
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freq_calc = clk_get_rate(clk_in); |
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dev_dbg(&ofdev->dev, |
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"clk fit, ref[%lu] (no div) freq[%lu]\n", |
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freq_calc, freq_calc); |
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} |
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/* select IPS or MCLK as the MSCAN input (returned to the caller), |
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* setup the MCLK mux source and rate if applicable, apply the |
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* optionally specified or derived above divider, and determine |
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* the actual resulting clock rate to return to the caller |
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*/ |
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switch (clk_from) { |
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case CLK_FROM_IPS: |
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clk_can = devm_clk_get(&ofdev->dev, "ips"); |
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if (IS_ERR(clk_can)) |
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goto err_notavail; |
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priv = netdev_priv(dev_get_drvdata(&ofdev->dev)); |
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priv->clk_can = clk_can; |
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freq_calc = clk_get_rate(clk_can); |
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*mscan_clksrc = MSCAN_CLKSRC_IPS; |
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dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n", |
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*mscan_clksrc, freq_calc); |
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break; |
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case CLK_FROM_SYS: |
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case CLK_FROM_REF: |
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clk_can = devm_clk_get(&ofdev->dev, "mclk"); |
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if (IS_ERR(clk_can)) |
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goto err_notavail; |
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priv = netdev_priv(dev_get_drvdata(&ofdev->dev)); |
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priv->clk_can = clk_can; |
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if (clk_from == CLK_FROM_SYS) |
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clk_in = devm_clk_get(&ofdev->dev, "sys"); |
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if (clk_from == CLK_FROM_REF) |
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clk_in = devm_clk_get(&ofdev->dev, "ref"); |
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if (IS_ERR(clk_in)) |
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goto err_notavail; |
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clk_set_parent(clk_can, clk_in); |
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freq_calc = clk_get_rate(clk_in); |
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freq_calc /= clockdiv; |
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clk_set_rate(clk_can, freq_calc); |
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freq_calc = clk_get_rate(clk_can); |
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*mscan_clksrc = MSCAN_CLKSRC_BUS; |
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dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n", |
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*mscan_clksrc, freq_calc); |
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break; |
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default: |
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goto err_invalid; |
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} |
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/* the above clk_can item is used for the bitrate, access to |
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* the peripheral's register set needs the clk_ipg item |
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*/ |
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clk_ipg = devm_clk_get(&ofdev->dev, "ipg"); |
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if (IS_ERR(clk_ipg)) |
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goto err_notavail_ipg; |
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if (clk_prepare_enable(clk_ipg)) |
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goto err_notavail_ipg; |
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priv = netdev_priv(dev_get_drvdata(&ofdev->dev)); |
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priv->clk_ipg = clk_ipg; |
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/* return the determined clock source rate */ |
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return freq_calc; |
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err_invalid: |
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dev_err(&ofdev->dev, "invalid clock source specification\n"); |
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/* clock source rate could not get determined */ |
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return 0; |
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err_notavail: |
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dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n"); |
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/* clock source rate could not get determined */ |
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return 0; |
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err_notavail_ipg: |
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dev_err(&ofdev->dev, "cannot acquire or setup register clock\n"); |
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/* clock source rate could not get determined */ |
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return 0; |
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} |
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static void mpc512x_can_put_clock(struct platform_device *ofdev) |
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{ |
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struct mscan_priv *priv; |
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priv = netdev_priv(dev_get_drvdata(&ofdev->dev)); |
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if (priv->clk_ipg) |
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clk_disable_unprepare(priv->clk_ipg); |
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} |
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#else /* !CONFIG_PPC_MPC512x */ |
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static u32 mpc512x_can_get_clock(struct platform_device *ofdev, |
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const char *clock_name, int *mscan_clksrc) |
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{ |
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return 0; |
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} |
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#define mpc512x_can_put_clock NULL |
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#endif /* CONFIG_PPC_MPC512x */ |
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static const struct of_device_id mpc5xxx_can_table[]; |
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static int mpc5xxx_can_probe(struct platform_device *ofdev) |
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{ |
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const struct of_device_id *match; |
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const struct mpc5xxx_can_data *data; |
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struct device_node *np = ofdev->dev.of_node; |
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struct net_device *dev; |
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struct mscan_priv *priv; |
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void __iomem *base; |
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const char *clock_name = NULL; |
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int irq, mscan_clksrc = 0; |
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int err = -ENOMEM; |
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match = of_match_device(mpc5xxx_can_table, &ofdev->dev); |
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if (!match) |
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return -EINVAL; |
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data = match->data; |
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base = of_iomap(np, 0); |
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if (!base) { |
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dev_err(&ofdev->dev, "couldn't ioremap\n"); |
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return err; |
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} |
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irq = irq_of_parse_and_map(np, 0); |
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if (!irq) { |
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dev_err(&ofdev->dev, "no irq found\n"); |
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err = -ENODEV; |
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goto exit_unmap_mem; |
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} |
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dev = alloc_mscandev(); |
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if (!dev) |
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goto exit_dispose_irq; |
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platform_set_drvdata(ofdev, dev); |
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SET_NETDEV_DEV(dev, &ofdev->dev); |
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priv = netdev_priv(dev); |
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priv->reg_base = base; |
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dev->irq = irq; |
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clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL); |
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BUG_ON(!data); |
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priv->type = data->type; |
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priv->can.clock.freq = data->get_clock(ofdev, clock_name, |
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&mscan_clksrc); |
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if (!priv->can.clock.freq) { |
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dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n"); |
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goto exit_free_mscan; |
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} |
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err = register_mscandev(dev, mscan_clksrc); |
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if (err) { |
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dev_err(&ofdev->dev, "registering %s failed (err=%d)\n", |
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DRV_NAME, err); |
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goto exit_free_mscan; |
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} |
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dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n", |
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priv->reg_base, dev->irq, priv->can.clock.freq); |
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return 0; |
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exit_free_mscan: |
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free_candev(dev); |
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exit_dispose_irq: |
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irq_dispose_mapping(irq); |
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exit_unmap_mem: |
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iounmap(base); |
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return err; |
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} |
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static int mpc5xxx_can_remove(struct platform_device *ofdev) |
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{ |
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const struct of_device_id *match; |
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const struct mpc5xxx_can_data *data; |
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struct net_device *dev = platform_get_drvdata(ofdev); |
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struct mscan_priv *priv = netdev_priv(dev); |
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match = of_match_device(mpc5xxx_can_table, &ofdev->dev); |
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data = match ? match->data : NULL; |
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unregister_mscandev(dev); |
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if (data && data->put_clock) |
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data->put_clock(ofdev); |
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iounmap(priv->reg_base); |
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irq_dispose_mapping(dev->irq); |
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free_candev(dev); |
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return 0; |
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} |
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#ifdef CONFIG_PM |
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static struct mscan_regs saved_regs; |
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static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state) |
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{ |
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struct net_device *dev = platform_get_drvdata(ofdev); |
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struct mscan_priv *priv = netdev_priv(dev); |
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struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; |
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_memcpy_fromio(&saved_regs, regs, sizeof(*regs)); |
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return 0; |
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} |
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static int mpc5xxx_can_resume(struct platform_device *ofdev) |
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{ |
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struct net_device *dev = platform_get_drvdata(ofdev); |
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struct mscan_priv *priv = netdev_priv(dev); |
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struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; |
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regs->canctl0 |= MSCAN_INITRQ; |
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while (!(regs->canctl1 & MSCAN_INITAK)) |
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udelay(10); |
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regs->canctl1 = saved_regs.canctl1; |
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regs->canbtr0 = saved_regs.canbtr0; |
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regs->canbtr1 = saved_regs.canbtr1; |
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regs->canidac = saved_regs.canidac; |
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/* restore masks, buffers etc. */ |
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_memcpy_toio(®s->canidar1_0, (void *)&saved_regs.canidar1_0, |
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sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0)); |
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regs->canctl0 &= ~MSCAN_INITRQ; |
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regs->cantbsel = saved_regs.cantbsel; |
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regs->canrier = saved_regs.canrier; |
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regs->cantier = saved_regs.cantier; |
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regs->canctl0 = saved_regs.canctl0; |
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return 0; |
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} |
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#endif |
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static const struct mpc5xxx_can_data mpc5200_can_data = { |
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.type = MSCAN_TYPE_MPC5200, |
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.get_clock = mpc52xx_can_get_clock, |
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/* .put_clock not applicable */ |
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}; |
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static const struct mpc5xxx_can_data mpc5121_can_data = { |
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.type = MSCAN_TYPE_MPC5121, |
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.get_clock = mpc512x_can_get_clock, |
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.put_clock = mpc512x_can_put_clock, |
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}; |
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static const struct of_device_id mpc5xxx_can_table[] = { |
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{ .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, }, |
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/* Note that only MPC5121 Rev. 2 (and later) is supported */ |
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{ .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, mpc5xxx_can_table); |
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static struct platform_driver mpc5xxx_can_driver = { |
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.driver = { |
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.name = "mpc5xxx_can", |
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.of_match_table = mpc5xxx_can_table, |
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}, |
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.probe = mpc5xxx_can_probe, |
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.remove = mpc5xxx_can_remove, |
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#ifdef CONFIG_PM |
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.suspend = mpc5xxx_can_suspend, |
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.resume = mpc5xxx_can_resume, |
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#endif |
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}; |
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module_platform_driver(mpc5xxx_can_driver); |
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MODULE_AUTHOR("Wolfgang Grandegger <[email protected]>"); |
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MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver"); |
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MODULE_LICENSE("GPL v2");
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