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556 lines
15 KiB
556 lines
15 KiB
/* |
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* Copyright (C) 2013 NVIDIA Corporation |
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* |
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* Permission to use, copy, modify, distribute, and sell this software and its |
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* documentation for any purpose is hereby granted without fee, provided that |
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* the above copyright notice appear in all copies and that both that copyright |
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* notice and this permission notice appear in supporting documentation, and |
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* that the name of the copyright holders not be used in advertising or |
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* publicity pertaining to distribution of the software without specific, |
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* written prior permission. The copyright holders make no representations |
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* about the suitability of this software for any purpose. It is provided "as |
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* is" without express or implied warranty. |
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* |
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
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* OF THIS SOFTWARE. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/host1x.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include "dev.h" |
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#define MIPI_CAL_CTRL 0x00 |
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#define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26) |
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#define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24) |
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#define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4) |
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#define MIPI_CAL_CTRL_START (1 << 0) |
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#define MIPI_CAL_AUTOCAL_CTRL 0x01 |
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#define MIPI_CAL_STATUS 0x02 |
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#define MIPI_CAL_STATUS_DONE (1 << 16) |
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#define MIPI_CAL_STATUS_ACTIVE (1 << 0) |
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#define MIPI_CAL_CONFIG_CSIA 0x05 |
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#define MIPI_CAL_CONFIG_CSIB 0x06 |
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#define MIPI_CAL_CONFIG_CSIC 0x07 |
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#define MIPI_CAL_CONFIG_CSID 0x08 |
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#define MIPI_CAL_CONFIG_CSIE 0x09 |
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#define MIPI_CAL_CONFIG_CSIF 0x0a |
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#define MIPI_CAL_CONFIG_DSIA 0x0e |
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#define MIPI_CAL_CONFIG_DSIB 0x0f |
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#define MIPI_CAL_CONFIG_DSIC 0x10 |
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#define MIPI_CAL_CONFIG_DSID 0x11 |
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#define MIPI_CAL_CONFIG_DSIA_CLK 0x19 |
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#define MIPI_CAL_CONFIG_DSIB_CLK 0x1a |
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#define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b |
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#define MIPI_CAL_CONFIG_DSIC_CLK 0x1c |
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#define MIPI_CAL_CONFIG_CSICD_CLK 0x1c |
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#define MIPI_CAL_CONFIG_DSID_CLK 0x1d |
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#define MIPI_CAL_CONFIG_CSIE_CLK 0x1d |
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|
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/* for data and clock lanes */ |
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#define MIPI_CAL_CONFIG_SELECT (1 << 21) |
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|
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/* for data lanes */ |
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#define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16) |
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#define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8) |
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#define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0) |
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|
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/* for clock lanes */ |
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#define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8) |
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#define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0) |
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#define MIPI_CAL_BIAS_PAD_CFG0 0x16 |
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#define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1) |
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#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0) |
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#define MIPI_CAL_BIAS_PAD_CFG1 0x17 |
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#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16) |
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#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8) |
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#define MIPI_CAL_BIAS_PAD_CFG2 0x18 |
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#define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16) |
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#define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4) |
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#define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1) |
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struct tegra_mipi_pad { |
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unsigned long data; |
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unsigned long clk; |
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}; |
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struct tegra_mipi_soc { |
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bool has_clk_lane; |
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const struct tegra_mipi_pad *pads; |
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unsigned int num_pads; |
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bool clock_enable_override; |
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bool needs_vclamp_ref; |
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/* bias pad configuration settings */ |
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u8 pad_drive_down_ref; |
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u8 pad_drive_up_ref; |
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u8 pad_vclamp_level; |
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u8 pad_vauxp_level; |
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/* calibration settings for data lanes */ |
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u8 hspdos; |
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u8 hspuos; |
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u8 termos; |
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/* calibration settings for clock lanes */ |
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u8 hsclkpdos; |
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u8 hsclkpuos; |
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}; |
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struct tegra_mipi { |
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const struct tegra_mipi_soc *soc; |
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struct device *dev; |
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void __iomem *regs; |
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struct mutex lock; |
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struct clk *clk; |
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unsigned long usage_count; |
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}; |
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struct tegra_mipi_device { |
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struct platform_device *pdev; |
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struct tegra_mipi *mipi; |
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struct device *device; |
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unsigned long pads; |
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}; |
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static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi, |
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unsigned long offset) |
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{ |
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return readl(mipi->regs + (offset << 2)); |
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} |
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static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value, |
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unsigned long offset) |
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{ |
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writel(value, mipi->regs + (offset << 2)); |
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} |
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static int tegra_mipi_power_up(struct tegra_mipi *mipi) |
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{ |
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u32 value; |
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int err; |
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err = clk_enable(mipi->clk); |
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if (err < 0) |
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return err; |
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value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0); |
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value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP; |
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if (mipi->soc->needs_vclamp_ref) |
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value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF; |
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tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0); |
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value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2); |
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value &= ~MIPI_CAL_BIAS_PAD_PDVREG; |
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tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2); |
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clk_disable(mipi->clk); |
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return 0; |
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} |
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static int tegra_mipi_power_down(struct tegra_mipi *mipi) |
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{ |
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u32 value; |
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int err; |
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err = clk_enable(mipi->clk); |
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if (err < 0) |
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return err; |
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/* |
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* The MIPI_CAL_BIAS_PAD_PDVREG controls a voltage regulator that |
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* supplies the DSI pads. This must be kept enabled until none of the |
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* DSI lanes are used anymore. |
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*/ |
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value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2); |
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value |= MIPI_CAL_BIAS_PAD_PDVREG; |
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tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2); |
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/* |
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* MIPI_CAL_BIAS_PAD_PDVCLAMP and MIPI_CAL_BIAS_PAD_E_VCLAMP_REF |
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* control a regulator that supplies current to the pre-driver logic. |
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* Powering down this regulator causes DSI to fail, so it must remain |
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* powered on until none of the DSI lanes are used anymore. |
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*/ |
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value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0); |
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if (mipi->soc->needs_vclamp_ref) |
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value &= ~MIPI_CAL_BIAS_PAD_E_VCLAMP_REF; |
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value |= MIPI_CAL_BIAS_PAD_PDVCLAMP; |
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tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0); |
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return 0; |
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} |
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struct tegra_mipi_device *tegra_mipi_request(struct device *device, |
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struct device_node *np) |
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{ |
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struct tegra_mipi_device *dev; |
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struct of_phandle_args args; |
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int err; |
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err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate", |
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"#nvidia,mipi-calibrate-cells", 0, |
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&args); |
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if (err < 0) |
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return ERR_PTR(err); |
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dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
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if (!dev) { |
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err = -ENOMEM; |
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goto out; |
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} |
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dev->pdev = of_find_device_by_node(args.np); |
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if (!dev->pdev) { |
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err = -ENODEV; |
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goto free; |
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} |
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dev->mipi = platform_get_drvdata(dev->pdev); |
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if (!dev->mipi) { |
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err = -EPROBE_DEFER; |
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goto put; |
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} |
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of_node_put(args.np); |
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dev->pads = args.args[0]; |
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dev->device = device; |
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return dev; |
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put: |
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platform_device_put(dev->pdev); |
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free: |
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kfree(dev); |
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out: |
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of_node_put(args.np); |
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return ERR_PTR(err); |
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} |
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EXPORT_SYMBOL(tegra_mipi_request); |
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void tegra_mipi_free(struct tegra_mipi_device *device) |
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{ |
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platform_device_put(device->pdev); |
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kfree(device); |
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} |
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EXPORT_SYMBOL(tegra_mipi_free); |
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int tegra_mipi_enable(struct tegra_mipi_device *dev) |
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{ |
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int err = 0; |
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mutex_lock(&dev->mipi->lock); |
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if (dev->mipi->usage_count++ == 0) |
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err = tegra_mipi_power_up(dev->mipi); |
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mutex_unlock(&dev->mipi->lock); |
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return err; |
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} |
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EXPORT_SYMBOL(tegra_mipi_enable); |
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int tegra_mipi_disable(struct tegra_mipi_device *dev) |
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{ |
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int err = 0; |
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mutex_lock(&dev->mipi->lock); |
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if (--dev->mipi->usage_count == 0) |
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err = tegra_mipi_power_down(dev->mipi); |
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mutex_unlock(&dev->mipi->lock); |
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return err; |
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} |
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EXPORT_SYMBOL(tegra_mipi_disable); |
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int tegra_mipi_finish_calibration(struct tegra_mipi_device *device) |
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{ |
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struct tegra_mipi *mipi = device->mipi; |
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void __iomem *status_reg = mipi->regs + (MIPI_CAL_STATUS << 2); |
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u32 value; |
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int err; |
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err = readl_relaxed_poll_timeout(status_reg, value, |
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!(value & MIPI_CAL_STATUS_ACTIVE) && |
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(value & MIPI_CAL_STATUS_DONE), 50, |
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250000); |
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mutex_unlock(&device->mipi->lock); |
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clk_disable(device->mipi->clk); |
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return err; |
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} |
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EXPORT_SYMBOL(tegra_mipi_finish_calibration); |
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int tegra_mipi_start_calibration(struct tegra_mipi_device *device) |
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{ |
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const struct tegra_mipi_soc *soc = device->mipi->soc; |
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unsigned int i; |
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u32 value; |
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int err; |
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err = clk_enable(device->mipi->clk); |
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if (err < 0) |
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return err; |
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mutex_lock(&device->mipi->lock); |
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value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) | |
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MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref); |
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tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1); |
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value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2); |
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value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7); |
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value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7); |
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value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level); |
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value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level); |
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tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2); |
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for (i = 0; i < soc->num_pads; i++) { |
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u32 clk = 0, data = 0; |
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if (device->pads & BIT(i)) { |
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data = MIPI_CAL_CONFIG_SELECT | |
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MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) | |
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MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) | |
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MIPI_CAL_CONFIG_TERMOS(soc->termos); |
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clk = MIPI_CAL_CONFIG_SELECT | |
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MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) | |
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MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos); |
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} |
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tegra_mipi_writel(device->mipi, data, soc->pads[i].data); |
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if (soc->has_clk_lane && soc->pads[i].clk != 0) |
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tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk); |
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} |
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value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL); |
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value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf); |
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value &= ~MIPI_CAL_CTRL_PRESCALE(0x3); |
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value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa); |
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value |= MIPI_CAL_CTRL_PRESCALE(0x2); |
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if (!soc->clock_enable_override) |
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value &= ~MIPI_CAL_CTRL_CLKEN_OVR; |
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else |
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value |= MIPI_CAL_CTRL_CLKEN_OVR; |
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tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); |
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/* clear any pending status bits */ |
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value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS); |
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tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS); |
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value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL); |
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value |= MIPI_CAL_CTRL_START; |
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tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); |
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/* |
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* Wait for min 72uS to let calibration logic finish calibration |
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* sequence codes before waiting for pads idle state to apply the |
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* results. |
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*/ |
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usleep_range(75, 80); |
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return 0; |
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} |
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EXPORT_SYMBOL(tegra_mipi_start_calibration); |
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static const struct tegra_mipi_pad tegra114_mipi_pads[] = { |
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{ .data = MIPI_CAL_CONFIG_CSIA }, |
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{ .data = MIPI_CAL_CONFIG_CSIB }, |
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{ .data = MIPI_CAL_CONFIG_CSIC }, |
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{ .data = MIPI_CAL_CONFIG_CSID }, |
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{ .data = MIPI_CAL_CONFIG_CSIE }, |
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{ .data = MIPI_CAL_CONFIG_DSIA }, |
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{ .data = MIPI_CAL_CONFIG_DSIB }, |
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{ .data = MIPI_CAL_CONFIG_DSIC }, |
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{ .data = MIPI_CAL_CONFIG_DSID }, |
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}; |
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static const struct tegra_mipi_soc tegra114_mipi_soc = { |
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.has_clk_lane = false, |
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.pads = tegra114_mipi_pads, |
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.num_pads = ARRAY_SIZE(tegra114_mipi_pads), |
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.clock_enable_override = true, |
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.needs_vclamp_ref = true, |
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.pad_drive_down_ref = 0x2, |
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.pad_drive_up_ref = 0x0, |
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.pad_vclamp_level = 0x0, |
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.pad_vauxp_level = 0x0, |
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.hspdos = 0x0, |
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.hspuos = 0x4, |
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.termos = 0x5, |
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.hsclkpdos = 0x0, |
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.hsclkpuos = 0x4, |
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}; |
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static const struct tegra_mipi_pad tegra124_mipi_pads[] = { |
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{ .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK }, |
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{ .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK }, |
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{ .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK }, |
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{ .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK }, |
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{ .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK }, |
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{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK }, |
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{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK }, |
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}; |
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static const struct tegra_mipi_soc tegra124_mipi_soc = { |
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.has_clk_lane = true, |
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.pads = tegra124_mipi_pads, |
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.num_pads = ARRAY_SIZE(tegra124_mipi_pads), |
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.clock_enable_override = true, |
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.needs_vclamp_ref = true, |
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.pad_drive_down_ref = 0x2, |
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.pad_drive_up_ref = 0x0, |
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.pad_vclamp_level = 0x0, |
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.pad_vauxp_level = 0x0, |
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.hspdos = 0x0, |
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.hspuos = 0x0, |
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.termos = 0x0, |
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.hsclkpdos = 0x1, |
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.hsclkpuos = 0x2, |
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}; |
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static const struct tegra_mipi_soc tegra132_mipi_soc = { |
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.has_clk_lane = true, |
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.pads = tegra124_mipi_pads, |
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.num_pads = ARRAY_SIZE(tegra124_mipi_pads), |
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.clock_enable_override = false, |
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.needs_vclamp_ref = false, |
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.pad_drive_down_ref = 0x0, |
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.pad_drive_up_ref = 0x3, |
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.pad_vclamp_level = 0x0, |
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.pad_vauxp_level = 0x0, |
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.hspdos = 0x0, |
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.hspuos = 0x0, |
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.termos = 0x0, |
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.hsclkpdos = 0x3, |
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.hsclkpuos = 0x2, |
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}; |
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static const struct tegra_mipi_pad tegra210_mipi_pads[] = { |
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{ .data = MIPI_CAL_CONFIG_CSIA, .clk = 0 }, |
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{ .data = MIPI_CAL_CONFIG_CSIB, .clk = 0 }, |
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{ .data = MIPI_CAL_CONFIG_CSIC, .clk = 0 }, |
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{ .data = MIPI_CAL_CONFIG_CSID, .clk = 0 }, |
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{ .data = MIPI_CAL_CONFIG_CSIE, .clk = 0 }, |
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{ .data = MIPI_CAL_CONFIG_CSIF, .clk = 0 }, |
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{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK }, |
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{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK }, |
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{ .data = MIPI_CAL_CONFIG_DSIC, .clk = MIPI_CAL_CONFIG_DSIC_CLK }, |
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{ .data = MIPI_CAL_CONFIG_DSID, .clk = MIPI_CAL_CONFIG_DSID_CLK }, |
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}; |
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static const struct tegra_mipi_soc tegra210_mipi_soc = { |
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.has_clk_lane = true, |
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.pads = tegra210_mipi_pads, |
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.num_pads = ARRAY_SIZE(tegra210_mipi_pads), |
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.clock_enable_override = true, |
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.needs_vclamp_ref = false, |
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.pad_drive_down_ref = 0x0, |
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.pad_drive_up_ref = 0x3, |
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.pad_vclamp_level = 0x1, |
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.pad_vauxp_level = 0x1, |
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.hspdos = 0x0, |
|
.hspuos = 0x2, |
|
.termos = 0x0, |
|
.hsclkpdos = 0x0, |
|
.hsclkpuos = 0x2, |
|
}; |
|
|
|
static const struct of_device_id tegra_mipi_of_match[] = { |
|
{ .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc }, |
|
{ .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc }, |
|
{ .compatible = "nvidia,tegra132-mipi", .data = &tegra132_mipi_soc }, |
|
{ .compatible = "nvidia,tegra210-mipi", .data = &tegra210_mipi_soc }, |
|
{ }, |
|
}; |
|
|
|
static int tegra_mipi_probe(struct platform_device *pdev) |
|
{ |
|
const struct of_device_id *match; |
|
struct tegra_mipi *mipi; |
|
struct resource *res; |
|
int err; |
|
|
|
match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node); |
|
if (!match) |
|
return -ENODEV; |
|
|
|
mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL); |
|
if (!mipi) |
|
return -ENOMEM; |
|
|
|
mipi->soc = match->data; |
|
mipi->dev = &pdev->dev; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
mipi->regs = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(mipi->regs)) |
|
return PTR_ERR(mipi->regs); |
|
|
|
mutex_init(&mipi->lock); |
|
|
|
mipi->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(mipi->clk)) { |
|
dev_err(&pdev->dev, "failed to get clock\n"); |
|
return PTR_ERR(mipi->clk); |
|
} |
|
|
|
err = clk_prepare(mipi->clk); |
|
if (err < 0) |
|
return err; |
|
|
|
platform_set_drvdata(pdev, mipi); |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra_mipi_remove(struct platform_device *pdev) |
|
{ |
|
struct tegra_mipi *mipi = platform_get_drvdata(pdev); |
|
|
|
clk_unprepare(mipi->clk); |
|
|
|
return 0; |
|
} |
|
|
|
struct platform_driver tegra_mipi_driver = { |
|
.driver = { |
|
.name = "tegra-mipi", |
|
.of_match_table = tegra_mipi_of_match, |
|
}, |
|
.probe = tegra_mipi_probe, |
|
.remove = tegra_mipi_remove, |
|
};
|
|
|