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108 lines
3.2 KiB
108 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2012-2013, NVIDIA Corporation. |
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*/ |
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/* |
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* Function naming determines intended use: |
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* |
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* <x>_r(void) : Returns the offset for register <x>. |
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* |
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>. |
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* |
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. |
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* |
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted |
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* and masked to place it at field <y> of register <x>. This value |
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* can be |'d with others to produce a full register value for |
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* register <x>. |
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* |
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This |
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* value can be ~'d and then &'d to clear the value of field <y> for |
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* register <x>. |
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* |
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted |
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* to place it at field <y> of register <x>. This value can be |'d |
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* with others to produce a full register value for <x>. |
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* |
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register |
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* <x> value 'r' after being shifted to place its LSB at bit 0. |
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* This value is suitable for direct comparison with other unshifted |
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* values appropriate for use in field <y> of register <x>. |
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* |
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for |
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* field <y> of register <x>. This value is suitable for direct |
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* comparison with unshifted values appropriate for use in field <y> |
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* of register <x>. |
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*/ |
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#ifndef __hw_host1x_channel_host1x_h__ |
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#define __hw_host1x_channel_host1x_h__ |
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static inline u32 host1x_channel_fifostat_r(void) |
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{ |
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return 0x0; |
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} |
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#define HOST1X_CHANNEL_FIFOSTAT \ |
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host1x_channel_fifostat_r() |
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static inline u32 host1x_channel_fifostat_cfempty_v(u32 r) |
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{ |
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return (r >> 10) & 0x1; |
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} |
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#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(r) \ |
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host1x_channel_fifostat_cfempty_v(r) |
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static inline u32 host1x_channel_dmastart_r(void) |
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{ |
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return 0x14; |
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} |
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#define HOST1X_CHANNEL_DMASTART \ |
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host1x_channel_dmastart_r() |
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static inline u32 host1x_channel_dmaput_r(void) |
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{ |
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return 0x18; |
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} |
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#define HOST1X_CHANNEL_DMAPUT \ |
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host1x_channel_dmaput_r() |
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static inline u32 host1x_channel_dmaget_r(void) |
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{ |
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return 0x1c; |
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} |
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#define HOST1X_CHANNEL_DMAGET \ |
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host1x_channel_dmaget_r() |
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static inline u32 host1x_channel_dmaend_r(void) |
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{ |
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return 0x20; |
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} |
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#define HOST1X_CHANNEL_DMAEND \ |
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host1x_channel_dmaend_r() |
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static inline u32 host1x_channel_dmactrl_r(void) |
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{ |
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return 0x24; |
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} |
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#define HOST1X_CHANNEL_DMACTRL \ |
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host1x_channel_dmactrl_r() |
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static inline u32 host1x_channel_dmactrl_dmastop(void) |
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{ |
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return 1 << 0; |
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} |
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#define HOST1X_CHANNEL_DMACTRL_DMASTOP \ |
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host1x_channel_dmactrl_dmastop() |
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static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r) |
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{ |
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return (r >> 0) & 0x1; |
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} |
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#define HOST1X_CHANNEL_DMACTRL_DMASTOP_V(r) \ |
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host1x_channel_dmactrl_dmastop_v(r) |
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static inline u32 host1x_channel_dmactrl_dmagetrst(void) |
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{ |
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return 1 << 1; |
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} |
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#define HOST1X_CHANNEL_DMACTRL_DMAGETRST \ |
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host1x_channel_dmactrl_dmagetrst() |
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static inline u32 host1x_channel_dmactrl_dmainitget(void) |
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{ |
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return 1 << 2; |
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} |
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#define HOST1X_CHANNEL_DMACTRL_DMAINITGET \ |
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host1x_channel_dmactrl_dmainitget() |
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#endif
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