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773 lines
19 KiB
773 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* timb_dma.c timberdale FPGA DMA driver |
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* Copyright (c) 2010 Intel Corporation |
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*/ |
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|
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/* Supports: |
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* Timberdale FPGA DMA engine |
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*/ |
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|
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#include <linux/dmaengine.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/timb_dma.h> |
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#include "dmaengine.h" |
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#define DRIVER_NAME "timb-dma" |
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/* Global DMA registers */ |
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#define TIMBDMA_ACR 0x34 |
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#define TIMBDMA_32BIT_ADDR 0x01 |
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#define TIMBDMA_ISR 0x080000 |
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#define TIMBDMA_IPR 0x080004 |
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#define TIMBDMA_IER 0x080008 |
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/* Channel specific registers */ |
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/* RX instances base addresses are 0x00, 0x40, 0x80 ... |
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* TX instances base addresses are 0x18, 0x58, 0x98 ... |
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*/ |
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#define TIMBDMA_INSTANCE_OFFSET 0x40 |
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#define TIMBDMA_INSTANCE_TX_OFFSET 0x18 |
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/* RX registers, relative the instance base */ |
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#define TIMBDMA_OFFS_RX_DHAR 0x00 |
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#define TIMBDMA_OFFS_RX_DLAR 0x04 |
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#define TIMBDMA_OFFS_RX_LR 0x0C |
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#define TIMBDMA_OFFS_RX_BLR 0x10 |
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#define TIMBDMA_OFFS_RX_ER 0x14 |
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#define TIMBDMA_RX_EN 0x01 |
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/* bytes per Row, video specific register |
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* which is placed after the TX registers... |
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*/ |
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#define TIMBDMA_OFFS_RX_BPRR 0x30 |
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/* TX registers, relative the instance base */ |
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#define TIMBDMA_OFFS_TX_DHAR 0x00 |
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#define TIMBDMA_OFFS_TX_DLAR 0x04 |
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#define TIMBDMA_OFFS_TX_BLR 0x0C |
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#define TIMBDMA_OFFS_TX_LR 0x14 |
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#define TIMB_DMA_DESC_SIZE 8 |
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struct timb_dma_desc { |
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struct list_head desc_node; |
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struct dma_async_tx_descriptor txd; |
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u8 *desc_list; |
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unsigned int desc_list_len; |
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bool interrupt; |
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}; |
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struct timb_dma_chan { |
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struct dma_chan chan; |
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void __iomem *membase; |
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spinlock_t lock; /* Used to protect data structures, |
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especially the lists and descriptors, |
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from races between the tasklet and calls |
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from above */ |
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bool ongoing; |
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struct list_head active_list; |
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struct list_head queue; |
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struct list_head free_list; |
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unsigned int bytes_per_line; |
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enum dma_transfer_direction direction; |
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unsigned int descs; /* Descriptors to allocate */ |
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unsigned int desc_elems; /* number of elems per descriptor */ |
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}; |
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struct timb_dma { |
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struct dma_device dma; |
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void __iomem *membase; |
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struct tasklet_struct tasklet; |
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struct timb_dma_chan channels[]; |
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}; |
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static struct device *chan2dev(struct dma_chan *chan) |
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{ |
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return &chan->dev->device; |
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} |
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static struct device *chan2dmadev(struct dma_chan *chan) |
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{ |
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return chan2dev(chan)->parent->parent; |
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} |
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static struct timb_dma *tdchantotd(struct timb_dma_chan *td_chan) |
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{ |
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int id = td_chan->chan.chan_id; |
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return (struct timb_dma *)((u8 *)td_chan - |
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id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma)); |
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} |
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/* Must be called with the spinlock held */ |
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static void __td_enable_chan_irq(struct timb_dma_chan *td_chan) |
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{ |
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int id = td_chan->chan.chan_id; |
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struct timb_dma *td = tdchantotd(td_chan); |
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u32 ier; |
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/* enable interrupt for this channel */ |
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ier = ioread32(td->membase + TIMBDMA_IER); |
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ier |= 1 << id; |
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dev_dbg(chan2dev(&td_chan->chan), "Enabling irq: %d, IER: 0x%x\n", id, |
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ier); |
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iowrite32(ier, td->membase + TIMBDMA_IER); |
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} |
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/* Should be called with the spinlock held */ |
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static bool __td_dma_done_ack(struct timb_dma_chan *td_chan) |
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{ |
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int id = td_chan->chan.chan_id; |
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struct timb_dma *td = (struct timb_dma *)((u8 *)td_chan - |
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id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma)); |
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u32 isr; |
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bool done = false; |
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dev_dbg(chan2dev(&td_chan->chan), "Checking irq: %d, td: %p\n", id, td); |
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isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id); |
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if (isr) { |
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iowrite32(isr, td->membase + TIMBDMA_ISR); |
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done = true; |
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} |
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return done; |
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} |
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static int td_fill_desc(struct timb_dma_chan *td_chan, u8 *dma_desc, |
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struct scatterlist *sg, bool last) |
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{ |
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if (sg_dma_len(sg) > USHRT_MAX) { |
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dev_err(chan2dev(&td_chan->chan), "Too big sg element\n"); |
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return -EINVAL; |
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} |
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/* length must be word aligned */ |
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if (sg_dma_len(sg) % sizeof(u32)) { |
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dev_err(chan2dev(&td_chan->chan), "Incorrect length: %d\n", |
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sg_dma_len(sg)); |
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return -EINVAL; |
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} |
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dev_dbg(chan2dev(&td_chan->chan), "desc: %p, addr: 0x%llx\n", |
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dma_desc, (unsigned long long)sg_dma_address(sg)); |
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dma_desc[7] = (sg_dma_address(sg) >> 24) & 0xff; |
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dma_desc[6] = (sg_dma_address(sg) >> 16) & 0xff; |
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dma_desc[5] = (sg_dma_address(sg) >> 8) & 0xff; |
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dma_desc[4] = (sg_dma_address(sg) >> 0) & 0xff; |
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dma_desc[3] = (sg_dma_len(sg) >> 8) & 0xff; |
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dma_desc[2] = (sg_dma_len(sg) >> 0) & 0xff; |
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dma_desc[1] = 0x00; |
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dma_desc[0] = 0x21 | (last ? 0x02 : 0); /* tran, valid */ |
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return 0; |
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} |
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/* Must be called with the spinlock held */ |
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static void __td_start_dma(struct timb_dma_chan *td_chan) |
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{ |
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struct timb_dma_desc *td_desc; |
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if (td_chan->ongoing) { |
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dev_err(chan2dev(&td_chan->chan), |
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"Transfer already ongoing\n"); |
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return; |
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} |
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td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc, |
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desc_node); |
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dev_dbg(chan2dev(&td_chan->chan), |
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"td_chan: %p, chan: %d, membase: %p\n", |
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td_chan, td_chan->chan.chan_id, td_chan->membase); |
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if (td_chan->direction == DMA_DEV_TO_MEM) { |
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/* descriptor address */ |
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iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); |
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iowrite32(td_desc->txd.phys, td_chan->membase + |
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TIMBDMA_OFFS_RX_DLAR); |
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/* Bytes per line */ |
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iowrite32(td_chan->bytes_per_line, td_chan->membase + |
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TIMBDMA_OFFS_RX_BPRR); |
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/* enable RX */ |
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iowrite32(TIMBDMA_RX_EN, td_chan->membase + TIMBDMA_OFFS_RX_ER); |
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} else { |
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/* address high */ |
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iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DHAR); |
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iowrite32(td_desc->txd.phys, td_chan->membase + |
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TIMBDMA_OFFS_TX_DLAR); |
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} |
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td_chan->ongoing = true; |
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if (td_desc->interrupt) |
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__td_enable_chan_irq(td_chan); |
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} |
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static void __td_finish(struct timb_dma_chan *td_chan) |
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{ |
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struct dmaengine_desc_callback cb; |
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struct dma_async_tx_descriptor *txd; |
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struct timb_dma_desc *td_desc; |
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/* can happen if the descriptor is canceled */ |
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if (list_empty(&td_chan->active_list)) |
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return; |
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td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc, |
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desc_node); |
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txd = &td_desc->txd; |
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dev_dbg(chan2dev(&td_chan->chan), "descriptor %u complete\n", |
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txd->cookie); |
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/* make sure to stop the transfer */ |
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if (td_chan->direction == DMA_DEV_TO_MEM) |
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iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER); |
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/* Currently no support for stopping DMA transfers |
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else |
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iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR); |
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*/ |
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dma_cookie_complete(txd); |
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td_chan->ongoing = false; |
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dmaengine_desc_get_callback(txd, &cb); |
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list_move(&td_desc->desc_node, &td_chan->free_list); |
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dma_descriptor_unmap(txd); |
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/* |
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* The API requires that no submissions are done from a |
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* callback, so we don't need to drop the lock here |
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*/ |
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dmaengine_desc_callback_invoke(&cb, NULL); |
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} |
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static u32 __td_ier_mask(struct timb_dma *td) |
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{ |
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int i; |
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u32 ret = 0; |
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for (i = 0; i < td->dma.chancnt; i++) { |
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struct timb_dma_chan *td_chan = td->channels + i; |
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if (td_chan->ongoing) { |
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struct timb_dma_desc *td_desc = |
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list_entry(td_chan->active_list.next, |
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struct timb_dma_desc, desc_node); |
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if (td_desc->interrupt) |
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ret |= 1 << i; |
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} |
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} |
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return ret; |
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} |
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static void __td_start_next(struct timb_dma_chan *td_chan) |
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{ |
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struct timb_dma_desc *td_desc; |
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BUG_ON(list_empty(&td_chan->queue)); |
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BUG_ON(td_chan->ongoing); |
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td_desc = list_entry(td_chan->queue.next, struct timb_dma_desc, |
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desc_node); |
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dev_dbg(chan2dev(&td_chan->chan), "%s: started %u\n", |
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__func__, td_desc->txd.cookie); |
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list_move(&td_desc->desc_node, &td_chan->active_list); |
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__td_start_dma(td_chan); |
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} |
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static dma_cookie_t td_tx_submit(struct dma_async_tx_descriptor *txd) |
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{ |
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struct timb_dma_desc *td_desc = container_of(txd, struct timb_dma_desc, |
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txd); |
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struct timb_dma_chan *td_chan = container_of(txd->chan, |
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struct timb_dma_chan, chan); |
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dma_cookie_t cookie; |
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spin_lock_bh(&td_chan->lock); |
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cookie = dma_cookie_assign(txd); |
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if (list_empty(&td_chan->active_list)) { |
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dev_dbg(chan2dev(txd->chan), "%s: started %u\n", __func__, |
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txd->cookie); |
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list_add_tail(&td_desc->desc_node, &td_chan->active_list); |
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__td_start_dma(td_chan); |
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} else { |
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dev_dbg(chan2dev(txd->chan), "tx_submit: queued %u\n", |
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txd->cookie); |
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list_add_tail(&td_desc->desc_node, &td_chan->queue); |
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} |
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spin_unlock_bh(&td_chan->lock); |
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return cookie; |
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} |
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static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan) |
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{ |
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struct dma_chan *chan = &td_chan->chan; |
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struct timb_dma_desc *td_desc; |
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int err; |
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td_desc = kzalloc(sizeof(struct timb_dma_desc), GFP_KERNEL); |
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if (!td_desc) |
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goto out; |
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td_desc->desc_list_len = td_chan->desc_elems * TIMB_DMA_DESC_SIZE; |
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td_desc->desc_list = kzalloc(td_desc->desc_list_len, GFP_KERNEL); |
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if (!td_desc->desc_list) |
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goto err; |
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dma_async_tx_descriptor_init(&td_desc->txd, chan); |
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td_desc->txd.tx_submit = td_tx_submit; |
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td_desc->txd.flags = DMA_CTRL_ACK; |
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td_desc->txd.phys = dma_map_single(chan2dmadev(chan), |
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td_desc->desc_list, td_desc->desc_list_len, DMA_TO_DEVICE); |
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err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys); |
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if (err) { |
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dev_err(chan2dev(chan), "DMA mapping error: %d\n", err); |
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goto err; |
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} |
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return td_desc; |
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err: |
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kfree(td_desc->desc_list); |
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kfree(td_desc); |
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out: |
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return NULL; |
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} |
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static void td_free_desc(struct timb_dma_desc *td_desc) |
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{ |
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dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc); |
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dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys, |
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td_desc->desc_list_len, DMA_TO_DEVICE); |
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kfree(td_desc->desc_list); |
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kfree(td_desc); |
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} |
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static void td_desc_put(struct timb_dma_chan *td_chan, |
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struct timb_dma_desc *td_desc) |
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{ |
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dev_dbg(chan2dev(&td_chan->chan), "Putting desc: %p\n", td_desc); |
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spin_lock_bh(&td_chan->lock); |
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list_add(&td_desc->desc_node, &td_chan->free_list); |
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spin_unlock_bh(&td_chan->lock); |
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} |
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static struct timb_dma_desc *td_desc_get(struct timb_dma_chan *td_chan) |
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{ |
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struct timb_dma_desc *td_desc, *_td_desc; |
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struct timb_dma_desc *ret = NULL; |
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spin_lock_bh(&td_chan->lock); |
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list_for_each_entry_safe(td_desc, _td_desc, &td_chan->free_list, |
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desc_node) { |
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if (async_tx_test_ack(&td_desc->txd)) { |
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list_del(&td_desc->desc_node); |
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ret = td_desc; |
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break; |
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} |
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dev_dbg(chan2dev(&td_chan->chan), "desc %p not ACKed\n", |
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td_desc); |
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} |
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spin_unlock_bh(&td_chan->lock); |
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return ret; |
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} |
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static int td_alloc_chan_resources(struct dma_chan *chan) |
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{ |
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struct timb_dma_chan *td_chan = |
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container_of(chan, struct timb_dma_chan, chan); |
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int i; |
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dev_dbg(chan2dev(chan), "%s: entry\n", __func__); |
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BUG_ON(!list_empty(&td_chan->free_list)); |
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for (i = 0; i < td_chan->descs; i++) { |
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struct timb_dma_desc *td_desc = td_alloc_init_desc(td_chan); |
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if (!td_desc) { |
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if (i) |
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break; |
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else { |
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dev_err(chan2dev(chan), |
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"Couldn't allocate any descriptors\n"); |
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return -ENOMEM; |
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} |
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} |
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td_desc_put(td_chan, td_desc); |
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} |
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spin_lock_bh(&td_chan->lock); |
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dma_cookie_init(chan); |
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spin_unlock_bh(&td_chan->lock); |
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return 0; |
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} |
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static void td_free_chan_resources(struct dma_chan *chan) |
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{ |
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struct timb_dma_chan *td_chan = |
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container_of(chan, struct timb_dma_chan, chan); |
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struct timb_dma_desc *td_desc, *_td_desc; |
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LIST_HEAD(list); |
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dev_dbg(chan2dev(chan), "%s: Entry\n", __func__); |
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/* check that all descriptors are free */ |
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BUG_ON(!list_empty(&td_chan->active_list)); |
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BUG_ON(!list_empty(&td_chan->queue)); |
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spin_lock_bh(&td_chan->lock); |
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list_splice_init(&td_chan->free_list, &list); |
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spin_unlock_bh(&td_chan->lock); |
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list_for_each_entry_safe(td_desc, _td_desc, &list, desc_node) { |
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dev_dbg(chan2dev(chan), "%s: Freeing desc: %p\n", __func__, |
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td_desc); |
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td_free_desc(td_desc); |
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} |
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} |
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static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie, |
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struct dma_tx_state *txstate) |
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{ |
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enum dma_status ret; |
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dev_dbg(chan2dev(chan), "%s: Entry\n", __func__); |
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ret = dma_cookie_status(chan, cookie, txstate); |
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dev_dbg(chan2dev(chan), "%s: exit, ret: %d\n", __func__, ret); |
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return ret; |
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} |
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static void td_issue_pending(struct dma_chan *chan) |
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{ |
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struct timb_dma_chan *td_chan = |
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container_of(chan, struct timb_dma_chan, chan); |
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dev_dbg(chan2dev(chan), "%s: Entry\n", __func__); |
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spin_lock_bh(&td_chan->lock); |
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if (!list_empty(&td_chan->active_list)) |
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/* transfer ongoing */ |
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if (__td_dma_done_ack(td_chan)) |
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__td_finish(td_chan); |
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if (list_empty(&td_chan->active_list) && !list_empty(&td_chan->queue)) |
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__td_start_next(td_chan); |
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spin_unlock_bh(&td_chan->lock); |
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} |
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static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan, |
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struct scatterlist *sgl, unsigned int sg_len, |
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enum dma_transfer_direction direction, unsigned long flags, |
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void *context) |
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{ |
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struct timb_dma_chan *td_chan = |
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container_of(chan, struct timb_dma_chan, chan); |
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struct timb_dma_desc *td_desc; |
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struct scatterlist *sg; |
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unsigned int i; |
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unsigned int desc_usage = 0; |
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if (!sgl || !sg_len) { |
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dev_err(chan2dev(chan), "%s: No SG list\n", __func__); |
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return NULL; |
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} |
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/* even channels are for RX, odd for TX */ |
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if (td_chan->direction != direction) { |
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dev_err(chan2dev(chan), |
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"Requesting channel in wrong direction\n"); |
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return NULL; |
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} |
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td_desc = td_desc_get(td_chan); |
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if (!td_desc) { |
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dev_err(chan2dev(chan), "Not enough descriptors available\n"); |
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return NULL; |
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} |
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td_desc->interrupt = (flags & DMA_PREP_INTERRUPT) != 0; |
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for_each_sg(sgl, sg, sg_len, i) { |
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int err; |
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if (desc_usage > td_desc->desc_list_len) { |
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dev_err(chan2dev(chan), "No descriptor space\n"); |
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return NULL; |
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} |
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err = td_fill_desc(td_chan, td_desc->desc_list + desc_usage, sg, |
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i == (sg_len - 1)); |
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if (err) { |
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dev_err(chan2dev(chan), "Failed to update desc: %d\n", |
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err); |
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td_desc_put(td_chan, td_desc); |
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return NULL; |
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} |
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desc_usage += TIMB_DMA_DESC_SIZE; |
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} |
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dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys, |
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td_desc->desc_list_len, DMA_TO_DEVICE); |
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|
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return &td_desc->txd; |
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} |
|
|
|
static int td_terminate_all(struct dma_chan *chan) |
|
{ |
|
struct timb_dma_chan *td_chan = |
|
container_of(chan, struct timb_dma_chan, chan); |
|
struct timb_dma_desc *td_desc, *_td_desc; |
|
|
|
dev_dbg(chan2dev(chan), "%s: Entry\n", __func__); |
|
|
|
/* first the easy part, put the queue into the free list */ |
|
spin_lock_bh(&td_chan->lock); |
|
list_for_each_entry_safe(td_desc, _td_desc, &td_chan->queue, |
|
desc_node) |
|
list_move(&td_desc->desc_node, &td_chan->free_list); |
|
|
|
/* now tear down the running */ |
|
__td_finish(td_chan); |
|
spin_unlock_bh(&td_chan->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static void td_tasklet(struct tasklet_struct *t) |
|
{ |
|
struct timb_dma *td = from_tasklet(td, t, tasklet); |
|
u32 isr; |
|
u32 ipr; |
|
u32 ier; |
|
int i; |
|
|
|
isr = ioread32(td->membase + TIMBDMA_ISR); |
|
ipr = isr & __td_ier_mask(td); |
|
|
|
/* ack the interrupts */ |
|
iowrite32(ipr, td->membase + TIMBDMA_ISR); |
|
|
|
for (i = 0; i < td->dma.chancnt; i++) |
|
if (ipr & (1 << i)) { |
|
struct timb_dma_chan *td_chan = td->channels + i; |
|
spin_lock(&td_chan->lock); |
|
__td_finish(td_chan); |
|
if (!list_empty(&td_chan->queue)) |
|
__td_start_next(td_chan); |
|
spin_unlock(&td_chan->lock); |
|
} |
|
|
|
ier = __td_ier_mask(td); |
|
iowrite32(ier, td->membase + TIMBDMA_IER); |
|
} |
|
|
|
|
|
static irqreturn_t td_irq(int irq, void *devid) |
|
{ |
|
struct timb_dma *td = devid; |
|
u32 ipr = ioread32(td->membase + TIMBDMA_IPR); |
|
|
|
if (ipr) { |
|
/* disable interrupts, will be re-enabled in tasklet */ |
|
iowrite32(0, td->membase + TIMBDMA_IER); |
|
|
|
tasklet_schedule(&td->tasklet); |
|
|
|
return IRQ_HANDLED; |
|
} else |
|
return IRQ_NONE; |
|
} |
|
|
|
|
|
static int td_probe(struct platform_device *pdev) |
|
{ |
|
struct timb_dma_platform_data *pdata = dev_get_platdata(&pdev->dev); |
|
struct timb_dma *td; |
|
struct resource *iomem; |
|
int irq; |
|
int err; |
|
int i; |
|
|
|
if (!pdata) { |
|
dev_err(&pdev->dev, "No platform data\n"); |
|
return -EINVAL; |
|
} |
|
|
|
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
if (!iomem) |
|
return -EINVAL; |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return irq; |
|
|
|
if (!request_mem_region(iomem->start, resource_size(iomem), |
|
DRIVER_NAME)) |
|
return -EBUSY; |
|
|
|
td = kzalloc(struct_size(td, channels, pdata->nr_channels), |
|
GFP_KERNEL); |
|
if (!td) { |
|
err = -ENOMEM; |
|
goto err_release_region; |
|
} |
|
|
|
dev_dbg(&pdev->dev, "Allocated TD: %p\n", td); |
|
|
|
td->membase = ioremap(iomem->start, resource_size(iomem)); |
|
if (!td->membase) { |
|
dev_err(&pdev->dev, "Failed to remap I/O memory\n"); |
|
err = -ENOMEM; |
|
goto err_free_mem; |
|
} |
|
|
|
/* 32bit addressing */ |
|
iowrite32(TIMBDMA_32BIT_ADDR, td->membase + TIMBDMA_ACR); |
|
|
|
/* disable and clear any interrupts */ |
|
iowrite32(0x0, td->membase + TIMBDMA_IER); |
|
iowrite32(0xFFFFFFFF, td->membase + TIMBDMA_ISR); |
|
|
|
tasklet_setup(&td->tasklet, td_tasklet); |
|
|
|
err = request_irq(irq, td_irq, IRQF_SHARED, DRIVER_NAME, td); |
|
if (err) { |
|
dev_err(&pdev->dev, "Failed to request IRQ\n"); |
|
goto err_tasklet_kill; |
|
} |
|
|
|
td->dma.device_alloc_chan_resources = td_alloc_chan_resources; |
|
td->dma.device_free_chan_resources = td_free_chan_resources; |
|
td->dma.device_tx_status = td_tx_status; |
|
td->dma.device_issue_pending = td_issue_pending; |
|
|
|
dma_cap_set(DMA_SLAVE, td->dma.cap_mask); |
|
dma_cap_set(DMA_PRIVATE, td->dma.cap_mask); |
|
td->dma.device_prep_slave_sg = td_prep_slave_sg; |
|
td->dma.device_terminate_all = td_terminate_all; |
|
|
|
td->dma.dev = &pdev->dev; |
|
|
|
INIT_LIST_HEAD(&td->dma.channels); |
|
|
|
for (i = 0; i < pdata->nr_channels; i++) { |
|
struct timb_dma_chan *td_chan = &td->channels[i]; |
|
struct timb_dma_platform_data_channel *pchan = |
|
pdata->channels + i; |
|
|
|
/* even channels are RX, odd are TX */ |
|
if ((i % 2) == pchan->rx) { |
|
dev_err(&pdev->dev, "Wrong channel configuration\n"); |
|
err = -EINVAL; |
|
goto err_free_irq; |
|
} |
|
|
|
td_chan->chan.device = &td->dma; |
|
dma_cookie_init(&td_chan->chan); |
|
spin_lock_init(&td_chan->lock); |
|
INIT_LIST_HEAD(&td_chan->active_list); |
|
INIT_LIST_HEAD(&td_chan->queue); |
|
INIT_LIST_HEAD(&td_chan->free_list); |
|
|
|
td_chan->descs = pchan->descriptors; |
|
td_chan->desc_elems = pchan->descriptor_elements; |
|
td_chan->bytes_per_line = pchan->bytes_per_line; |
|
td_chan->direction = pchan->rx ? DMA_DEV_TO_MEM : |
|
DMA_MEM_TO_DEV; |
|
|
|
td_chan->membase = td->membase + |
|
(i / 2) * TIMBDMA_INSTANCE_OFFSET + |
|
(pchan->rx ? 0 : TIMBDMA_INSTANCE_TX_OFFSET); |
|
|
|
dev_dbg(&pdev->dev, "Chan: %d, membase: %p\n", |
|
i, td_chan->membase); |
|
|
|
list_add_tail(&td_chan->chan.device_node, &td->dma.channels); |
|
} |
|
|
|
err = dma_async_device_register(&td->dma); |
|
if (err) { |
|
dev_err(&pdev->dev, "Failed to register async device\n"); |
|
goto err_free_irq; |
|
} |
|
|
|
platform_set_drvdata(pdev, td); |
|
|
|
dev_dbg(&pdev->dev, "Probe result: %d\n", err); |
|
return err; |
|
|
|
err_free_irq: |
|
free_irq(irq, td); |
|
err_tasklet_kill: |
|
tasklet_kill(&td->tasklet); |
|
iounmap(td->membase); |
|
err_free_mem: |
|
kfree(td); |
|
err_release_region: |
|
release_mem_region(iomem->start, resource_size(iomem)); |
|
|
|
return err; |
|
|
|
} |
|
|
|
static int td_remove(struct platform_device *pdev) |
|
{ |
|
struct timb_dma *td = platform_get_drvdata(pdev); |
|
struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
int irq = platform_get_irq(pdev, 0); |
|
|
|
dma_async_device_unregister(&td->dma); |
|
free_irq(irq, td); |
|
tasklet_kill(&td->tasklet); |
|
iounmap(td->membase); |
|
kfree(td); |
|
release_mem_region(iomem->start, resource_size(iomem)); |
|
|
|
dev_dbg(&pdev->dev, "Removed...\n"); |
|
return 0; |
|
} |
|
|
|
static struct platform_driver td_driver = { |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
}, |
|
.probe = td_probe, |
|
.remove = td_remove, |
|
}; |
|
|
|
module_platform_driver(td_driver); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("Timberdale DMA controller driver"); |
|
MODULE_AUTHOR("Pelagicore AB <[email protected]>"); |
|
MODULE_ALIAS("platform:"DRIVER_NAME);
|
|
|