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877 lines
22 KiB
877 lines
22 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* DMA driver for STMicroelectronics STi FDMA controller |
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* |
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* Copyright (C) 2014 STMicroelectronics |
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* |
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* Author: Ludovic Barre <[email protected]> |
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* Peter Griffin <[email protected]> |
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*/ |
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|
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/of_dma.h> |
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#include <linux/platform_device.h> |
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#include <linux/interrupt.h> |
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#include <linux/remoteproc.h> |
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#include <linux/slab.h> |
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#include "st_fdma.h" |
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static inline struct st_fdma_chan *to_st_fdma_chan(struct dma_chan *c) |
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{ |
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return container_of(c, struct st_fdma_chan, vchan.chan); |
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} |
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static struct st_fdma_desc *to_st_fdma_desc(struct virt_dma_desc *vd) |
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{ |
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return container_of(vd, struct st_fdma_desc, vdesc); |
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} |
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static int st_fdma_dreq_get(struct st_fdma_chan *fchan) |
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{ |
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struct st_fdma_dev *fdev = fchan->fdev; |
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u32 req_line_cfg = fchan->cfg.req_line; |
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u32 dreq_line; |
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int try = 0; |
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|
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/* |
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* dreq_mask is shared for n channels of fdma, so all accesses must be |
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* atomic. if the dreq_mask is changed between ffz and set_bit, |
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* we retry |
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*/ |
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do { |
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if (fdev->dreq_mask == ~0L) { |
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dev_err(fdev->dev, "No req lines available\n"); |
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return -EINVAL; |
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} |
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if (try || req_line_cfg >= ST_FDMA_NR_DREQS) { |
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dev_err(fdev->dev, "Invalid or used req line\n"); |
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return -EINVAL; |
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} else { |
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dreq_line = req_line_cfg; |
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} |
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try++; |
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} while (test_and_set_bit(dreq_line, &fdev->dreq_mask)); |
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dev_dbg(fdev->dev, "get dreq_line:%d mask:%#lx\n", |
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dreq_line, fdev->dreq_mask); |
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return dreq_line; |
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} |
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static void st_fdma_dreq_put(struct st_fdma_chan *fchan) |
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{ |
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struct st_fdma_dev *fdev = fchan->fdev; |
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dev_dbg(fdev->dev, "put dreq_line:%#x\n", fchan->dreq_line); |
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clear_bit(fchan->dreq_line, &fdev->dreq_mask); |
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} |
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static void st_fdma_xfer_desc(struct st_fdma_chan *fchan) |
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{ |
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struct virt_dma_desc *vdesc; |
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unsigned long nbytes, ch_cmd, cmd; |
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vdesc = vchan_next_desc(&fchan->vchan); |
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if (!vdesc) |
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return; |
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fchan->fdesc = to_st_fdma_desc(vdesc); |
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nbytes = fchan->fdesc->node[0].desc->nbytes; |
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cmd = FDMA_CMD_START(fchan->vchan.chan.chan_id); |
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ch_cmd = fchan->fdesc->node[0].pdesc | FDMA_CH_CMD_STA_START; |
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/* start the channel for the descriptor */ |
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fnode_write(fchan, nbytes, FDMA_CNTN_OFST); |
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fchan_write(fchan, ch_cmd, FDMA_CH_CMD_OFST); |
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writel(cmd, |
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fchan->fdev->slim_rproc->peri + FDMA_CMD_SET_OFST); |
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dev_dbg(fchan->fdev->dev, "start chan:%d\n", fchan->vchan.chan.chan_id); |
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} |
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static void st_fdma_ch_sta_update(struct st_fdma_chan *fchan, |
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unsigned long int_sta) |
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{ |
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unsigned long ch_sta, ch_err; |
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int ch_id = fchan->vchan.chan.chan_id; |
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struct st_fdma_dev *fdev = fchan->fdev; |
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ch_sta = fchan_read(fchan, FDMA_CH_CMD_OFST); |
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ch_err = ch_sta & FDMA_CH_CMD_ERR_MASK; |
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ch_sta &= FDMA_CH_CMD_STA_MASK; |
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if (int_sta & FDMA_INT_STA_ERR) { |
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dev_warn(fdev->dev, "chan:%d, error:%ld\n", ch_id, ch_err); |
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fchan->status = DMA_ERROR; |
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return; |
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} |
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switch (ch_sta) { |
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case FDMA_CH_CMD_STA_PAUSED: |
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fchan->status = DMA_PAUSED; |
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break; |
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case FDMA_CH_CMD_STA_RUNNING: |
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fchan->status = DMA_IN_PROGRESS; |
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break; |
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} |
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} |
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static irqreturn_t st_fdma_irq_handler(int irq, void *dev_id) |
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{ |
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struct st_fdma_dev *fdev = dev_id; |
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irqreturn_t ret = IRQ_NONE; |
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struct st_fdma_chan *fchan = &fdev->chans[0]; |
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unsigned long int_sta, clr; |
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int_sta = fdma_read(fdev, FDMA_INT_STA_OFST); |
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clr = int_sta; |
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for (; int_sta != 0 ; int_sta >>= 2, fchan++) { |
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if (!(int_sta & (FDMA_INT_STA_CH | FDMA_INT_STA_ERR))) |
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continue; |
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spin_lock(&fchan->vchan.lock); |
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st_fdma_ch_sta_update(fchan, int_sta); |
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if (fchan->fdesc) { |
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if (!fchan->fdesc->iscyclic) { |
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list_del(&fchan->fdesc->vdesc.node); |
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vchan_cookie_complete(&fchan->fdesc->vdesc); |
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fchan->fdesc = NULL; |
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fchan->status = DMA_COMPLETE; |
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} else { |
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vchan_cyclic_callback(&fchan->fdesc->vdesc); |
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} |
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/* Start the next descriptor (if available) */ |
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if (!fchan->fdesc) |
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st_fdma_xfer_desc(fchan); |
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} |
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spin_unlock(&fchan->vchan.lock); |
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ret = IRQ_HANDLED; |
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} |
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fdma_write(fdev, clr, FDMA_INT_CLR_OFST); |
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return ret; |
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} |
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static struct dma_chan *st_fdma_of_xlate(struct of_phandle_args *dma_spec, |
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struct of_dma *ofdma) |
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{ |
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struct st_fdma_dev *fdev = ofdma->of_dma_data; |
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struct dma_chan *chan; |
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struct st_fdma_chan *fchan; |
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int ret; |
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if (dma_spec->args_count < 1) |
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return ERR_PTR(-EINVAL); |
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if (fdev->dma_device.dev->of_node != dma_spec->np) |
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return ERR_PTR(-EINVAL); |
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ret = rproc_boot(fdev->slim_rproc->rproc); |
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if (ret == -ENOENT) |
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return ERR_PTR(-EPROBE_DEFER); |
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else if (ret) |
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return ERR_PTR(ret); |
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chan = dma_get_any_slave_channel(&fdev->dma_device); |
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if (!chan) |
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goto err_chan; |
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fchan = to_st_fdma_chan(chan); |
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fchan->cfg.of_node = dma_spec->np; |
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fchan->cfg.req_line = dma_spec->args[0]; |
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fchan->cfg.req_ctrl = 0; |
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fchan->cfg.type = ST_FDMA_TYPE_FREE_RUN; |
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if (dma_spec->args_count > 1) |
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fchan->cfg.req_ctrl = dma_spec->args[1] |
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& FDMA_REQ_CTRL_CFG_MASK; |
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if (dma_spec->args_count > 2) |
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fchan->cfg.type = dma_spec->args[2]; |
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if (fchan->cfg.type == ST_FDMA_TYPE_FREE_RUN) { |
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fchan->dreq_line = 0; |
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} else { |
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fchan->dreq_line = st_fdma_dreq_get(fchan); |
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if (IS_ERR_VALUE(fchan->dreq_line)) { |
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chan = ERR_PTR(fchan->dreq_line); |
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goto err_chan; |
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} |
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} |
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dev_dbg(fdev->dev, "xlate req_line:%d type:%d req_ctrl:%#lx\n", |
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fchan->cfg.req_line, fchan->cfg.type, fchan->cfg.req_ctrl); |
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return chan; |
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err_chan: |
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rproc_shutdown(fdev->slim_rproc->rproc); |
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return chan; |
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} |
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static void st_fdma_free_desc(struct virt_dma_desc *vdesc) |
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{ |
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struct st_fdma_desc *fdesc; |
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int i; |
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fdesc = to_st_fdma_desc(vdesc); |
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for (i = 0; i < fdesc->n_nodes; i++) |
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dma_pool_free(fdesc->fchan->node_pool, fdesc->node[i].desc, |
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fdesc->node[i].pdesc); |
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kfree(fdesc); |
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} |
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static struct st_fdma_desc *st_fdma_alloc_desc(struct st_fdma_chan *fchan, |
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int sg_len) |
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{ |
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struct st_fdma_desc *fdesc; |
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int i; |
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fdesc = kzalloc(struct_size(fdesc, node, sg_len), GFP_NOWAIT); |
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if (!fdesc) |
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return NULL; |
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fdesc->fchan = fchan; |
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fdesc->n_nodes = sg_len; |
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for (i = 0; i < sg_len; i++) { |
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fdesc->node[i].desc = dma_pool_alloc(fchan->node_pool, |
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GFP_NOWAIT, &fdesc->node[i].pdesc); |
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if (!fdesc->node[i].desc) |
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goto err; |
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} |
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return fdesc; |
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err: |
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while (--i >= 0) |
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dma_pool_free(fchan->node_pool, fdesc->node[i].desc, |
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fdesc->node[i].pdesc); |
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kfree(fdesc); |
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return NULL; |
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} |
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static int st_fdma_alloc_chan_res(struct dma_chan *chan) |
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{ |
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struct st_fdma_chan *fchan = to_st_fdma_chan(chan); |
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/* Create the dma pool for descriptor allocation */ |
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fchan->node_pool = dma_pool_create(dev_name(&chan->dev->device), |
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fchan->fdev->dev, |
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sizeof(struct st_fdma_hw_node), |
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__alignof__(struct st_fdma_hw_node), |
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0); |
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if (!fchan->node_pool) { |
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dev_err(fchan->fdev->dev, "unable to allocate desc pool\n"); |
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return -ENOMEM; |
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} |
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dev_dbg(fchan->fdev->dev, "alloc ch_id:%d type:%d\n", |
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fchan->vchan.chan.chan_id, fchan->cfg.type); |
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return 0; |
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} |
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static void st_fdma_free_chan_res(struct dma_chan *chan) |
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{ |
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struct st_fdma_chan *fchan = to_st_fdma_chan(chan); |
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struct rproc *rproc = fchan->fdev->slim_rproc->rproc; |
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unsigned long flags; |
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dev_dbg(fchan->fdev->dev, "%s: freeing chan:%d\n", |
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__func__, fchan->vchan.chan.chan_id); |
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if (fchan->cfg.type != ST_FDMA_TYPE_FREE_RUN) |
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st_fdma_dreq_put(fchan); |
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spin_lock_irqsave(&fchan->vchan.lock, flags); |
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fchan->fdesc = NULL; |
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spin_unlock_irqrestore(&fchan->vchan.lock, flags); |
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dma_pool_destroy(fchan->node_pool); |
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fchan->node_pool = NULL; |
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memset(&fchan->cfg, 0, sizeof(struct st_fdma_cfg)); |
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rproc_shutdown(rproc); |
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} |
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static struct dma_async_tx_descriptor *st_fdma_prep_dma_memcpy( |
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struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, |
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size_t len, unsigned long flags) |
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{ |
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struct st_fdma_chan *fchan; |
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struct st_fdma_desc *fdesc; |
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struct st_fdma_hw_node *hw_node; |
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if (!len) |
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return NULL; |
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fchan = to_st_fdma_chan(chan); |
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/* We only require a single descriptor */ |
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fdesc = st_fdma_alloc_desc(fchan, 1); |
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if (!fdesc) { |
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dev_err(fchan->fdev->dev, "no memory for desc\n"); |
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return NULL; |
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} |
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hw_node = fdesc->node[0].desc; |
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hw_node->next = 0; |
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hw_node->control = FDMA_NODE_CTRL_REQ_MAP_FREE_RUN; |
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hw_node->control |= FDMA_NODE_CTRL_SRC_INCR; |
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hw_node->control |= FDMA_NODE_CTRL_DST_INCR; |
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hw_node->control |= FDMA_NODE_CTRL_INT_EON; |
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hw_node->nbytes = len; |
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hw_node->saddr = src; |
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hw_node->daddr = dst; |
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hw_node->generic.length = len; |
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hw_node->generic.sstride = 0; |
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hw_node->generic.dstride = 0; |
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return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags); |
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} |
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static int config_reqctrl(struct st_fdma_chan *fchan, |
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enum dma_transfer_direction direction) |
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{ |
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u32 maxburst = 0, addr = 0; |
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enum dma_slave_buswidth width; |
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int ch_id = fchan->vchan.chan.chan_id; |
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struct st_fdma_dev *fdev = fchan->fdev; |
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switch (direction) { |
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case DMA_DEV_TO_MEM: |
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fchan->cfg.req_ctrl &= ~FDMA_REQ_CTRL_WNR; |
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maxburst = fchan->scfg.src_maxburst; |
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width = fchan->scfg.src_addr_width; |
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addr = fchan->scfg.src_addr; |
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break; |
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case DMA_MEM_TO_DEV: |
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fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_WNR; |
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maxburst = fchan->scfg.dst_maxburst; |
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width = fchan->scfg.dst_addr_width; |
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addr = fchan->scfg.dst_addr; |
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break; |
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default: |
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return -EINVAL; |
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} |
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fchan->cfg.req_ctrl &= ~FDMA_REQ_CTRL_OPCODE_MASK; |
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switch (width) { |
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case DMA_SLAVE_BUSWIDTH_1_BYTE: |
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fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST1; |
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break; |
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case DMA_SLAVE_BUSWIDTH_2_BYTES: |
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fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST2; |
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break; |
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case DMA_SLAVE_BUSWIDTH_4_BYTES: |
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fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST4; |
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break; |
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case DMA_SLAVE_BUSWIDTH_8_BYTES: |
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fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST8; |
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break; |
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default: |
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return -EINVAL; |
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} |
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fchan->cfg.req_ctrl &= ~FDMA_REQ_CTRL_NUM_OPS_MASK; |
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fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_NUM_OPS(maxburst-1); |
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dreq_write(fchan, fchan->cfg.req_ctrl, FDMA_REQ_CTRL_OFST); |
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fchan->cfg.dev_addr = addr; |
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fchan->cfg.dir = direction; |
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dev_dbg(fdev->dev, "chan:%d config_reqctrl:%#x req_ctrl:%#lx\n", |
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ch_id, addr, fchan->cfg.req_ctrl); |
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return 0; |
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} |
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static void fill_hw_node(struct st_fdma_hw_node *hw_node, |
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struct st_fdma_chan *fchan, |
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enum dma_transfer_direction direction) |
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{ |
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if (direction == DMA_MEM_TO_DEV) { |
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hw_node->control |= FDMA_NODE_CTRL_SRC_INCR; |
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hw_node->control |= FDMA_NODE_CTRL_DST_STATIC; |
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hw_node->daddr = fchan->cfg.dev_addr; |
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} else { |
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hw_node->control |= FDMA_NODE_CTRL_SRC_STATIC; |
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hw_node->control |= FDMA_NODE_CTRL_DST_INCR; |
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hw_node->saddr = fchan->cfg.dev_addr; |
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} |
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hw_node->generic.sstride = 0; |
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hw_node->generic.dstride = 0; |
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} |
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static inline struct st_fdma_chan *st_fdma_prep_common(struct dma_chan *chan, |
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size_t len, enum dma_transfer_direction direction) |
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{ |
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struct st_fdma_chan *fchan; |
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if (!chan || !len) |
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return NULL; |
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fchan = to_st_fdma_chan(chan); |
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if (!is_slave_direction(direction)) { |
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dev_err(fchan->fdev->dev, "bad direction?\n"); |
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return NULL; |
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} |
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return fchan; |
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} |
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static struct dma_async_tx_descriptor *st_fdma_prep_dma_cyclic( |
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struct dma_chan *chan, dma_addr_t buf_addr, size_t len, |
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size_t period_len, enum dma_transfer_direction direction, |
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unsigned long flags) |
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{ |
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struct st_fdma_chan *fchan; |
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struct st_fdma_desc *fdesc; |
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int sg_len, i; |
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fchan = st_fdma_prep_common(chan, len, direction); |
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if (!fchan) |
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return NULL; |
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if (!period_len) |
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return NULL; |
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if (config_reqctrl(fchan, direction)) { |
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dev_err(fchan->fdev->dev, "bad width or direction\n"); |
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return NULL; |
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} |
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/* the buffer length must be a multiple of period_len */ |
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if (len % period_len != 0) { |
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dev_err(fchan->fdev->dev, "len is not multiple of period\n"); |
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return NULL; |
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} |
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sg_len = len / period_len; |
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fdesc = st_fdma_alloc_desc(fchan, sg_len); |
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if (!fdesc) { |
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dev_err(fchan->fdev->dev, "no memory for desc\n"); |
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return NULL; |
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} |
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fdesc->iscyclic = true; |
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for (i = 0; i < sg_len; i++) { |
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struct st_fdma_hw_node *hw_node = fdesc->node[i].desc; |
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hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc; |
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hw_node->control = |
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FDMA_NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line); |
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hw_node->control |= FDMA_NODE_CTRL_INT_EON; |
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fill_hw_node(hw_node, fchan, direction); |
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if (direction == DMA_MEM_TO_DEV) |
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hw_node->saddr = buf_addr + (i * period_len); |
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else |
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hw_node->daddr = buf_addr + (i * period_len); |
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hw_node->nbytes = period_len; |
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hw_node->generic.length = period_len; |
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} |
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return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags); |
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} |
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static struct dma_async_tx_descriptor *st_fdma_prep_slave_sg( |
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struct dma_chan *chan, struct scatterlist *sgl, |
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unsigned int sg_len, enum dma_transfer_direction direction, |
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unsigned long flags, void *context) |
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{ |
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struct st_fdma_chan *fchan; |
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struct st_fdma_desc *fdesc; |
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struct st_fdma_hw_node *hw_node; |
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struct scatterlist *sg; |
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int i; |
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fchan = st_fdma_prep_common(chan, sg_len, direction); |
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if (!fchan) |
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return NULL; |
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|
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if (!sgl) |
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return NULL; |
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fdesc = st_fdma_alloc_desc(fchan, sg_len); |
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if (!fdesc) { |
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dev_err(fchan->fdev->dev, "no memory for desc\n"); |
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return NULL; |
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} |
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fdesc->iscyclic = false; |
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for_each_sg(sgl, sg, sg_len, i) { |
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hw_node = fdesc->node[i].desc; |
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|
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hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc; |
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hw_node->control = FDMA_NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line); |
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|
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fill_hw_node(hw_node, fchan, direction); |
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|
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if (direction == DMA_MEM_TO_DEV) |
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hw_node->saddr = sg_dma_address(sg); |
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else |
|
hw_node->daddr = sg_dma_address(sg); |
|
|
|
hw_node->nbytes = sg_dma_len(sg); |
|
hw_node->generic.length = sg_dma_len(sg); |
|
} |
|
|
|
/* interrupt at end of last node */ |
|
hw_node->control |= FDMA_NODE_CTRL_INT_EON; |
|
|
|
return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags); |
|
} |
|
|
|
static size_t st_fdma_desc_residue(struct st_fdma_chan *fchan, |
|
struct virt_dma_desc *vdesc, |
|
bool in_progress) |
|
{ |
|
struct st_fdma_desc *fdesc = fchan->fdesc; |
|
size_t residue = 0; |
|
dma_addr_t cur_addr = 0; |
|
int i; |
|
|
|
if (in_progress) { |
|
cur_addr = fchan_read(fchan, FDMA_CH_CMD_OFST); |
|
cur_addr &= FDMA_CH_CMD_DATA_MASK; |
|
} |
|
|
|
for (i = fchan->fdesc->n_nodes - 1 ; i >= 0; i--) { |
|
if (cur_addr == fdesc->node[i].pdesc) { |
|
residue += fnode_read(fchan, FDMA_CNTN_OFST); |
|
break; |
|
} |
|
residue += fdesc->node[i].desc->nbytes; |
|
} |
|
|
|
return residue; |
|
} |
|
|
|
static enum dma_status st_fdma_tx_status(struct dma_chan *chan, |
|
dma_cookie_t cookie, |
|
struct dma_tx_state *txstate) |
|
{ |
|
struct st_fdma_chan *fchan = to_st_fdma_chan(chan); |
|
struct virt_dma_desc *vd; |
|
enum dma_status ret; |
|
unsigned long flags; |
|
|
|
ret = dma_cookie_status(chan, cookie, txstate); |
|
if (ret == DMA_COMPLETE || !txstate) |
|
return ret; |
|
|
|
spin_lock_irqsave(&fchan->vchan.lock, flags); |
|
vd = vchan_find_desc(&fchan->vchan, cookie); |
|
if (fchan->fdesc && cookie == fchan->fdesc->vdesc.tx.cookie) |
|
txstate->residue = st_fdma_desc_residue(fchan, vd, true); |
|
else if (vd) |
|
txstate->residue = st_fdma_desc_residue(fchan, vd, false); |
|
else |
|
txstate->residue = 0; |
|
|
|
spin_unlock_irqrestore(&fchan->vchan.lock, flags); |
|
|
|
return ret; |
|
} |
|
|
|
static void st_fdma_issue_pending(struct dma_chan *chan) |
|
{ |
|
struct st_fdma_chan *fchan = to_st_fdma_chan(chan); |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&fchan->vchan.lock, flags); |
|
|
|
if (vchan_issue_pending(&fchan->vchan) && !fchan->fdesc) |
|
st_fdma_xfer_desc(fchan); |
|
|
|
spin_unlock_irqrestore(&fchan->vchan.lock, flags); |
|
} |
|
|
|
static int st_fdma_pause(struct dma_chan *chan) |
|
{ |
|
unsigned long flags; |
|
struct st_fdma_chan *fchan = to_st_fdma_chan(chan); |
|
int ch_id = fchan->vchan.chan.chan_id; |
|
unsigned long cmd = FDMA_CMD_PAUSE(ch_id); |
|
|
|
dev_dbg(fchan->fdev->dev, "pause chan:%d\n", ch_id); |
|
|
|
spin_lock_irqsave(&fchan->vchan.lock, flags); |
|
if (fchan->fdesc) |
|
fdma_write(fchan->fdev, cmd, FDMA_CMD_SET_OFST); |
|
spin_unlock_irqrestore(&fchan->vchan.lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static int st_fdma_resume(struct dma_chan *chan) |
|
{ |
|
unsigned long flags; |
|
unsigned long val; |
|
struct st_fdma_chan *fchan = to_st_fdma_chan(chan); |
|
int ch_id = fchan->vchan.chan.chan_id; |
|
|
|
dev_dbg(fchan->fdev->dev, "resume chan:%d\n", ch_id); |
|
|
|
spin_lock_irqsave(&fchan->vchan.lock, flags); |
|
if (fchan->fdesc) { |
|
val = fchan_read(fchan, FDMA_CH_CMD_OFST); |
|
val &= FDMA_CH_CMD_DATA_MASK; |
|
fchan_write(fchan, val, FDMA_CH_CMD_OFST); |
|
} |
|
spin_unlock_irqrestore(&fchan->vchan.lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static int st_fdma_terminate_all(struct dma_chan *chan) |
|
{ |
|
unsigned long flags; |
|
LIST_HEAD(head); |
|
struct st_fdma_chan *fchan = to_st_fdma_chan(chan); |
|
int ch_id = fchan->vchan.chan.chan_id; |
|
unsigned long cmd = FDMA_CMD_PAUSE(ch_id); |
|
|
|
dev_dbg(fchan->fdev->dev, "terminate chan:%d\n", ch_id); |
|
|
|
spin_lock_irqsave(&fchan->vchan.lock, flags); |
|
fdma_write(fchan->fdev, cmd, FDMA_CMD_SET_OFST); |
|
fchan->fdesc = NULL; |
|
vchan_get_all_descriptors(&fchan->vchan, &head); |
|
spin_unlock_irqrestore(&fchan->vchan.lock, flags); |
|
vchan_dma_desc_free_list(&fchan->vchan, &head); |
|
|
|
return 0; |
|
} |
|
|
|
static int st_fdma_slave_config(struct dma_chan *chan, |
|
struct dma_slave_config *slave_cfg) |
|
{ |
|
struct st_fdma_chan *fchan = to_st_fdma_chan(chan); |
|
|
|
memcpy(&fchan->scfg, slave_cfg, sizeof(fchan->scfg)); |
|
return 0; |
|
} |
|
|
|
static const struct st_fdma_driverdata fdma_mpe31_stih407_11 = { |
|
.name = "STiH407", |
|
.id = 0, |
|
}; |
|
|
|
static const struct st_fdma_driverdata fdma_mpe31_stih407_12 = { |
|
.name = "STiH407", |
|
.id = 1, |
|
}; |
|
|
|
static const struct st_fdma_driverdata fdma_mpe31_stih407_13 = { |
|
.name = "STiH407", |
|
.id = 2, |
|
}; |
|
|
|
static const struct of_device_id st_fdma_match[] = { |
|
{ .compatible = "st,stih407-fdma-mpe31-11" |
|
, .data = &fdma_mpe31_stih407_11 }, |
|
{ .compatible = "st,stih407-fdma-mpe31-12" |
|
, .data = &fdma_mpe31_stih407_12 }, |
|
{ .compatible = "st,stih407-fdma-mpe31-13" |
|
, .data = &fdma_mpe31_stih407_13 }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, st_fdma_match); |
|
|
|
static int st_fdma_parse_dt(struct platform_device *pdev, |
|
const struct st_fdma_driverdata *drvdata, |
|
struct st_fdma_dev *fdev) |
|
{ |
|
snprintf(fdev->fw_name, FW_NAME_SIZE, "fdma_%s_%d.elf", |
|
drvdata->name, drvdata->id); |
|
|
|
return of_property_read_u32(pdev->dev.of_node, "dma-channels", |
|
&fdev->nr_channels); |
|
} |
|
#define FDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
|
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ |
|
BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ |
|
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) |
|
|
|
static void st_fdma_free(struct st_fdma_dev *fdev) |
|
{ |
|
struct st_fdma_chan *fchan; |
|
int i; |
|
|
|
for (i = 0; i < fdev->nr_channels; i++) { |
|
fchan = &fdev->chans[i]; |
|
list_del(&fchan->vchan.chan.device_node); |
|
tasklet_kill(&fchan->vchan.task); |
|
} |
|
} |
|
|
|
static int st_fdma_probe(struct platform_device *pdev) |
|
{ |
|
struct st_fdma_dev *fdev; |
|
const struct of_device_id *match; |
|
struct device_node *np = pdev->dev.of_node; |
|
const struct st_fdma_driverdata *drvdata; |
|
int ret, i; |
|
|
|
match = of_match_device((st_fdma_match), &pdev->dev); |
|
if (!match || !match->data) { |
|
dev_err(&pdev->dev, "No device match found\n"); |
|
return -ENODEV; |
|
} |
|
|
|
drvdata = match->data; |
|
|
|
fdev = devm_kzalloc(&pdev->dev, sizeof(*fdev), GFP_KERNEL); |
|
if (!fdev) |
|
return -ENOMEM; |
|
|
|
ret = st_fdma_parse_dt(pdev, drvdata, fdev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "unable to find platform data\n"); |
|
goto err; |
|
} |
|
|
|
fdev->chans = devm_kcalloc(&pdev->dev, fdev->nr_channels, |
|
sizeof(struct st_fdma_chan), GFP_KERNEL); |
|
if (!fdev->chans) |
|
return -ENOMEM; |
|
|
|
fdev->dev = &pdev->dev; |
|
fdev->drvdata = drvdata; |
|
platform_set_drvdata(pdev, fdev); |
|
|
|
fdev->irq = platform_get_irq(pdev, 0); |
|
if (fdev->irq < 0) |
|
return -EINVAL; |
|
|
|
ret = devm_request_irq(&pdev->dev, fdev->irq, st_fdma_irq_handler, 0, |
|
dev_name(&pdev->dev), fdev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Failed to request irq (%d)\n", ret); |
|
goto err; |
|
} |
|
|
|
fdev->slim_rproc = st_slim_rproc_alloc(pdev, fdev->fw_name); |
|
if (IS_ERR(fdev->slim_rproc)) { |
|
ret = PTR_ERR(fdev->slim_rproc); |
|
dev_err(&pdev->dev, "slim_rproc_alloc failed (%d)\n", ret); |
|
goto err; |
|
} |
|
|
|
/* Initialise list of FDMA channels */ |
|
INIT_LIST_HEAD(&fdev->dma_device.channels); |
|
for (i = 0; i < fdev->nr_channels; i++) { |
|
struct st_fdma_chan *fchan = &fdev->chans[i]; |
|
|
|
fchan->fdev = fdev; |
|
fchan->vchan.desc_free = st_fdma_free_desc; |
|
vchan_init(&fchan->vchan, &fdev->dma_device); |
|
} |
|
|
|
/* Initialise the FDMA dreq (reserve 0 & 31 for FDMA use) */ |
|
fdev->dreq_mask = BIT(0) | BIT(31); |
|
|
|
dma_cap_set(DMA_SLAVE, fdev->dma_device.cap_mask); |
|
dma_cap_set(DMA_CYCLIC, fdev->dma_device.cap_mask); |
|
dma_cap_set(DMA_MEMCPY, fdev->dma_device.cap_mask); |
|
|
|
fdev->dma_device.dev = &pdev->dev; |
|
fdev->dma_device.device_alloc_chan_resources = st_fdma_alloc_chan_res; |
|
fdev->dma_device.device_free_chan_resources = st_fdma_free_chan_res; |
|
fdev->dma_device.device_prep_dma_cyclic = st_fdma_prep_dma_cyclic; |
|
fdev->dma_device.device_prep_slave_sg = st_fdma_prep_slave_sg; |
|
fdev->dma_device.device_prep_dma_memcpy = st_fdma_prep_dma_memcpy; |
|
fdev->dma_device.device_tx_status = st_fdma_tx_status; |
|
fdev->dma_device.device_issue_pending = st_fdma_issue_pending; |
|
fdev->dma_device.device_terminate_all = st_fdma_terminate_all; |
|
fdev->dma_device.device_config = st_fdma_slave_config; |
|
fdev->dma_device.device_pause = st_fdma_pause; |
|
fdev->dma_device.device_resume = st_fdma_resume; |
|
|
|
fdev->dma_device.src_addr_widths = FDMA_DMA_BUSWIDTHS; |
|
fdev->dma_device.dst_addr_widths = FDMA_DMA_BUSWIDTHS; |
|
fdev->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); |
|
fdev->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
|
|
|
ret = dmaenginem_async_device_register(&fdev->dma_device); |
|
if (ret) { |
|
dev_err(&pdev->dev, |
|
"Failed to register DMA device (%d)\n", ret); |
|
goto err_rproc; |
|
} |
|
|
|
ret = of_dma_controller_register(np, st_fdma_of_xlate, fdev); |
|
if (ret) { |
|
dev_err(&pdev->dev, |
|
"Failed to register controller (%d)\n", ret); |
|
goto err_rproc; |
|
} |
|
|
|
dev_info(&pdev->dev, "ST FDMA engine driver, irq:%d\n", fdev->irq); |
|
|
|
return 0; |
|
|
|
err_rproc: |
|
st_fdma_free(fdev); |
|
st_slim_rproc_put(fdev->slim_rproc); |
|
err: |
|
return ret; |
|
} |
|
|
|
static int st_fdma_remove(struct platform_device *pdev) |
|
{ |
|
struct st_fdma_dev *fdev = platform_get_drvdata(pdev); |
|
|
|
devm_free_irq(&pdev->dev, fdev->irq, fdev); |
|
st_slim_rproc_put(fdev->slim_rproc); |
|
of_dma_controller_free(pdev->dev.of_node); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver st_fdma_platform_driver = { |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
.of_match_table = st_fdma_match, |
|
}, |
|
.probe = st_fdma_probe, |
|
.remove = st_fdma_remove, |
|
}; |
|
module_platform_driver(st_fdma_platform_driver); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("STMicroelectronics FDMA engine driver"); |
|
MODULE_AUTHOR("Ludovic.barre <[email protected]>"); |
|
MODULE_AUTHOR("Peter Griffin <[email protected]>"); |
|
MODULE_ALIAS("platform: " DRIVER_NAME);
|
|
|