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350 lines
8.4 KiB
350 lines
8.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. |
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* Synopsys DesignWare eDMA v0 core |
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* |
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* Author: Gustavo Pimentel <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include "dw-edma-core.h" |
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#include "dw-edma-v0-core.h" |
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#include "dw-edma-v0-regs.h" |
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#include "dw-edma-v0-debugfs.h" |
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enum dw_edma_control { |
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DW_EDMA_V0_CB = BIT(0), |
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DW_EDMA_V0_TCB = BIT(1), |
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DW_EDMA_V0_LLP = BIT(2), |
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DW_EDMA_V0_LIE = BIT(3), |
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DW_EDMA_V0_RIE = BIT(4), |
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DW_EDMA_V0_CCS = BIT(8), |
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DW_EDMA_V0_LLE = BIT(9), |
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}; |
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static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) |
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{ |
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return dw->rg_region.vaddr; |
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} |
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#define SET(dw, name, value) \ |
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writel(value, &(__dw_regs(dw)->name)) |
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#define GET(dw, name) \ |
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readl(&(__dw_regs(dw)->name)) |
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#define SET_RW(dw, dir, name, value) \ |
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do { \ |
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if ((dir) == EDMA_DIR_WRITE) \ |
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SET(dw, wr_##name, value); \ |
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else \ |
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SET(dw, rd_##name, value); \ |
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} while (0) |
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#define GET_RW(dw, dir, name) \ |
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((dir) == EDMA_DIR_WRITE \ |
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? GET(dw, wr_##name) \ |
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: GET(dw, rd_##name)) |
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#define SET_BOTH(dw, name, value) \ |
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do { \ |
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SET(dw, wr_##name, value); \ |
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SET(dw, rd_##name, value); \ |
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} while (0) |
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static inline struct dw_edma_v0_ch_regs __iomem * |
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__dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) |
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{ |
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if (dw->mode == EDMA_MODE_LEGACY) |
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return &(__dw_regs(dw)->type.legacy.ch); |
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if (dir == EDMA_DIR_WRITE) |
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return &__dw_regs(dw)->type.unroll.ch[ch].wr; |
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return &__dw_regs(dw)->type.unroll.ch[ch].rd; |
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} |
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static inline void writel_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, |
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u32 value, void __iomem *addr) |
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{ |
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if (dw->mode == EDMA_MODE_LEGACY) { |
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u32 viewport_sel; |
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unsigned long flags; |
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raw_spin_lock_irqsave(&dw->lock, flags); |
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viewport_sel = FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch); |
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if (dir == EDMA_DIR_READ) |
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viewport_sel |= BIT(31); |
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writel(viewport_sel, |
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&(__dw_regs(dw)->type.legacy.viewport_sel)); |
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writel(value, addr); |
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raw_spin_unlock_irqrestore(&dw->lock, flags); |
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} else { |
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writel(value, addr); |
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} |
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} |
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static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, |
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const void __iomem *addr) |
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{ |
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u32 value; |
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if (dw->mode == EDMA_MODE_LEGACY) { |
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u32 viewport_sel; |
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unsigned long flags; |
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raw_spin_lock_irqsave(&dw->lock, flags); |
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viewport_sel = FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch); |
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if (dir == EDMA_DIR_READ) |
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viewport_sel |= BIT(31); |
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writel(viewport_sel, |
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&(__dw_regs(dw)->type.legacy.viewport_sel)); |
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value = readl(addr); |
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raw_spin_unlock_irqrestore(&dw->lock, flags); |
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} else { |
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value = readl(addr); |
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} |
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return value; |
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} |
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#define SET_CH(dw, dir, ch, name, value) \ |
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writel_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name)) |
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#define GET_CH(dw, dir, ch, name) \ |
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readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name)) |
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#define SET_LL(ll, value) \ |
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writel(value, ll) |
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/* eDMA management callbacks */ |
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void dw_edma_v0_core_off(struct dw_edma *dw) |
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{ |
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SET_BOTH(dw, int_mask, EDMA_V0_DONE_INT_MASK | EDMA_V0_ABORT_INT_MASK); |
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SET_BOTH(dw, int_clear, EDMA_V0_DONE_INT_MASK | EDMA_V0_ABORT_INT_MASK); |
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SET_BOTH(dw, engine_en, 0); |
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} |
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u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir) |
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{ |
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u32 num_ch; |
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if (dir == EDMA_DIR_WRITE) |
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num_ch = FIELD_GET(EDMA_V0_WRITE_CH_COUNT_MASK, GET(dw, ctrl)); |
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else |
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num_ch = FIELD_GET(EDMA_V0_READ_CH_COUNT_MASK, GET(dw, ctrl)); |
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if (num_ch > EDMA_V0_MAX_NR_CH) |
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num_ch = EDMA_V0_MAX_NR_CH; |
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return (u16)num_ch; |
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} |
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enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan) |
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{ |
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struct dw_edma *dw = chan->chip->dw; |
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u32 tmp; |
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tmp = FIELD_GET(EDMA_V0_CH_STATUS_MASK, |
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GET_CH(dw, chan->dir, chan->id, ch_control1)); |
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if (tmp == 1) |
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return DMA_IN_PROGRESS; |
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else if (tmp == 3) |
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return DMA_COMPLETE; |
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else |
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return DMA_ERROR; |
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} |
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void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan) |
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{ |
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struct dw_edma *dw = chan->chip->dw; |
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SET_RW(dw, chan->dir, int_clear, |
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FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id))); |
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} |
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void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan) |
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{ |
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struct dw_edma *dw = chan->chip->dw; |
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SET_RW(dw, chan->dir, int_clear, |
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FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id))); |
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} |
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u32 dw_edma_v0_core_status_done_int(struct dw_edma *dw, enum dw_edma_dir dir) |
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{ |
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return FIELD_GET(EDMA_V0_DONE_INT_MASK, GET_RW(dw, dir, int_status)); |
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} |
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u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir) |
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{ |
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return FIELD_GET(EDMA_V0_ABORT_INT_MASK, GET_RW(dw, dir, int_status)); |
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} |
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static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) |
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{ |
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struct dw_edma_burst *child; |
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struct dw_edma_v0_lli __iomem *lli; |
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struct dw_edma_v0_llp __iomem *llp; |
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u32 control = 0, i = 0; |
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int j; |
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lli = chunk->ll_region.vaddr; |
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if (chunk->cb) |
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control = DW_EDMA_V0_CB; |
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j = chunk->bursts_alloc; |
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list_for_each_entry(child, &chunk->burst->list, list) { |
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j--; |
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if (!j) |
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control |= (DW_EDMA_V0_LIE | DW_EDMA_V0_RIE); |
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/* Channel control */ |
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SET_LL(&lli[i].control, control); |
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/* Transfer size */ |
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SET_LL(&lli[i].transfer_size, child->sz); |
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/* SAR - low, high */ |
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SET_LL(&lli[i].sar_low, lower_32_bits(child->sar)); |
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SET_LL(&lli[i].sar_high, upper_32_bits(child->sar)); |
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/* DAR - low, high */ |
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SET_LL(&lli[i].dar_low, lower_32_bits(child->dar)); |
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SET_LL(&lli[i].dar_high, upper_32_bits(child->dar)); |
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i++; |
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} |
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llp = (void __iomem *)&lli[i]; |
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control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB; |
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if (!chunk->cb) |
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control |= DW_EDMA_V0_CB; |
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/* Channel control */ |
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SET_LL(&llp->control, control); |
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/* Linked list - low, high */ |
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SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr)); |
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SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr)); |
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} |
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void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) |
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{ |
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struct dw_edma_chan *chan = chunk->chan; |
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struct dw_edma *dw = chan->chip->dw; |
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u32 tmp; |
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dw_edma_v0_core_write_chunk(chunk); |
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if (first) { |
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/* Enable engine */ |
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SET_RW(dw, chan->dir, engine_en, BIT(0)); |
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/* Interrupt unmask - done, abort */ |
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tmp = GET_RW(dw, chan->dir, int_mask); |
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tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); |
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tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); |
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SET_RW(dw, chan->dir, int_mask, tmp); |
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/* Linked list error */ |
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tmp = GET_RW(dw, chan->dir, linked_list_err_en); |
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tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id)); |
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SET_RW(dw, chan->dir, linked_list_err_en, tmp); |
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/* Channel control */ |
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SET_CH(dw, chan->dir, chan->id, ch_control1, |
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(DW_EDMA_V0_CCS | DW_EDMA_V0_LLE)); |
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/* Linked list - low, high */ |
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SET_CH(dw, chan->dir, chan->id, llp_low, |
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lower_32_bits(chunk->ll_region.paddr)); |
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SET_CH(dw, chan->dir, chan->id, llp_high, |
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upper_32_bits(chunk->ll_region.paddr)); |
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} |
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/* Doorbell */ |
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SET_RW(dw, chan->dir, doorbell, |
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FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id)); |
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} |
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int dw_edma_v0_core_device_config(struct dw_edma_chan *chan) |
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{ |
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struct dw_edma *dw = chan->chip->dw; |
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u32 tmp = 0; |
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/* MSI done addr - low, high */ |
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SET_RW(dw, chan->dir, done_imwr_low, chan->msi.address_lo); |
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SET_RW(dw, chan->dir, done_imwr_high, chan->msi.address_hi); |
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/* MSI abort addr - low, high */ |
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SET_RW(dw, chan->dir, abort_imwr_low, chan->msi.address_lo); |
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SET_RW(dw, chan->dir, abort_imwr_high, chan->msi.address_hi); |
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/* MSI data - low, high */ |
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switch (chan->id) { |
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case 0: |
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case 1: |
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tmp = GET_RW(dw, chan->dir, ch01_imwr_data); |
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break; |
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case 2: |
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case 3: |
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tmp = GET_RW(dw, chan->dir, ch23_imwr_data); |
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break; |
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case 4: |
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case 5: |
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tmp = GET_RW(dw, chan->dir, ch45_imwr_data); |
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break; |
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case 6: |
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case 7: |
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tmp = GET_RW(dw, chan->dir, ch67_imwr_data); |
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break; |
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} |
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if (chan->id & BIT(0)) { |
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/* Channel odd {1, 3, 5, 7} */ |
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tmp &= EDMA_V0_CH_EVEN_MSI_DATA_MASK; |
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tmp |= FIELD_PREP(EDMA_V0_CH_ODD_MSI_DATA_MASK, |
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chan->msi.data); |
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} else { |
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/* Channel even {0, 2, 4, 6} */ |
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tmp &= EDMA_V0_CH_ODD_MSI_DATA_MASK; |
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tmp |= FIELD_PREP(EDMA_V0_CH_EVEN_MSI_DATA_MASK, |
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chan->msi.data); |
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} |
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switch (chan->id) { |
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case 0: |
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case 1: |
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SET_RW(dw, chan->dir, ch01_imwr_data, tmp); |
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break; |
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case 2: |
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case 3: |
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SET_RW(dw, chan->dir, ch23_imwr_data, tmp); |
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break; |
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case 4: |
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case 5: |
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SET_RW(dw, chan->dir, ch45_imwr_data, tmp); |
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break; |
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case 6: |
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case 7: |
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SET_RW(dw, chan->dir, ch67_imwr_data, tmp); |
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break; |
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} |
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return 0; |
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} |
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/* eDMA debugfs callbacks */ |
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void dw_edma_v0_core_debugfs_on(struct dw_edma_chip *chip) |
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{ |
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dw_edma_v0_debugfs_on(chip); |
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} |
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void dw_edma_v0_core_debugfs_off(void) |
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{ |
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dw_edma_v0_debugfs_off(); |
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}
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