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459 lines
12 KiB
459 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Faraday Technology FTTMR010 timer driver |
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* Copyright (C) 2017 Linus Walleij <[email protected]> |
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* |
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* Based on a rewrite of arch/arm/mach-gemini/timer.c: |
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* Copyright (C) 2001-2006 Storlink, Corp. |
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* Copyright (C) 2008-2009 Paulius Zaleckas <[email protected]> |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/clockchips.h> |
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#include <linux/clocksource.h> |
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#include <linux/sched_clock.h> |
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#include <linux/clk.h> |
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#include <linux/slab.h> |
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#include <linux/bitops.h> |
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#include <linux/delay.h> |
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/* |
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* Register definitions common for all the timer variants. |
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*/ |
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#define TIMER1_COUNT (0x00) |
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#define TIMER1_LOAD (0x04) |
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#define TIMER1_MATCH1 (0x08) |
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#define TIMER1_MATCH2 (0x0c) |
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#define TIMER2_COUNT (0x10) |
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#define TIMER2_LOAD (0x14) |
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#define TIMER2_MATCH1 (0x18) |
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#define TIMER2_MATCH2 (0x1c) |
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#define TIMER3_COUNT (0x20) |
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#define TIMER3_LOAD (0x24) |
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#define TIMER3_MATCH1 (0x28) |
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#define TIMER3_MATCH2 (0x2c) |
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#define TIMER_CR (0x30) |
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/* |
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* Control register set to clear for ast2600 only. |
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*/ |
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#define AST2600_TIMER_CR_CLR (0x3c) |
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/* |
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* Control register (TMC30) bit fields for fttmr010/gemini/moxart timers. |
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*/ |
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#define TIMER_1_CR_ENABLE BIT(0) |
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#define TIMER_1_CR_CLOCK BIT(1) |
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#define TIMER_1_CR_INT BIT(2) |
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#define TIMER_2_CR_ENABLE BIT(3) |
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#define TIMER_2_CR_CLOCK BIT(4) |
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#define TIMER_2_CR_INT BIT(5) |
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#define TIMER_3_CR_ENABLE BIT(6) |
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#define TIMER_3_CR_CLOCK BIT(7) |
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#define TIMER_3_CR_INT BIT(8) |
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#define TIMER_1_CR_UPDOWN BIT(9) |
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#define TIMER_2_CR_UPDOWN BIT(10) |
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#define TIMER_3_CR_UPDOWN BIT(11) |
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/* |
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* Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers. |
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* The aspeed timers move bits around in the control register and lacks |
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* bits for setting the timer to count upwards. |
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*/ |
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#define TIMER_1_CR_ASPEED_ENABLE BIT(0) |
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#define TIMER_1_CR_ASPEED_CLOCK BIT(1) |
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#define TIMER_1_CR_ASPEED_INT BIT(2) |
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#define TIMER_2_CR_ASPEED_ENABLE BIT(4) |
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#define TIMER_2_CR_ASPEED_CLOCK BIT(5) |
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#define TIMER_2_CR_ASPEED_INT BIT(6) |
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#define TIMER_3_CR_ASPEED_ENABLE BIT(8) |
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#define TIMER_3_CR_ASPEED_CLOCK BIT(9) |
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#define TIMER_3_CR_ASPEED_INT BIT(10) |
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/* |
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* Interrupt status/mask register definitions for fttmr010/gemini/moxart |
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* timers. |
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* The registers don't exist and they are not needed on aspeed timers |
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* because: |
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* - aspeed timer overflow interrupt is controlled by bits in Control |
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* Register (TMC30). |
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* - aspeed timers always generate interrupt when either one of the |
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* Match registers equals to Status register. |
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*/ |
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#define TIMER_INTR_STATE (0x34) |
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#define TIMER_INTR_MASK (0x38) |
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#define TIMER_1_INT_MATCH1 BIT(0) |
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#define TIMER_1_INT_MATCH2 BIT(1) |
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#define TIMER_1_INT_OVERFLOW BIT(2) |
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#define TIMER_2_INT_MATCH1 BIT(3) |
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#define TIMER_2_INT_MATCH2 BIT(4) |
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#define TIMER_2_INT_OVERFLOW BIT(5) |
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#define TIMER_3_INT_MATCH1 BIT(6) |
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#define TIMER_3_INT_MATCH2 BIT(7) |
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#define TIMER_3_INT_OVERFLOW BIT(8) |
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#define TIMER_INT_ALL_MASK 0x1ff |
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struct fttmr010 { |
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void __iomem *base; |
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unsigned int tick_rate; |
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bool is_aspeed; |
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u32 t1_enable_val; |
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struct clock_event_device clkevt; |
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int (*timer_shutdown)(struct clock_event_device *evt); |
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#ifdef CONFIG_ARM |
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struct delay_timer delay_timer; |
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#endif |
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}; |
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/* |
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* A local singleton used by sched_clock and delay timer reads, which are |
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* fast and stateless |
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*/ |
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static struct fttmr010 *local_fttmr; |
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static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) |
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{ |
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return container_of(evt, struct fttmr010, clkevt); |
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} |
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static unsigned long fttmr010_read_current_timer_up(void) |
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{ |
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return readl(local_fttmr->base + TIMER2_COUNT); |
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} |
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static unsigned long fttmr010_read_current_timer_down(void) |
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{ |
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return ~readl(local_fttmr->base + TIMER2_COUNT); |
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} |
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static u64 notrace fttmr010_read_sched_clock_up(void) |
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{ |
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return fttmr010_read_current_timer_up(); |
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} |
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static u64 notrace fttmr010_read_sched_clock_down(void) |
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{ |
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return fttmr010_read_current_timer_down(); |
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} |
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static int fttmr010_timer_set_next_event(unsigned long cycles, |
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struct clock_event_device *evt) |
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{ |
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struct fttmr010 *fttmr010 = to_fttmr010(evt); |
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u32 cr; |
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/* Stop */ |
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fttmr010->timer_shutdown(evt); |
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if (fttmr010->is_aspeed) { |
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/* |
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* ASPEED Timer Controller will load TIMER1_LOAD register |
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* into TIMER1_COUNT register when the timer is re-enabled. |
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*/ |
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writel(cycles, fttmr010->base + TIMER1_LOAD); |
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} else { |
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/* Setup the match register forward in time */ |
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cr = readl(fttmr010->base + TIMER1_COUNT); |
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writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); |
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} |
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/* Start */ |
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cr = readl(fttmr010->base + TIMER_CR); |
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cr |= fttmr010->t1_enable_val; |
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writel(cr, fttmr010->base + TIMER_CR); |
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return 0; |
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} |
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static int ast2600_timer_shutdown(struct clock_event_device *evt) |
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{ |
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struct fttmr010 *fttmr010 = to_fttmr010(evt); |
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/* Stop */ |
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writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR); |
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return 0; |
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} |
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static int fttmr010_timer_shutdown(struct clock_event_device *evt) |
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{ |
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struct fttmr010 *fttmr010 = to_fttmr010(evt); |
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u32 cr; |
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/* Stop */ |
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cr = readl(fttmr010->base + TIMER_CR); |
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cr &= ~fttmr010->t1_enable_val; |
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writel(cr, fttmr010->base + TIMER_CR); |
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return 0; |
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} |
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static int fttmr010_timer_set_oneshot(struct clock_event_device *evt) |
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{ |
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struct fttmr010 *fttmr010 = to_fttmr010(evt); |
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u32 cr; |
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/* Stop */ |
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fttmr010->timer_shutdown(evt); |
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/* Setup counter start from 0 or ~0 */ |
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writel(0, fttmr010->base + TIMER1_COUNT); |
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if (fttmr010->is_aspeed) { |
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writel(~0, fttmr010->base + TIMER1_LOAD); |
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} else { |
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writel(0, fttmr010->base + TIMER1_LOAD); |
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/* Enable interrupt */ |
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cr = readl(fttmr010->base + TIMER_INTR_MASK); |
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cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); |
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cr |= TIMER_1_INT_MATCH1; |
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writel(cr, fttmr010->base + TIMER_INTR_MASK); |
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} |
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return 0; |
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} |
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static int fttmr010_timer_set_periodic(struct clock_event_device *evt) |
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{ |
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struct fttmr010 *fttmr010 = to_fttmr010(evt); |
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u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ); |
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u32 cr; |
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/* Stop */ |
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fttmr010->timer_shutdown(evt); |
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/* Setup timer to fire at 1/HZ intervals. */ |
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if (fttmr010->is_aspeed) { |
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writel(period, fttmr010->base + TIMER1_LOAD); |
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} else { |
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cr = 0xffffffff - (period - 1); |
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writel(cr, fttmr010->base + TIMER1_COUNT); |
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writel(cr, fttmr010->base + TIMER1_LOAD); |
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/* Enable interrupt on overflow */ |
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cr = readl(fttmr010->base + TIMER_INTR_MASK); |
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cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); |
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cr |= TIMER_1_INT_OVERFLOW; |
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writel(cr, fttmr010->base + TIMER_INTR_MASK); |
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} |
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/* Start the timer */ |
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cr = readl(fttmr010->base + TIMER_CR); |
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cr |= fttmr010->t1_enable_val; |
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writel(cr, fttmr010->base + TIMER_CR); |
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return 0; |
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} |
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/* |
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* IRQ handler for the timer |
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*/ |
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static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = dev_id; |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t ast2600_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = dev_id; |
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struct fttmr010 *fttmr010 = to_fttmr010(evt); |
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writel(0x1, fttmr010->base + TIMER_INTR_STATE); |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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static int __init fttmr010_common_init(struct device_node *np, |
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bool is_aspeed, |
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int (*timer_shutdown)(struct clock_event_device *), |
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irq_handler_t irq_handler) |
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{ |
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struct fttmr010 *fttmr010; |
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int irq; |
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struct clk *clk; |
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int ret; |
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u32 val; |
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/* |
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* These implementations require a clock reference. |
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* FIXME: we currently only support clocking using PCLK |
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* and using EXTCLK is not supported in the driver. |
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*/ |
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clk = of_clk_get_by_name(np, "PCLK"); |
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if (IS_ERR(clk)) { |
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pr_err("could not get PCLK\n"); |
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return PTR_ERR(clk); |
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} |
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ret = clk_prepare_enable(clk); |
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if (ret) { |
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pr_err("failed to enable PCLK\n"); |
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return ret; |
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} |
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fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL); |
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if (!fttmr010) { |
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ret = -ENOMEM; |
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goto out_disable_clock; |
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} |
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fttmr010->tick_rate = clk_get_rate(clk); |
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fttmr010->base = of_iomap(np, 0); |
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if (!fttmr010->base) { |
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pr_err("Can't remap registers\n"); |
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ret = -ENXIO; |
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goto out_free; |
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} |
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/* IRQ for timer 1 */ |
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irq = irq_of_parse_and_map(np, 0); |
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if (irq <= 0) { |
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pr_err("Can't parse IRQ\n"); |
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ret = -EINVAL; |
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goto out_unmap; |
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} |
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/* |
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* The Aspeed timers move bits around in the control register. |
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*/ |
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if (is_aspeed) { |
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fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE | |
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TIMER_1_CR_ASPEED_INT; |
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fttmr010->is_aspeed = true; |
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} else { |
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fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT; |
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/* |
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* Reset the interrupt mask and status |
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*/ |
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writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); |
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writel(0, fttmr010->base + TIMER_INTR_STATE); |
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} |
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/* |
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* Enable timer 1 count up, timer 2 count up, except on Aspeed, |
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* where everything just counts down. |
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*/ |
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if (is_aspeed) |
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val = TIMER_2_CR_ASPEED_ENABLE; |
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else { |
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val = TIMER_2_CR_ENABLE | TIMER_1_CR_UPDOWN | |
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TIMER_2_CR_UPDOWN; |
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} |
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writel(val, fttmr010->base + TIMER_CR); |
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/* |
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* Setup free-running clocksource timer (interrupts |
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* disabled.) |
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*/ |
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local_fttmr = fttmr010; |
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writel(0, fttmr010->base + TIMER2_COUNT); |
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writel(0, fttmr010->base + TIMER2_MATCH1); |
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writel(0, fttmr010->base + TIMER2_MATCH2); |
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if (fttmr010->is_aspeed) { |
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writel(~0, fttmr010->base + TIMER2_LOAD); |
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clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, |
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"FTTMR010-TIMER2", |
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fttmr010->tick_rate, |
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300, 32, clocksource_mmio_readl_down); |
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sched_clock_register(fttmr010_read_sched_clock_down, 32, |
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fttmr010->tick_rate); |
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} else { |
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writel(0, fttmr010->base + TIMER2_LOAD); |
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clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, |
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"FTTMR010-TIMER2", |
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fttmr010->tick_rate, |
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300, 32, clocksource_mmio_readl_up); |
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sched_clock_register(fttmr010_read_sched_clock_up, 32, |
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fttmr010->tick_rate); |
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} |
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fttmr010->timer_shutdown = timer_shutdown; |
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/* |
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* Setup clockevent timer (interrupt-driven) on timer 1. |
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*/ |
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writel(0, fttmr010->base + TIMER1_COUNT); |
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writel(0, fttmr010->base + TIMER1_LOAD); |
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writel(0, fttmr010->base + TIMER1_MATCH1); |
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writel(0, fttmr010->base + TIMER1_MATCH2); |
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ret = request_irq(irq, irq_handler, IRQF_TIMER, |
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"FTTMR010-TIMER1", &fttmr010->clkevt); |
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if (ret) { |
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pr_err("FTTMR010-TIMER1 no IRQ\n"); |
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goto out_unmap; |
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} |
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fttmr010->clkevt.name = "FTTMR010-TIMER1"; |
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/* Reasonably fast and accurate clock event */ |
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fttmr010->clkevt.rating = 300; |
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fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT; |
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fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event; |
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fttmr010->clkevt.set_state_shutdown = fttmr010->timer_shutdown; |
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fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic; |
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fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot; |
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fttmr010->clkevt.tick_resume = fttmr010->timer_shutdown; |
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fttmr010->clkevt.cpumask = cpumask_of(0); |
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fttmr010->clkevt.irq = irq; |
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clockevents_config_and_register(&fttmr010->clkevt, |
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fttmr010->tick_rate, |
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1, 0xffffffff); |
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#ifdef CONFIG_ARM |
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/* Also use this timer for delays */ |
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if (fttmr010->is_aspeed) |
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fttmr010->delay_timer.read_current_timer = |
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fttmr010_read_current_timer_down; |
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else |
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fttmr010->delay_timer.read_current_timer = |
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fttmr010_read_current_timer_up; |
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fttmr010->delay_timer.freq = fttmr010->tick_rate; |
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register_current_timer_delay(&fttmr010->delay_timer); |
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#endif |
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return 0; |
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out_unmap: |
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iounmap(fttmr010->base); |
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out_free: |
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kfree(fttmr010); |
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out_disable_clock: |
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clk_disable_unprepare(clk); |
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return ret; |
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} |
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static __init int ast2600_timer_init(struct device_node *np) |
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{ |
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return fttmr010_common_init(np, true, |
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ast2600_timer_shutdown, |
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ast2600_timer_interrupt); |
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} |
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static __init int aspeed_timer_init(struct device_node *np) |
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{ |
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return fttmr010_common_init(np, true, |
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fttmr010_timer_shutdown, |
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fttmr010_timer_interrupt); |
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} |
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static __init int fttmr010_timer_init(struct device_node *np) |
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{ |
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return fttmr010_common_init(np, false, |
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fttmr010_timer_shutdown, |
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fttmr010_timer_interrupt); |
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} |
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TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init); |
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TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init); |
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TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init); |
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TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init); |
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TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init); |
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TIMER_OF_DECLARE(ast2600, "aspeed,ast2600-timer", ast2600_timer_init);
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