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283 lines
7.3 KiB
283 lines
7.3 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2008 STMicroelectronics |
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* Copyright (C) 2010 Alessandro Rubini |
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* Copyright (C) 2010 Linus Walleij for ST-Ericsson |
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*/ |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/io.h> |
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#include <linux/clockchips.h> |
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#include <linux/clocksource.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_platform.h> |
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#include <linux/clk.h> |
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#include <linux/jiffies.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/sched_clock.h> |
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#include <asm/mach/time.h> |
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/* |
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* The MTU device hosts four different counters, with 4 set of |
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* registers. These are register names. |
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*/ |
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#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ |
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#define MTU_RIS 0x04 /* Raw interrupt status */ |
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#define MTU_MIS 0x08 /* Masked interrupt status */ |
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#define MTU_ICR 0x0C /* Interrupt clear register */ |
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/* per-timer registers take 0..3 as argument */ |
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#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ |
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#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ |
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#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ |
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#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ |
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/* bits for the control register */ |
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#define MTU_CRn_ENA 0x80 |
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#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ |
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#define MTU_CRn_PRESCALE_MASK 0x0c |
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#define MTU_CRn_PRESCALE_1 0x00 |
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#define MTU_CRn_PRESCALE_16 0x04 |
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#define MTU_CRn_PRESCALE_256 0x08 |
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#define MTU_CRn_32BITS 0x02 |
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#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ |
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/* Other registers are usual amba/primecell registers, currently not used */ |
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#define MTU_ITCR 0xff0 |
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#define MTU_ITOP 0xff4 |
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#define MTU_PERIPH_ID0 0xfe0 |
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#define MTU_PERIPH_ID1 0xfe4 |
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#define MTU_PERIPH_ID2 0xfe8 |
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#define MTU_PERIPH_ID3 0xfeC |
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#define MTU_PCELL0 0xff0 |
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#define MTU_PCELL1 0xff4 |
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#define MTU_PCELL2 0xff8 |
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#define MTU_PCELL3 0xffC |
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static void __iomem *mtu_base; |
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static bool clkevt_periodic; |
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static u32 clk_prescale; |
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static u32 nmdk_cycle; /* write-once */ |
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static struct delay_timer mtu_delay_timer; |
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/* |
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* Override the global weak sched_clock symbol with this |
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* local implementation which uses the clocksource to get some |
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* better resolution when scheduling the kernel. |
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*/ |
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static u64 notrace nomadik_read_sched_clock(void) |
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{ |
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if (unlikely(!mtu_base)) |
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return 0; |
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return -readl(mtu_base + MTU_VAL(0)); |
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} |
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static unsigned long nmdk_timer_read_current_timer(void) |
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{ |
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return ~readl_relaxed(mtu_base + MTU_VAL(0)); |
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} |
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/* Clockevent device: use one-shot mode */ |
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static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) |
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{ |
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writel(1 << 1, mtu_base + MTU_IMSC); |
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writel(evt, mtu_base + MTU_LR(1)); |
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/* Load highest value, enable device, enable interrupts */ |
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writel(MTU_CRn_ONESHOT | clk_prescale | |
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MTU_CRn_32BITS | MTU_CRn_ENA, |
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mtu_base + MTU_CR(1)); |
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return 0; |
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} |
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static void nmdk_clkevt_reset(void) |
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{ |
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if (clkevt_periodic) { |
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/* Timer: configure load and background-load, and fire it up */ |
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writel(nmdk_cycle, mtu_base + MTU_LR(1)); |
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writel(nmdk_cycle, mtu_base + MTU_BGLR(1)); |
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writel(MTU_CRn_PERIODIC | clk_prescale | |
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MTU_CRn_32BITS | MTU_CRn_ENA, |
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mtu_base + MTU_CR(1)); |
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writel(1 << 1, mtu_base + MTU_IMSC); |
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} else { |
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/* Generate an interrupt to start the clockevent again */ |
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(void) nmdk_clkevt_next(nmdk_cycle, NULL); |
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} |
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} |
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static int nmdk_clkevt_shutdown(struct clock_event_device *evt) |
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{ |
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writel(0, mtu_base + MTU_IMSC); |
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/* disable timer */ |
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writel(0, mtu_base + MTU_CR(1)); |
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/* load some high default value */ |
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writel(0xffffffff, mtu_base + MTU_LR(1)); |
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return 0; |
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} |
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static int nmdk_clkevt_set_oneshot(struct clock_event_device *evt) |
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{ |
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clkevt_periodic = false; |
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return 0; |
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} |
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static int nmdk_clkevt_set_periodic(struct clock_event_device *evt) |
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{ |
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clkevt_periodic = true; |
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nmdk_clkevt_reset(); |
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return 0; |
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} |
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static void nmdk_clksrc_reset(void) |
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{ |
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/* Disable */ |
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writel(0, mtu_base + MTU_CR(0)); |
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/* ClockSource: configure load and background-load, and fire it up */ |
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writel(nmdk_cycle, mtu_base + MTU_LR(0)); |
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writel(nmdk_cycle, mtu_base + MTU_BGLR(0)); |
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writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA, |
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mtu_base + MTU_CR(0)); |
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} |
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static void nmdk_clkevt_resume(struct clock_event_device *cedev) |
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{ |
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nmdk_clkevt_reset(); |
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nmdk_clksrc_reset(); |
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} |
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static struct clock_event_device nmdk_clkevt = { |
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.name = "mtu_1", |
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.features = CLOCK_EVT_FEAT_ONESHOT | |
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CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_DYNIRQ, |
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.rating = 200, |
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.set_state_shutdown = nmdk_clkevt_shutdown, |
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.set_state_periodic = nmdk_clkevt_set_periodic, |
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.set_state_oneshot = nmdk_clkevt_set_oneshot, |
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.set_next_event = nmdk_clkevt_next, |
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.resume = nmdk_clkevt_resume, |
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}; |
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/* |
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* IRQ Handler for timer 1 of the MTU block. |
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*/ |
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static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evdev = dev_id; |
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writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */ |
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evdev->event_handler(evdev); |
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return IRQ_HANDLED; |
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} |
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static int __init nmdk_timer_init(void __iomem *base, int irq, |
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struct clk *pclk, struct clk *clk) |
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{ |
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unsigned long rate; |
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int ret; |
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int min_ticks; |
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mtu_base = base; |
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BUG_ON(clk_prepare_enable(pclk)); |
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BUG_ON(clk_prepare_enable(clk)); |
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/* |
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* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz |
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* for ux500, and in one specific Ux500 case 32768 Hz. |
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* |
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* Use a divide-by-16 counter if the tick rate is more than 32MHz. |
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* At 32 MHz, the timer (with 32 bit counter) can be programmed |
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* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer |
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* with 16 gives too low timer resolution. |
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*/ |
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rate = clk_get_rate(clk); |
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if (rate > 32000000) { |
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rate /= 16; |
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clk_prescale = MTU_CRn_PRESCALE_16; |
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} else { |
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clk_prescale = MTU_CRn_PRESCALE_1; |
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} |
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/* Cycles for periodic mode */ |
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nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ); |
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/* Timer 0 is the free running clocksource */ |
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nmdk_clksrc_reset(); |
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ret = clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0", |
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rate, 200, 32, clocksource_mmio_readl_down); |
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if (ret) { |
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pr_err("timer: failed to initialize clock source %s\n", "mtu_0"); |
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return ret; |
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} |
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sched_clock_register(nomadik_read_sched_clock, 32, rate); |
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/* Timer 1 is used for events, register irq and clockevents */ |
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if (request_irq(irq, nmdk_timer_interrupt, IRQF_TIMER, |
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"Nomadik Timer Tick", &nmdk_clkevt)) |
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pr_err("%s: request_irq() failed\n", "Nomadik Timer Tick"); |
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nmdk_clkevt.cpumask = cpumask_of(0); |
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nmdk_clkevt.irq = irq; |
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if (rate < 100000) |
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min_ticks = 5; |
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else |
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min_ticks = 2; |
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clockevents_config_and_register(&nmdk_clkevt, rate, min_ticks, |
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0xffffffffU); |
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mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer; |
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mtu_delay_timer.freq = rate; |
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register_current_timer_delay(&mtu_delay_timer); |
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return 0; |
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} |
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static int __init nmdk_timer_of_init(struct device_node *node) |
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{ |
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struct clk *pclk; |
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struct clk *clk; |
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void __iomem *base; |
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int irq; |
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base = of_iomap(node, 0); |
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if (!base) { |
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pr_err("Can't remap registers\n"); |
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return -ENXIO; |
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} |
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pclk = of_clk_get_by_name(node, "apb_pclk"); |
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if (IS_ERR(pclk)) { |
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pr_err("could not get apb_pclk\n"); |
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return PTR_ERR(pclk); |
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} |
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clk = of_clk_get_by_name(node, "timclk"); |
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if (IS_ERR(clk)) { |
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pr_err("could not get timclk\n"); |
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return PTR_ERR(clk); |
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} |
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irq = irq_of_parse_and_map(node, 0); |
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if (irq <= 0) { |
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pr_err("Can't parse IRQ\n"); |
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return -EINVAL; |
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} |
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return nmdk_timer_init(base, irq, pclk, clk); |
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} |
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TIMER_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu", |
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nmdk_timer_of_init);
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