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613 lines
16 KiB
613 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* linux/arch/arm/mach-exynos4/mct.c |
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* |
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* Copyright (c) 2011 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com |
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* |
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* Exynos4 MCT(Multi-Core Timer) support |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/err.h> |
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#include <linux/clk.h> |
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#include <linux/clockchips.h> |
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#include <linux/cpu.h> |
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#include <linux/delay.h> |
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#include <linux/percpu.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/clocksource.h> |
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#include <linux/sched_clock.h> |
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#define EXYNOS4_MCTREG(x) (x) |
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#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) |
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#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) |
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#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) |
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#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) |
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#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) |
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#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) |
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#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) |
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#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) |
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#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) |
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#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) |
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#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) |
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#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) |
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#define EXYNOS4_MCT_L_MASK (0xffffff00) |
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#define MCT_L_TCNTB_OFFSET (0x00) |
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#define MCT_L_ICNTB_OFFSET (0x08) |
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#define MCT_L_TCON_OFFSET (0x20) |
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#define MCT_L_INT_CSTAT_OFFSET (0x30) |
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#define MCT_L_INT_ENB_OFFSET (0x34) |
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#define MCT_L_WSTAT_OFFSET (0x40) |
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#define MCT_G_TCON_START (1 << 8) |
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#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) |
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#define MCT_G_TCON_COMP0_ENABLE (1 << 0) |
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#define MCT_L_TCON_INTERVAL_MODE (1 << 2) |
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#define MCT_L_TCON_INT_START (1 << 1) |
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#define MCT_L_TCON_TIMER_START (1 << 0) |
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#define TICK_BASE_CNT 1 |
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enum { |
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MCT_INT_SPI, |
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MCT_INT_PPI |
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}; |
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enum { |
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MCT_G0_IRQ, |
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MCT_G1_IRQ, |
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MCT_G2_IRQ, |
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MCT_G3_IRQ, |
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MCT_L0_IRQ, |
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MCT_L1_IRQ, |
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MCT_L2_IRQ, |
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MCT_L3_IRQ, |
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MCT_L4_IRQ, |
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MCT_L5_IRQ, |
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MCT_L6_IRQ, |
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MCT_L7_IRQ, |
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MCT_NR_IRQS, |
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}; |
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static void __iomem *reg_base; |
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static unsigned long clk_rate; |
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static unsigned int mct_int_type; |
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static int mct_irqs[MCT_NR_IRQS]; |
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struct mct_clock_event_device { |
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struct clock_event_device evt; |
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unsigned long base; |
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char name[10]; |
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}; |
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static void exynos4_mct_write(unsigned int value, unsigned long offset) |
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{ |
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unsigned long stat_addr; |
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u32 mask; |
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u32 i; |
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writel_relaxed(value, reg_base + offset); |
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if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { |
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stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; |
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switch (offset & ~EXYNOS4_MCT_L_MASK) { |
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case MCT_L_TCON_OFFSET: |
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mask = 1 << 3; /* L_TCON write status */ |
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break; |
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case MCT_L_ICNTB_OFFSET: |
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mask = 1 << 1; /* L_ICNTB write status */ |
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break; |
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case MCT_L_TCNTB_OFFSET: |
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mask = 1 << 0; /* L_TCNTB write status */ |
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break; |
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default: |
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return; |
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} |
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} else { |
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switch (offset) { |
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case EXYNOS4_MCT_G_TCON: |
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stat_addr = EXYNOS4_MCT_G_WSTAT; |
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mask = 1 << 16; /* G_TCON write status */ |
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break; |
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case EXYNOS4_MCT_G_COMP0_L: |
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stat_addr = EXYNOS4_MCT_G_WSTAT; |
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mask = 1 << 0; /* G_COMP0_L write status */ |
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break; |
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case EXYNOS4_MCT_G_COMP0_U: |
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stat_addr = EXYNOS4_MCT_G_WSTAT; |
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mask = 1 << 1; /* G_COMP0_U write status */ |
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break; |
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case EXYNOS4_MCT_G_COMP0_ADD_INCR: |
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stat_addr = EXYNOS4_MCT_G_WSTAT; |
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mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ |
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break; |
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case EXYNOS4_MCT_G_CNT_L: |
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stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
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mask = 1 << 0; /* G_CNT_L write status */ |
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break; |
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case EXYNOS4_MCT_G_CNT_U: |
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stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
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mask = 1 << 1; /* G_CNT_U write status */ |
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break; |
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default: |
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return; |
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} |
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} |
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/* Wait maximum 1 ms until written values are applied */ |
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for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) |
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if (readl_relaxed(reg_base + stat_addr) & mask) { |
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writel_relaxed(mask, reg_base + stat_addr); |
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return; |
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} |
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panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); |
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} |
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/* Clocksource handling */ |
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static void exynos4_mct_frc_start(void) |
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{ |
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u32 reg; |
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reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); |
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reg |= MCT_G_TCON_START; |
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exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); |
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} |
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/** |
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* exynos4_read_count_64 - Read all 64-bits of the global counter |
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* |
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* This will read all 64-bits of the global counter taking care to make sure |
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* that the upper and lower half match. Note that reading the MCT can be quite |
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* slow (hundreds of nanoseconds) so you should use the 32-bit (lower half |
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* only) version when possible. |
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* |
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* Returns the number of cycles in the global counter. |
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*/ |
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static u64 exynos4_read_count_64(void) |
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{ |
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unsigned int lo, hi; |
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u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); |
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do { |
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hi = hi2; |
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lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); |
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hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); |
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} while (hi != hi2); |
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return ((u64)hi << 32) | lo; |
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} |
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/** |
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* exynos4_read_count_32 - Read the lower 32-bits of the global counter |
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* |
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* This will read just the lower 32-bits of the global counter. This is marked |
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* as notrace so it can be used by the scheduler clock. |
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* |
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* Returns the number of cycles in the global counter (lower 32 bits). |
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*/ |
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static u32 notrace exynos4_read_count_32(void) |
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{ |
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return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); |
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} |
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static u64 exynos4_frc_read(struct clocksource *cs) |
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{ |
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return exynos4_read_count_32(); |
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} |
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static void exynos4_frc_resume(struct clocksource *cs) |
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{ |
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exynos4_mct_frc_start(); |
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} |
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static struct clocksource mct_frc = { |
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.name = "mct-frc", |
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.rating = 450, /* use value higher than ARM arch timer */ |
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.read = exynos4_frc_read, |
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.mask = CLOCKSOURCE_MASK(32), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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.resume = exynos4_frc_resume, |
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}; |
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static u64 notrace exynos4_read_sched_clock(void) |
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{ |
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return exynos4_read_count_32(); |
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} |
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#if defined(CONFIG_ARM) |
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static struct delay_timer exynos4_delay_timer; |
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static cycles_t exynos4_read_current_timer(void) |
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{ |
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BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32), |
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"cycles_t needs to move to 32-bit for ARM64 usage"); |
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return exynos4_read_count_32(); |
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} |
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#endif |
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static int __init exynos4_clocksource_init(void) |
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{ |
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exynos4_mct_frc_start(); |
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#if defined(CONFIG_ARM) |
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exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; |
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exynos4_delay_timer.freq = clk_rate; |
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register_current_timer_delay(&exynos4_delay_timer); |
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#endif |
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if (clocksource_register_hz(&mct_frc, clk_rate)) |
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panic("%s: can't register clocksource\n", mct_frc.name); |
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sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); |
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return 0; |
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} |
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static void exynos4_mct_comp0_stop(void) |
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{ |
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unsigned int tcon; |
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tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); |
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tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); |
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exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); |
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exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); |
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} |
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static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles) |
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{ |
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unsigned int tcon; |
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u64 comp_cycle; |
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tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); |
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if (periodic) { |
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tcon |= MCT_G_TCON_COMP0_AUTO_INC; |
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exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); |
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} |
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comp_cycle = exynos4_read_count_64() + cycles; |
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exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); |
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exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); |
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exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); |
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tcon |= MCT_G_TCON_COMP0_ENABLE; |
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exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); |
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} |
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static int exynos4_comp_set_next_event(unsigned long cycles, |
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struct clock_event_device *evt) |
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{ |
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exynos4_mct_comp0_start(false, cycles); |
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return 0; |
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} |
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static int mct_set_state_shutdown(struct clock_event_device *evt) |
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{ |
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exynos4_mct_comp0_stop(); |
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return 0; |
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} |
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static int mct_set_state_periodic(struct clock_event_device *evt) |
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{ |
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unsigned long cycles_per_jiffy; |
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cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) |
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>> evt->shift); |
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exynos4_mct_comp0_stop(); |
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exynos4_mct_comp0_start(true, cycles_per_jiffy); |
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return 0; |
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} |
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static struct clock_event_device mct_comp_device = { |
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.name = "mct-comp", |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.rating = 250, |
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.set_next_event = exynos4_comp_set_next_event, |
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.set_state_periodic = mct_set_state_periodic, |
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.set_state_shutdown = mct_set_state_shutdown, |
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.set_state_oneshot = mct_set_state_shutdown, |
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.set_state_oneshot_stopped = mct_set_state_shutdown, |
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.tick_resume = mct_set_state_shutdown, |
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}; |
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static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = dev_id; |
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exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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static int exynos4_clockevent_init(void) |
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{ |
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mct_comp_device.cpumask = cpumask_of(0); |
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clockevents_config_and_register(&mct_comp_device, clk_rate, |
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0xf, 0xffffffff); |
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if (request_irq(mct_irqs[MCT_G0_IRQ], exynos4_mct_comp_isr, |
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IRQF_TIMER | IRQF_IRQPOLL, "mct_comp_irq", |
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&mct_comp_device)) |
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pr_err("%s: request_irq() failed\n", "mct_comp_irq"); |
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return 0; |
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} |
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static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); |
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/* Clock event handling */ |
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static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) |
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{ |
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unsigned long tmp; |
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unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; |
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unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; |
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tmp = readl_relaxed(reg_base + offset); |
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if (tmp & mask) { |
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tmp &= ~mask; |
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exynos4_mct_write(tmp, offset); |
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} |
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} |
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static void exynos4_mct_tick_start(unsigned long cycles, |
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struct mct_clock_event_device *mevt) |
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{ |
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unsigned long tmp; |
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exynos4_mct_tick_stop(mevt); |
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tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ |
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/* update interrupt count buffer */ |
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exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); |
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/* enable MCT tick interrupt */ |
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); |
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tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); |
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tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | |
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MCT_L_TCON_INTERVAL_MODE; |
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exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); |
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} |
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static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) |
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{ |
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/* Clear the MCT tick interrupt */ |
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if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) |
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); |
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} |
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static int exynos4_tick_set_next_event(unsigned long cycles, |
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struct clock_event_device *evt) |
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{ |
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struct mct_clock_event_device *mevt; |
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mevt = container_of(evt, struct mct_clock_event_device, evt); |
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exynos4_mct_tick_start(cycles, mevt); |
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return 0; |
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} |
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static int set_state_shutdown(struct clock_event_device *evt) |
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{ |
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struct mct_clock_event_device *mevt; |
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mevt = container_of(evt, struct mct_clock_event_device, evt); |
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exynos4_mct_tick_stop(mevt); |
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exynos4_mct_tick_clear(mevt); |
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return 0; |
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} |
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static int set_state_periodic(struct clock_event_device *evt) |
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{ |
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struct mct_clock_event_device *mevt; |
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unsigned long cycles_per_jiffy; |
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mevt = container_of(evt, struct mct_clock_event_device, evt); |
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cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) |
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>> evt->shift); |
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exynos4_mct_tick_stop(mevt); |
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exynos4_mct_tick_start(cycles_per_jiffy, mevt); |
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return 0; |
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} |
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static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) |
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{ |
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struct mct_clock_event_device *mevt = dev_id; |
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struct clock_event_device *evt = &mevt->evt; |
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/* |
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* This is for supporting oneshot mode. |
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* Mct would generate interrupt periodically |
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* without explicit stopping. |
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*/ |
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if (!clockevent_state_periodic(&mevt->evt)) |
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exynos4_mct_tick_stop(mevt); |
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exynos4_mct_tick_clear(mevt); |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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static int exynos4_mct_starting_cpu(unsigned int cpu) |
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{ |
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struct mct_clock_event_device *mevt = |
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per_cpu_ptr(&percpu_mct_tick, cpu); |
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struct clock_event_device *evt = &mevt->evt; |
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mevt->base = EXYNOS4_MCT_L_BASE(cpu); |
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snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); |
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evt->name = mevt->name; |
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evt->cpumask = cpumask_of(cpu); |
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evt->set_next_event = exynos4_tick_set_next_event; |
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evt->set_state_periodic = set_state_periodic; |
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evt->set_state_shutdown = set_state_shutdown; |
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evt->set_state_oneshot = set_state_shutdown; |
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evt->set_state_oneshot_stopped = set_state_shutdown; |
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evt->tick_resume = set_state_shutdown; |
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evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
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evt->rating = 500; /* use value higher than ARM arch timer */ |
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exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); |
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if (mct_int_type == MCT_INT_SPI) { |
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if (evt->irq == -1) |
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return -EIO; |
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irq_force_affinity(evt->irq, cpumask_of(cpu)); |
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enable_irq(evt->irq); |
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} else { |
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enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); |
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} |
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clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), |
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0xf, 0x7fffffff); |
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return 0; |
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} |
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static int exynos4_mct_dying_cpu(unsigned int cpu) |
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{ |
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struct mct_clock_event_device *mevt = |
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per_cpu_ptr(&percpu_mct_tick, cpu); |
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struct clock_event_device *evt = &mevt->evt; |
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evt->set_state_shutdown(evt); |
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if (mct_int_type == MCT_INT_SPI) { |
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if (evt->irq != -1) |
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disable_irq_nosync(evt->irq); |
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); |
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} else { |
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disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); |
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} |
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return 0; |
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} |
|
|
|
static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base) |
|
{ |
|
int err, cpu; |
|
struct clk *mct_clk, *tick_clk; |
|
|
|
tick_clk = of_clk_get_by_name(np, "fin_pll"); |
|
if (IS_ERR(tick_clk)) |
|
panic("%s: unable to determine tick clock rate\n", __func__); |
|
clk_rate = clk_get_rate(tick_clk); |
|
|
|
mct_clk = of_clk_get_by_name(np, "mct"); |
|
if (IS_ERR(mct_clk)) |
|
panic("%s: unable to retrieve mct clock instance\n", __func__); |
|
clk_prepare_enable(mct_clk); |
|
|
|
reg_base = base; |
|
if (!reg_base) |
|
panic("%s: unable to ioremap mct address space\n", __func__); |
|
|
|
if (mct_int_type == MCT_INT_PPI) { |
|
|
|
err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], |
|
exynos4_mct_tick_isr, "MCT", |
|
&percpu_mct_tick); |
|
WARN(err, "MCT: can't request IRQ %d (%d)\n", |
|
mct_irqs[MCT_L0_IRQ], err); |
|
} else { |
|
for_each_possible_cpu(cpu) { |
|
int mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; |
|
struct mct_clock_event_device *pcpu_mevt = |
|
per_cpu_ptr(&percpu_mct_tick, cpu); |
|
|
|
pcpu_mevt->evt.irq = -1; |
|
|
|
irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); |
|
if (request_irq(mct_irq, |
|
exynos4_mct_tick_isr, |
|
IRQF_TIMER | IRQF_NOBALANCING, |
|
pcpu_mevt->name, pcpu_mevt)) { |
|
pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", |
|
cpu); |
|
|
|
continue; |
|
} |
|
pcpu_mevt->evt.irq = mct_irq; |
|
} |
|
} |
|
|
|
/* Install hotplug callbacks which configure the timer on this CPU */ |
|
err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, |
|
"clockevents/exynos4/mct_timer:starting", |
|
exynos4_mct_starting_cpu, |
|
exynos4_mct_dying_cpu); |
|
if (err) |
|
goto out_irq; |
|
|
|
return 0; |
|
|
|
out_irq: |
|
if (mct_int_type == MCT_INT_PPI) { |
|
free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); |
|
} else { |
|
for_each_possible_cpu(cpu) { |
|
struct mct_clock_event_device *pcpu_mevt = |
|
per_cpu_ptr(&percpu_mct_tick, cpu); |
|
|
|
if (pcpu_mevt->evt.irq != -1) { |
|
free_irq(pcpu_mevt->evt.irq, pcpu_mevt); |
|
pcpu_mevt->evt.irq = -1; |
|
} |
|
} |
|
} |
|
return err; |
|
} |
|
|
|
static int __init mct_init_dt(struct device_node *np, unsigned int int_type) |
|
{ |
|
u32 nr_irqs, i; |
|
int ret; |
|
|
|
mct_int_type = int_type; |
|
|
|
/* This driver uses only one global timer interrupt */ |
|
mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); |
|
|
|
/* |
|
* Find out the number of local irqs specified. The local |
|
* timer irqs are specified after the four global timer |
|
* irqs are specified. |
|
*/ |
|
nr_irqs = of_irq_count(np); |
|
for (i = MCT_L0_IRQ; i < nr_irqs; i++) |
|
mct_irqs[i] = irq_of_parse_and_map(np, i); |
|
|
|
ret = exynos4_timer_resources(np, of_iomap(np, 0)); |
|
if (ret) |
|
return ret; |
|
|
|
ret = exynos4_clocksource_init(); |
|
if (ret) |
|
return ret; |
|
|
|
return exynos4_clockevent_init(); |
|
} |
|
|
|
|
|
static int __init mct_init_spi(struct device_node *np) |
|
{ |
|
return mct_init_dt(np, MCT_INT_SPI); |
|
} |
|
|
|
static int __init mct_init_ppi(struct device_node *np) |
|
{ |
|
return mct_init_dt(np, MCT_INT_PPI); |
|
} |
|
TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); |
|
TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
|
|
|