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440 lines
11 KiB
440 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Cortina Systems Gemini SATA bridge add-on to Faraday FTIDE010 |
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* Copyright (C) 2017 Linus Walleij <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/bitops.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#include <linux/delay.h> |
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#include <linux/reset.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/pinctrl/consumer.h> |
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#include "sata_gemini.h" |
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#define DRV_NAME "gemini_sata_bridge" |
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/** |
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* struct sata_gemini - a state container for a Gemini SATA bridge |
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* @dev: the containing device |
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* @base: remapped I/O memory base |
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* @muxmode: the current muxing mode |
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* @ide_pins: if the device is using the plain IDE interface pins |
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* @sata_bridge: if the device enables the SATA bridge |
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* @sata0_reset: SATA0 reset handler |
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* @sata1_reset: SATA1 reset handler |
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* @sata0_pclk: SATA0 PCLK handler |
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* @sata1_pclk: SATA1 PCLK handler |
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*/ |
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struct sata_gemini { |
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struct device *dev; |
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void __iomem *base; |
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enum gemini_muxmode muxmode; |
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bool ide_pins; |
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bool sata_bridge; |
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struct reset_control *sata0_reset; |
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struct reset_control *sata1_reset; |
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struct clk *sata0_pclk; |
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struct clk *sata1_pclk; |
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}; |
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/* Miscellaneous Control Register */ |
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#define GEMINI_GLOBAL_MISC_CTRL 0x30 |
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/* |
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* Values of IDE IOMUX bits in the misc control register |
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* |
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* Bits 26:24 are "IDE IO Select", which decides what SATA |
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* adapters are connected to which of the two IDE/ATA |
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* controllers in the Gemini. We can connect the two IDE blocks |
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* to one SATA adapter each, both acting as master, or one IDE |
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* blocks to two SATA adapters so the IDE block can act in a |
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* master/slave configuration. |
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* |
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* We also bring out different blocks on the actual IDE |
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* pins (not SATA pins) if (and only if) these are muxed in. |
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* |
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* 111-100 - Reserved |
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* Mode 0: 000 - ata0 master <-> sata0 |
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* ata1 master <-> sata1 |
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* ata0 slave interface brought out on IDE pads |
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* Mode 1: 001 - ata0 master <-> sata0 |
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* ata1 master <-> sata1 |
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* ata1 slave interface brought out on IDE pads |
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* Mode 2: 010 - ata1 master <-> sata1 |
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* ata1 slave <-> sata0 |
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* ata0 master and slave interfaces brought out |
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* on IDE pads |
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* Mode 3: 011 - ata0 master <-> sata0 |
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* ata1 slave <-> sata1 |
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* ata1 master and slave interfaces brought out |
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* on IDE pads |
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*/ |
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#define GEMINI_IDE_IOMUX_MASK (7 << 24) |
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#define GEMINI_IDE_IOMUX_MODE0 (0 << 24) |
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#define GEMINI_IDE_IOMUX_MODE1 (1 << 24) |
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#define GEMINI_IDE_IOMUX_MODE2 (2 << 24) |
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#define GEMINI_IDE_IOMUX_MODE3 (3 << 24) |
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#define GEMINI_IDE_IOMUX_SHIFT (24) |
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/* |
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* Registers directly controlling the PATA<->SATA adapters |
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*/ |
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#define GEMINI_SATA_ID 0x00 |
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#define GEMINI_SATA_PHY_ID 0x04 |
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#define GEMINI_SATA0_STATUS 0x08 |
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#define GEMINI_SATA1_STATUS 0x0c |
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#define GEMINI_SATA0_CTRL 0x18 |
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#define GEMINI_SATA1_CTRL 0x1c |
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#define GEMINI_SATA_STATUS_BIST_DONE BIT(5) |
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#define GEMINI_SATA_STATUS_BIST_OK BIT(4) |
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#define GEMINI_SATA_STATUS_PHY_READY BIT(0) |
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#define GEMINI_SATA_CTRL_PHY_BIST_EN BIT(14) |
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#define GEMINI_SATA_CTRL_PHY_FORCE_IDLE BIT(13) |
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#define GEMINI_SATA_CTRL_PHY_FORCE_READY BIT(12) |
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#define GEMINI_SATA_CTRL_PHY_AFE_LOOP_EN BIT(10) |
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#define GEMINI_SATA_CTRL_PHY_DIG_LOOP_EN BIT(9) |
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#define GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN BIT(4) |
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#define GEMINI_SATA_CTRL_ATAPI_EN BIT(3) |
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#define GEMINI_SATA_CTRL_BUS_WITH_20 BIT(2) |
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#define GEMINI_SATA_CTRL_SLAVE_EN BIT(1) |
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#define GEMINI_SATA_CTRL_EN BIT(0) |
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/* |
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* There is only ever one instance of this bridge on a system, |
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* so create a singleton so that the FTIDE010 instances can grab |
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* a reference to it. |
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*/ |
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static struct sata_gemini *sg_singleton; |
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struct sata_gemini *gemini_sata_bridge_get(void) |
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{ |
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if (sg_singleton) |
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return sg_singleton; |
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return ERR_PTR(-EPROBE_DEFER); |
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} |
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EXPORT_SYMBOL(gemini_sata_bridge_get); |
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bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1) |
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{ |
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if (!sg->sata_bridge) |
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return false; |
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/* |
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* In muxmode 2 and 3 one of the ATA controllers is |
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* actually not connected to any SATA bridge. |
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*/ |
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if ((sg->muxmode == GEMINI_MUXMODE_2) && |
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!is_ata1) |
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return false; |
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if ((sg->muxmode == GEMINI_MUXMODE_3) && |
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is_ata1) |
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return false; |
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return true; |
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} |
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EXPORT_SYMBOL(gemini_sata_bridge_enabled); |
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enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg) |
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{ |
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return sg->muxmode; |
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} |
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EXPORT_SYMBOL(gemini_sata_get_muxmode); |
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static int gemini_sata_setup_bridge(struct sata_gemini *sg, |
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unsigned int bridge) |
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{ |
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unsigned long timeout = jiffies + (HZ * 1); |
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bool bridge_online; |
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u32 val; |
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if (bridge == 0) { |
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val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; |
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/* SATA0 slave mode is only used in muxmode 2 */ |
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if (sg->muxmode == GEMINI_MUXMODE_2) |
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val |= GEMINI_SATA_CTRL_SLAVE_EN; |
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writel(val, sg->base + GEMINI_SATA0_CTRL); |
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} else { |
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val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; |
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/* SATA1 slave mode is only used in muxmode 3 */ |
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if (sg->muxmode == GEMINI_MUXMODE_3) |
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val |= GEMINI_SATA_CTRL_SLAVE_EN; |
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writel(val, sg->base + GEMINI_SATA1_CTRL); |
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} |
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/* Vendor code waits 10 ms here */ |
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msleep(10); |
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/* Wait for PHY to become ready */ |
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do { |
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msleep(100); |
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if (bridge == 0) |
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val = readl(sg->base + GEMINI_SATA0_STATUS); |
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else |
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val = readl(sg->base + GEMINI_SATA1_STATUS); |
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if (val & GEMINI_SATA_STATUS_PHY_READY) |
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break; |
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} while (time_before(jiffies, timeout)); |
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bridge_online = !!(val & GEMINI_SATA_STATUS_PHY_READY); |
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dev_info(sg->dev, "SATA%d PHY %s\n", bridge, |
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bridge_online ? "ready" : "not ready"); |
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return bridge_online ? 0: -ENODEV; |
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} |
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int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge) |
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{ |
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struct clk *pclk; |
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int ret; |
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if (bridge == 0) |
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pclk = sg->sata0_pclk; |
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else |
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pclk = sg->sata1_pclk; |
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clk_enable(pclk); |
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msleep(10); |
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/* Do not keep clocking a bridge that is not online */ |
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ret = gemini_sata_setup_bridge(sg, bridge); |
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if (ret) |
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clk_disable(pclk); |
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return ret; |
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} |
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EXPORT_SYMBOL(gemini_sata_start_bridge); |
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void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge) |
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{ |
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if (bridge == 0) |
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clk_disable(sg->sata0_pclk); |
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else if (bridge == 1) |
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clk_disable(sg->sata1_pclk); |
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} |
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EXPORT_SYMBOL(gemini_sata_stop_bridge); |
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int gemini_sata_reset_bridge(struct sata_gemini *sg, |
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unsigned int bridge) |
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{ |
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if (bridge == 0) |
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reset_control_reset(sg->sata0_reset); |
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else |
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reset_control_reset(sg->sata1_reset); |
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msleep(10); |
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return gemini_sata_setup_bridge(sg, bridge); |
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} |
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EXPORT_SYMBOL(gemini_sata_reset_bridge); |
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static int gemini_sata_bridge_init(struct sata_gemini *sg) |
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{ |
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struct device *dev = sg->dev; |
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u32 sata_id, sata_phy_id; |
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int ret; |
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sg->sata0_pclk = devm_clk_get(dev, "SATA0_PCLK"); |
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if (IS_ERR(sg->sata0_pclk)) { |
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dev_err(dev, "no SATA0 PCLK"); |
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return -ENODEV; |
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} |
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sg->sata1_pclk = devm_clk_get(dev, "SATA1_PCLK"); |
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if (IS_ERR(sg->sata1_pclk)) { |
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dev_err(dev, "no SATA1 PCLK"); |
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return -ENODEV; |
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} |
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ret = clk_prepare_enable(sg->sata0_pclk); |
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if (ret) { |
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pr_err("failed to enable SATA0 PCLK\n"); |
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return ret; |
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} |
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ret = clk_prepare_enable(sg->sata1_pclk); |
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if (ret) { |
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pr_err("failed to enable SATA1 PCLK\n"); |
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clk_disable_unprepare(sg->sata0_pclk); |
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return ret; |
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} |
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sg->sata0_reset = devm_reset_control_get_exclusive(dev, "sata0"); |
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if (IS_ERR(sg->sata0_reset)) { |
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dev_err(dev, "no SATA0 reset controller\n"); |
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clk_disable_unprepare(sg->sata1_pclk); |
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clk_disable_unprepare(sg->sata0_pclk); |
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return PTR_ERR(sg->sata0_reset); |
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} |
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sg->sata1_reset = devm_reset_control_get_exclusive(dev, "sata1"); |
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if (IS_ERR(sg->sata1_reset)) { |
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dev_err(dev, "no SATA1 reset controller\n"); |
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clk_disable_unprepare(sg->sata1_pclk); |
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clk_disable_unprepare(sg->sata0_pclk); |
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return PTR_ERR(sg->sata1_reset); |
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} |
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sata_id = readl(sg->base + GEMINI_SATA_ID); |
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sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID); |
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sg->sata_bridge = true; |
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clk_disable(sg->sata0_pclk); |
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clk_disable(sg->sata1_pclk); |
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dev_info(dev, "SATA ID %08x, PHY ID: %08x\n", sata_id, sata_phy_id); |
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return 0; |
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} |
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static int gemini_setup_ide_pins(struct device *dev) |
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{ |
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struct pinctrl *p; |
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struct pinctrl_state *ide_state; |
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int ret; |
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p = devm_pinctrl_get(dev); |
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if (IS_ERR(p)) |
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return PTR_ERR(p); |
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ide_state = pinctrl_lookup_state(p, "ide"); |
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if (IS_ERR(ide_state)) |
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return PTR_ERR(ide_state); |
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ret = pinctrl_select_state(p, ide_state); |
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if (ret) { |
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dev_err(dev, "could not select IDE state\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int gemini_sata_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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struct sata_gemini *sg; |
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struct regmap *map; |
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struct resource *res; |
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enum gemini_muxmode muxmode; |
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u32 gmode; |
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u32 gmask; |
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int ret; |
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sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL); |
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if (!sg) |
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return -ENOMEM; |
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sg->dev = dev; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) |
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return -ENODEV; |
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sg->base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(sg->base)) |
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return PTR_ERR(sg->base); |
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map = syscon_regmap_lookup_by_phandle(np, "syscon"); |
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if (IS_ERR(map)) { |
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dev_err(dev, "no global syscon\n"); |
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return PTR_ERR(map); |
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} |
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/* Set up the SATA bridge if need be */ |
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if (of_property_read_bool(np, "cortina,gemini-enable-sata-bridge")) { |
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ret = gemini_sata_bridge_init(sg); |
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if (ret) |
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return ret; |
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} |
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if (of_property_read_bool(np, "cortina,gemini-enable-ide-pins")) |
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sg->ide_pins = true; |
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if (!sg->sata_bridge && !sg->ide_pins) { |
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dev_err(dev, "neither SATA bridge or IDE output enabled\n"); |
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ret = -EINVAL; |
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goto out_unprep_clk; |
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} |
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ret = of_property_read_u32(np, "cortina,gemini-ata-muxmode", &muxmode); |
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if (ret) { |
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dev_err(dev, "could not parse ATA muxmode\n"); |
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goto out_unprep_clk; |
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} |
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if (muxmode > GEMINI_MUXMODE_3) { |
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dev_err(dev, "illegal muxmode %d\n", muxmode); |
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ret = -EINVAL; |
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goto out_unprep_clk; |
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} |
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sg->muxmode = muxmode; |
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gmask = GEMINI_IDE_IOMUX_MASK; |
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gmode = (muxmode << GEMINI_IDE_IOMUX_SHIFT); |
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ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, gmask, gmode); |
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if (ret) { |
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dev_err(dev, "unable to set up IDE muxing\n"); |
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ret = -ENODEV; |
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goto out_unprep_clk; |
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} |
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/* |
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* Route out the IDE pins if desired. |
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* This is done by looking up a special pin control state called |
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* "ide" that will route out the IDE pins. |
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*/ |
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if (sg->ide_pins) { |
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ret = gemini_setup_ide_pins(dev); |
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if (ret) |
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return ret; |
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} |
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dev_info(dev, "set up the Gemini IDE/SATA nexus\n"); |
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platform_set_drvdata(pdev, sg); |
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sg_singleton = sg; |
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return 0; |
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out_unprep_clk: |
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if (sg->sata_bridge) { |
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clk_unprepare(sg->sata1_pclk); |
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clk_unprepare(sg->sata0_pclk); |
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} |
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return ret; |
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} |
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static int gemini_sata_remove(struct platform_device *pdev) |
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{ |
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struct sata_gemini *sg = platform_get_drvdata(pdev); |
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if (sg->sata_bridge) { |
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clk_unprepare(sg->sata1_pclk); |
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clk_unprepare(sg->sata0_pclk); |
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} |
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sg_singleton = NULL; |
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return 0; |
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} |
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static const struct of_device_id gemini_sata_of_match[] = { |
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{ |
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.compatible = "cortina,gemini-sata-bridge", |
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}, |
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{}, |
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}; |
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static struct platform_driver gemini_sata_driver = { |
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.driver = { |
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.name = DRV_NAME, |
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.of_match_table = of_match_ptr(gemini_sata_of_match), |
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}, |
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.probe = gemini_sata_probe, |
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.remove = gemini_sata_remove, |
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}; |
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module_platform_driver(gemini_sata_driver); |
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MODULE_AUTHOR("Linus Walleij <[email protected]>"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:" DRV_NAME);
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