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21 KiB
775 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277. |
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* |
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* Ported to libata by: |
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* Albert Lee <[email protected]> IBM Corporation |
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* |
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* Copyright (C) 1998-2002 Andre Hedrick <[email protected]> |
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* Portions Copyright (C) 1999 Promise Technology, Inc. |
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* |
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* Author: Frank Tiernan ([email protected]) |
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* Released under terms of General Public License |
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* |
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* libata documentation is available via 'make {ps|pdf}docs', |
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* as Documentation/driver-api/libata.rst |
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* |
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* Hardware information only available under NDA. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/ktime.h> |
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#include <scsi/scsi.h> |
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#include <scsi/scsi_host.h> |
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#include <scsi/scsi_cmnd.h> |
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#include <linux/libata.h> |
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#define DRV_NAME "pata_pdc2027x" |
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#define DRV_VERSION "1.0" |
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#undef PDC_DEBUG |
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#ifdef PDC_DEBUG |
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#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) |
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#else |
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#define PDPRINTK(fmt, args...) |
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#endif |
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enum { |
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PDC_MMIO_BAR = 5, |
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PDC_UDMA_100 = 0, |
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PDC_UDMA_133 = 1, |
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PDC_100_MHZ = 100000000, |
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PDC_133_MHZ = 133333333, |
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PDC_SYS_CTL = 0x1100, |
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PDC_ATA_CTL = 0x1104, |
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PDC_GLOBAL_CTL = 0x1108, |
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PDC_CTCR0 = 0x110C, |
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PDC_CTCR1 = 0x1110, |
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PDC_BYTE_COUNT = 0x1120, |
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PDC_PLL_CTL = 0x1202, |
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}; |
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static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
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#ifdef CONFIG_PM_SLEEP |
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static int pdc2027x_reinit_one(struct pci_dev *pdev); |
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#endif |
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static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline); |
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static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev); |
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static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev); |
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static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc); |
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static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask); |
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static int pdc2027x_cable_detect(struct ata_port *ap); |
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static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed); |
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/* |
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* ATA Timing Tables based on 133MHz controller clock. |
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* These tables are only used when the controller is in 133MHz clock. |
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* If the controller is in 100MHz clock, the ASIC hardware will |
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* set the timing registers automatically when "set feature" command |
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* is issued to the device. However, if the controller clock is 133MHz, |
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* the following tables must be used. |
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*/ |
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static const struct pdc2027x_pio_timing { |
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u8 value0, value1, value2; |
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} pdc2027x_pio_timing_tbl[] = { |
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{ 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ |
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{ 0x46, 0x29, 0xa4 }, /* PIO mode 1 */ |
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{ 0x23, 0x26, 0x64 }, /* PIO mode 2 */ |
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{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ |
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{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ |
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}; |
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static const struct pdc2027x_mdma_timing { |
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u8 value0, value1; |
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} pdc2027x_mdma_timing_tbl[] = { |
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{ 0xdf, 0x5f }, /* MDMA mode 0 */ |
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{ 0x6b, 0x27 }, /* MDMA mode 1 */ |
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{ 0x69, 0x25 }, /* MDMA mode 2 */ |
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}; |
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static const struct pdc2027x_udma_timing { |
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u8 value0, value1, value2; |
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} pdc2027x_udma_timing_tbl[] = { |
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{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ |
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{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ |
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{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ |
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{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ |
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{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ |
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{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ |
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{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ |
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}; |
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static const struct pci_device_id pdc2027x_pci_tbl[] = { |
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 }, |
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 }, |
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 }, |
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 }, |
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 }, |
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 }, |
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 }, |
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{ } /* terminate list */ |
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}; |
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static struct pci_driver pdc2027x_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = pdc2027x_pci_tbl, |
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.probe = pdc2027x_init_one, |
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.remove = ata_pci_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = ata_pci_device_suspend, |
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.resume = pdc2027x_reinit_one, |
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#endif |
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}; |
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static struct scsi_host_template pdc2027x_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static struct ata_port_operations pdc2027x_pata100_ops = { |
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.inherits = &ata_bmdma_port_ops, |
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.check_atapi_dma = pdc2027x_check_atapi_dma, |
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.cable_detect = pdc2027x_cable_detect, |
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.prereset = pdc2027x_prereset, |
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}; |
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static struct ata_port_operations pdc2027x_pata133_ops = { |
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.inherits = &pdc2027x_pata100_ops, |
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.mode_filter = pdc2027x_mode_filter, |
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.set_piomode = pdc2027x_set_piomode, |
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.set_dmamode = pdc2027x_set_dmamode, |
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.set_mode = pdc2027x_set_mode, |
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}; |
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static struct ata_port_info pdc2027x_port_info[] = { |
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/* PDC_UDMA_100 */ |
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{ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &pdc2027x_pata100_ops, |
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}, |
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/* PDC_UDMA_133 */ |
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{ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &pdc2027x_pata133_ops, |
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}, |
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}; |
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MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee"); |
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MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277"); |
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MODULE_LICENSE("GPL"); |
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MODULE_VERSION(DRV_VERSION); |
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MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); |
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/** |
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* port_mmio - Get the MMIO address of PDC2027x extended registers |
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* @ap: Port |
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* @offset: offset from mmio base |
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*/ |
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static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) |
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{ |
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return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset; |
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} |
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/** |
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* dev_mmio - Get the MMIO address of PDC2027x extended registers |
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* @ap: Port |
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* @adev: device |
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* @offset: offset from mmio base |
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*/ |
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static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset) |
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{ |
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u8 adj = (adev->devno) ? 0x08 : 0x00; |
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return port_mmio(ap, offset) + adj; |
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} |
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/** |
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* pdc2027x_pata_cable_detect - Probe host controller cable detect info |
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* @ap: Port for which cable detect info is desired |
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* |
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* Read 80c cable indicator from Promise extended register. |
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* This register is latched when the system is reset. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static int pdc2027x_cable_detect(struct ata_port *ap) |
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{ |
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u32 cgcr; |
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/* check cable detect results */ |
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cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL)); |
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if (cgcr & (1 << 26)) |
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goto cbl40; |
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PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no); |
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return ATA_CBL_PATA80; |
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cbl40: |
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printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no); |
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return ATA_CBL_PATA40; |
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} |
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/** |
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* pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled. |
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* @ap: Port to check |
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*/ |
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static inline int pdc2027x_port_enabled(struct ata_port *ap) |
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{ |
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return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02; |
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} |
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/** |
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* pdc2027x_prereset - prereset for PATA host controller |
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* @link: Target link |
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* @deadline: deadline jiffies for the operation |
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* |
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* Probeinit including cable detection. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline) |
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{ |
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/* Check whether port enabled */ |
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if (!pdc2027x_port_enabled(link->ap)) |
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return -ENOENT; |
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return ata_sff_prereset(link, deadline); |
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} |
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/** |
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* pdc2720x_mode_filter - mode selection filter |
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* @adev: ATA device |
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* @mask: list of modes proposed |
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* |
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* Block UDMA on devices that cause trouble with this controller. |
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*/ |
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static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask) |
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{ |
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unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
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struct ata_device *pair = ata_dev_pair(adev); |
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if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL) |
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return mask; |
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/* Check for slave of a Maxtor at UDMA6 */ |
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ata_id_c_string(pair->id, model_num, ATA_ID_PROD, |
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ATA_ID_PROD_LEN + 1); |
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/* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */ |
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if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6) |
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mask &= ~ (1 << (6 + ATA_SHIFT_UDMA)); |
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return mask; |
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} |
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/** |
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* pdc2027x_set_piomode - Initialize host controller PATA PIO timings |
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* @ap: Port to configure |
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* @adev: um |
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* |
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* Set PIO mode for device. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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unsigned int pio = adev->pio_mode - XFER_PIO_0; |
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u32 ctcr0, ctcr1; |
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PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode); |
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/* Sanity check */ |
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if (pio > 4) { |
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printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio); |
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return; |
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} |
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/* Set the PIO timing registers using value table for 133MHz */ |
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PDPRINTK("Set pio regs... \n"); |
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ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); |
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ctcr0 &= 0xffff0000; |
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ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | |
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(pdc2027x_pio_timing_tbl[pio].value1 << 8); |
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iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); |
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ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); |
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ctcr1 &= 0x00ffffff; |
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ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); |
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iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); |
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PDPRINTK("Set pio regs done\n"); |
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PDPRINTK("Set to pio mode[%u] \n", pio); |
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} |
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/** |
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* pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings |
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* @ap: Port to configure |
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* @adev: um |
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* |
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* Set UDMA mode for device. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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unsigned int dma_mode = adev->dma_mode; |
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u32 ctcr0, ctcr1; |
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if ((dma_mode >= XFER_UDMA_0) && |
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(dma_mode <= XFER_UDMA_6)) { |
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/* Set the UDMA timing registers with value table for 133MHz */ |
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unsigned int udma_mode = dma_mode & 0x07; |
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if (dma_mode == XFER_UDMA_2) { |
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/* |
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* Turn off tHOLD. |
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* If tHOLD is '1', the hardware will add half clock for data hold time. |
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* This code segment seems to be no effect. tHOLD will be overwritten below. |
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*/ |
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ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); |
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iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1)); |
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} |
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PDPRINTK("Set udma regs... \n"); |
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ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); |
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ctcr1 &= 0xff000000; |
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ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 | |
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(pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) | |
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(pdc2027x_udma_timing_tbl[udma_mode].value2 << 16); |
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iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); |
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PDPRINTK("Set udma regs done\n"); |
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PDPRINTK("Set to udma mode[%u] \n", udma_mode); |
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} else if ((dma_mode >= XFER_MW_DMA_0) && |
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(dma_mode <= XFER_MW_DMA_2)) { |
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/* Set the MDMA timing registers with value table for 133MHz */ |
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unsigned int mdma_mode = dma_mode & 0x07; |
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PDPRINTK("Set mdma regs... \n"); |
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ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); |
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ctcr0 &= 0x0000ffff; |
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ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) | |
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(pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24); |
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iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); |
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PDPRINTK("Set mdma regs done\n"); |
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PDPRINTK("Set to mdma mode[%u] \n", mdma_mode); |
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} else { |
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printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode); |
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} |
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} |
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/** |
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* pdc2027x_set_mode - Set the timing registers back to correct values. |
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* @link: link to configure |
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* @r_failed: Returned device for failure |
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* |
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* The pdc2027x hardware will look at "SET FEATURES" and change the timing registers |
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* automatically. The values set by the hardware might be incorrect, under 133Mhz PLL. |
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* This function overwrites the possibly incorrect values set by the hardware to be correct. |
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*/ |
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static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed) |
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{ |
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struct ata_port *ap = link->ap; |
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struct ata_device *dev; |
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int rc; |
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rc = ata_do_set_mode(link, r_failed); |
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if (rc < 0) |
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return rc; |
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ata_for_each_dev(dev, link, ENABLED) { |
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pdc2027x_set_piomode(ap, dev); |
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/* |
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* Enable prefetch if the device support PIO only. |
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*/ |
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if (dev->xfer_shift == ATA_SHIFT_PIO) { |
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u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1)); |
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ctcr1 |= (1 << 25); |
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iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1)); |
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PDPRINTK("Turn on prefetch\n"); |
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} else { |
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pdc2027x_set_dmamode(ap, dev); |
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} |
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} |
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return 0; |
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} |
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/** |
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* pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command |
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* @qc: Metadata associated with taskfile to check |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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* |
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* RETURNS: 0 when ATAPI DMA can be used |
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* 1 otherwise |
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*/ |
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static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc) |
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{ |
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struct scsi_cmnd *cmd = qc->scsicmd; |
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u8 *scsicmd = cmd->cmnd; |
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int rc = 1; /* atapi dma off by default */ |
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/* |
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* This workaround is from Promise's GPL driver. |
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* If ATAPI DMA is used for commands not in the |
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* following white list, say MODE_SENSE and REQUEST_SENSE, |
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* pdc2027x might hit the irq lost problem. |
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*/ |
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switch (scsicmd[0]) { |
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case READ_10: |
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case WRITE_10: |
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case READ_12: |
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case WRITE_12: |
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case READ_6: |
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case WRITE_6: |
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case 0xad: /* READ_DVD_STRUCTURE */ |
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case 0xbe: /* READ_CD */ |
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/* ATAPI DMA is ok */ |
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rc = 0; |
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break; |
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default: |
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; |
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} |
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return rc; |
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} |
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|
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/** |
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* pdc_read_counter - Read the ctr counter |
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* @host: target ATA host |
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*/ |
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static long pdc_read_counter(struct ata_host *host) |
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{ |
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void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; |
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long counter; |
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int retry = 1; |
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u32 bccrl, bccrh, bccrlv, bccrhv; |
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retry: |
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bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; |
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bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; |
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/* Read the counter values again for verification */ |
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bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; |
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bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; |
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counter = (bccrh << 15) | bccrl; |
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PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl); |
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PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv); |
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|
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/* |
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* The 30-bit decreasing counter are read by 2 pieces. |
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* Incorrect value may be read when both bccrh and bccrl are changing. |
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* Ex. When 7900 decrease to 78FF, wrong value 7800 might be read. |
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*/ |
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if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) { |
|
retry--; |
|
PDPRINTK("rereading counter\n"); |
|
goto retry; |
|
} |
|
|
|
return counter; |
|
} |
|
|
|
/** |
|
* adjust_pll - Adjust the PLL input clock in Hz. |
|
* |
|
* @pdc_controller: controller specific information |
|
* @host: target ATA host |
|
* @pll_clock: The input of PLL in HZ |
|
*/ |
|
static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx) |
|
{ |
|
void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; |
|
u16 pll_ctl; |
|
long pll_clock_khz = pll_clock / 1000; |
|
long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; |
|
long ratio = pout_required / pll_clock_khz; |
|
int F, R; |
|
|
|
/* Sanity check */ |
|
if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) { |
|
printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz); |
|
return; |
|
} |
|
|
|
#ifdef PDC_DEBUG |
|
PDPRINTK("pout_required is %ld\n", pout_required); |
|
|
|
/* Show the current clock value of PLL control register |
|
* (maybe already configured by the firmware) |
|
*/ |
|
pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); |
|
|
|
PDPRINTK("pll_ctl[%X]\n", pll_ctl); |
|
#endif |
|
|
|
/* |
|
* Calculate the ratio of F, R and OD |
|
* POUT = (F + 2) / (( R + 2) * NO) |
|
*/ |
|
if (ratio < 8600L) { /* 8.6x */ |
|
/* Using NO = 0x01, R = 0x0D */ |
|
R = 0x0d; |
|
} else if (ratio < 12900L) { /* 12.9x */ |
|
/* Using NO = 0x01, R = 0x08 */ |
|
R = 0x08; |
|
} else if (ratio < 16100L) { /* 16.1x */ |
|
/* Using NO = 0x01, R = 0x06 */ |
|
R = 0x06; |
|
} else if (ratio < 64000L) { /* 64x */ |
|
R = 0x00; |
|
} else { |
|
/* Invalid ratio */ |
|
printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio); |
|
return; |
|
} |
|
|
|
F = (ratio * (R+2)) / 1000 - 2; |
|
|
|
if (unlikely(F < 0 || F > 127)) { |
|
/* Invalid F */ |
|
printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F); |
|
return; |
|
} |
|
|
|
PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); |
|
|
|
pll_ctl = (R << 8) | F; |
|
|
|
PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl); |
|
|
|
iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); |
|
ioread16(mmio_base + PDC_PLL_CTL); /* flush */ |
|
|
|
/* Wait the PLL circuit to be stable */ |
|
msleep(30); |
|
|
|
#ifdef PDC_DEBUG |
|
/* |
|
* Show the current clock value of PLL control register |
|
* (maybe configured by the firmware) |
|
*/ |
|
pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); |
|
|
|
PDPRINTK("pll_ctl[%X]\n", pll_ctl); |
|
#endif |
|
|
|
return; |
|
} |
|
|
|
/** |
|
* detect_pll_input_clock - Detect the PLL input clock in Hz. |
|
* @host: target ATA host |
|
* Ex. 16949000 on 33MHz PCI bus for pdc20275. |
|
* Half of the PCI clock. |
|
*/ |
|
static long pdc_detect_pll_input_clock(struct ata_host *host) |
|
{ |
|
void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; |
|
u32 scr; |
|
long start_count, end_count; |
|
ktime_t start_time, end_time; |
|
long pll_clock, usec_elapsed; |
|
|
|
/* Start the test mode */ |
|
scr = ioread32(mmio_base + PDC_SYS_CTL); |
|
PDPRINTK("scr[%X]\n", scr); |
|
iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL); |
|
ioread32(mmio_base + PDC_SYS_CTL); /* flush */ |
|
|
|
/* Read current counter value */ |
|
start_count = pdc_read_counter(host); |
|
start_time = ktime_get(); |
|
|
|
/* Let the counter run for 100 ms. */ |
|
msleep(100); |
|
|
|
/* Read the counter values again */ |
|
end_count = pdc_read_counter(host); |
|
end_time = ktime_get(); |
|
|
|
/* Stop the test mode */ |
|
scr = ioread32(mmio_base + PDC_SYS_CTL); |
|
PDPRINTK("scr[%X]\n", scr); |
|
iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL); |
|
ioread32(mmio_base + PDC_SYS_CTL); /* flush */ |
|
|
|
/* calculate the input clock in Hz */ |
|
usec_elapsed = (long) ktime_us_delta(end_time, start_time); |
|
|
|
pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 * |
|
(100000000 / usec_elapsed); |
|
|
|
PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count); |
|
PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock); |
|
|
|
return pll_clock; |
|
} |
|
|
|
/** |
|
* pdc_hardware_init - Initialize the hardware. |
|
* @host: target ATA host |
|
* @board_idx: board identifier |
|
*/ |
|
static void pdc_hardware_init(struct ata_host *host, unsigned int board_idx) |
|
{ |
|
long pll_clock; |
|
|
|
/* |
|
* Detect PLL input clock rate. |
|
* On some system, where PCI bus is running at non-standard clock rate. |
|
* Ex. 25MHz or 40MHz, we have to adjust the cycle_time. |
|
* The pdc20275 controller employs PLL circuit to help correct timing registers setting. |
|
*/ |
|
pll_clock = pdc_detect_pll_input_clock(host); |
|
|
|
dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000); |
|
|
|
/* Adjust PLL control register */ |
|
pdc_adjust_pll(host, pll_clock, board_idx); |
|
} |
|
|
|
/** |
|
* pdc_ata_setup_port - setup the mmio address |
|
* @port: ata ioports to setup |
|
* @base: base address |
|
*/ |
|
static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
|
{ |
|
port->cmd_addr = |
|
port->data_addr = base; |
|
port->feature_addr = |
|
port->error_addr = base + 0x05; |
|
port->nsect_addr = base + 0x0a; |
|
port->lbal_addr = base + 0x0f; |
|
port->lbam_addr = base + 0x10; |
|
port->lbah_addr = base + 0x15; |
|
port->device_addr = base + 0x1a; |
|
port->command_addr = |
|
port->status_addr = base + 0x1f; |
|
port->altstatus_addr = |
|
port->ctl_addr = base + 0x81a; |
|
} |
|
|
|
/** |
|
* pdc2027x_init_one - PCI probe function |
|
* Called when an instance of PCI adapter is inserted. |
|
* This function checks whether the hardware is supported, |
|
* initialize hardware and register an instance of ata_host to |
|
* libata. (implements struct pci_driver.probe() ) |
|
* |
|
* @pdev: instance of pci_dev found |
|
* @ent: matching entry in the id_tbl[] |
|
*/ |
|
static int pdc2027x_init_one(struct pci_dev *pdev, |
|
const struct pci_device_id *ent) |
|
{ |
|
static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 }; |
|
static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 }; |
|
unsigned int board_idx = (unsigned int) ent->driver_data; |
|
const struct ata_port_info *ppi[] = |
|
{ &pdc2027x_port_info[board_idx], NULL }; |
|
struct ata_host *host; |
|
void __iomem *mmio_base; |
|
int i, rc; |
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION); |
|
|
|
/* alloc host */ |
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); |
|
if (!host) |
|
return -ENOMEM; |
|
|
|
/* acquire resources and fill host */ |
|
rc = pcim_enable_device(pdev); |
|
if (rc) |
|
return rc; |
|
|
|
rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
|
if (rc) |
|
return rc; |
|
host->iomap = pcim_iomap_table(pdev); |
|
|
|
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); |
|
if (rc) |
|
return rc; |
|
|
|
mmio_base = host->iomap[PDC_MMIO_BAR]; |
|
|
|
for (i = 0; i < 2; i++) { |
|
struct ata_port *ap = host->ports[i]; |
|
|
|
pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]); |
|
ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i]; |
|
|
|
ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); |
|
ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd"); |
|
} |
|
|
|
//pci_enable_intx(pdev); |
|
|
|
/* initialize adapter */ |
|
pdc_hardware_init(host, board_idx); |
|
|
|
pci_set_master(pdev); |
|
return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, |
|
IRQF_SHARED, &pdc2027x_sht); |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int pdc2027x_reinit_one(struct pci_dev *pdev) |
|
{ |
|
struct ata_host *host = pci_get_drvdata(pdev); |
|
unsigned int board_idx; |
|
int rc; |
|
|
|
rc = ata_pci_device_do_resume(pdev); |
|
if (rc) |
|
return rc; |
|
|
|
if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 || |
|
pdev->device == PCI_DEVICE_ID_PROMISE_20270) |
|
board_idx = PDC_UDMA_100; |
|
else |
|
board_idx = PDC_UDMA_133; |
|
|
|
pdc_hardware_init(host, board_idx); |
|
|
|
ata_host_resume(host); |
|
return 0; |
|
} |
|
#endif |
|
|
|
module_pci_driver(pdc2027x_pci_driver);
|
|
|