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1265 lines
33 KiB
1265 lines
33 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* pata-legacy.c - Legacy port PATA/SATA controller driver. |
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* Copyright 2005/2006 Red Hat, all rights reserved. |
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* |
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* An ATA driver for the legacy ATA ports. |
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* |
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* Data Sources: |
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* Opti 82C465/82C611 support: Data sheets at opti-inc.com |
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* HT6560 series: |
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* Promise 20230/20620: |
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* http://www.ryston.cz/petr/vlb/pdc20230b.html |
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* http://www.ryston.cz/petr/vlb/pdc20230c.html |
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* http://www.ryston.cz/petr/vlb/pdc20630.html |
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* QDI65x0: |
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* http://www.ryston.cz/petr/vlb/qd6500.html |
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* http://www.ryston.cz/petr/vlb/qd6580.html |
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* |
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* QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c |
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* Rewritten from the work of Colten Edwards <[email protected]> by |
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* Samuel Thibault <[email protected]> |
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* |
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* Unsupported but docs exist: |
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* Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 |
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* |
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* This driver handles legacy (that is "ISA/VLB side") IDE ports found |
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* on PC class systems. There are three hybrid devices that are exceptions |
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* The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and |
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* the MPIIX where the tuning is PCI side but the IDE is "ISA side". |
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* |
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* Specific support is included for the ht6560a/ht6560b/opti82c611a/ |
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* opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A |
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* |
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* Support for the Winbond 83759A when operating in advanced mode. |
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* Multichip mode is not currently supported. |
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* |
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* Use the autospeed and pio_mask options with: |
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* Appian ADI/2 aka CLPD7220 or AIC25VL01. |
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* Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with |
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* Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, |
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* Winbond W83759A, Promise PDC20230-B |
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* |
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* For now use autospeed and pio_mask as above with the W83759A. This may |
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* change. |
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*/ |
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|
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#include <linux/async.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/ata.h> |
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#include <linux/libata.h> |
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#include <linux/platform_device.h> |
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|
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#define DRV_NAME "pata_legacy" |
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#define DRV_VERSION "0.6.5" |
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|
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#define NR_HOST 6 |
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|
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static int all; |
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module_param(all, int, 0444); |
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MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); |
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|
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enum controller { |
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BIOS = 0, |
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SNOOP = 1, |
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PDC20230 = 2, |
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HT6560A = 3, |
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HT6560B = 4, |
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OPTI611A = 5, |
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OPTI46X = 6, |
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QDI6500 = 7, |
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QDI6580 = 8, |
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QDI6580DP = 9, /* Dual channel mode is different */ |
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W83759A = 10, |
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|
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UNKNOWN = -1 |
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}; |
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|
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struct legacy_data { |
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unsigned long timing; |
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u8 clock[2]; |
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u8 last; |
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int fast; |
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enum controller type; |
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struct platform_device *platform_dev; |
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}; |
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struct legacy_probe { |
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unsigned char *name; |
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unsigned long port; |
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unsigned int irq; |
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unsigned int slot; |
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enum controller type; |
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unsigned long private; |
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}; |
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|
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struct legacy_controller { |
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const char *name; |
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struct ata_port_operations *ops; |
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unsigned int pio_mask; |
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unsigned int flags; |
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unsigned int pflags; |
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int (*setup)(struct platform_device *, struct legacy_probe *probe, |
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struct legacy_data *data); |
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}; |
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|
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static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; |
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|
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static struct legacy_probe probe_list[NR_HOST]; |
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static struct legacy_data legacy_data[NR_HOST]; |
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static struct ata_host *legacy_host[NR_HOST]; |
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static int nr_legacy_host; |
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static int probe_all; /* Set to check all ISA port ranges */ |
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static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ |
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static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ |
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static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ |
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static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ |
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static int autospeed; /* Chip present which snoops speed changes */ |
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static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */ |
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static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ |
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|
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/* Set to probe QDI controllers */ |
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#ifdef CONFIG_PATA_QDI_MODULE |
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static int qdi = 1; |
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#else |
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static int qdi; |
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#endif |
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|
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#ifdef CONFIG_PATA_WINBOND_VLB_MODULE |
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static int winbond = 1; /* Set to probe Winbond controllers, |
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give I/O port if non standard */ |
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#else |
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static int winbond; /* Set to probe Winbond controllers, |
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give I/O port if non standard */ |
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#endif |
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|
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/** |
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* legacy_probe_add - Add interface to probe list |
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* @port: Controller port |
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* @irq: IRQ number |
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* @type: Controller type |
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* @private: Controller specific info |
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* |
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* Add an entry into the probe list for ATA controllers. This is used |
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* to add the default ISA slots and then to build up the table |
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* further according to other ISA/VLB/Weird device scans |
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* |
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* An I/O port list is used to keep ordering stable and sane, as we |
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* don't have any good way to talk about ordering otherwise |
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*/ |
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|
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static int legacy_probe_add(unsigned long port, unsigned int irq, |
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enum controller type, unsigned long private) |
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{ |
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struct legacy_probe *lp = &probe_list[0]; |
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int i; |
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struct legacy_probe *free = NULL; |
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|
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for (i = 0; i < NR_HOST; i++) { |
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if (lp->port == 0 && free == NULL) |
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free = lp; |
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/* Matching port, or the correct slot for ordering */ |
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if (lp->port == port || legacy_port[i] == port) { |
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free = lp; |
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break; |
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} |
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lp++; |
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} |
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if (free == NULL) { |
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printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); |
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return -1; |
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} |
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/* Fill in the entry for later probing */ |
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free->port = port; |
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free->irq = irq; |
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free->type = type; |
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free->private = private; |
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return 0; |
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} |
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/** |
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* legacy_set_mode - mode setting |
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* @link: IDE link |
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* @unused: Device that failed when error is returned |
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* |
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* Use a non standard set_mode function. We don't want to be tuned. |
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* |
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* The BIOS configured everything. Our job is not to fiddle. Just use |
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* whatever PIO the hardware is using and leave it at that. When we |
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* get some kind of nice user driven API for control then we can |
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* expand on this as per hdparm in the base kernel. |
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*/ |
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|
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static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) |
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{ |
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struct ata_device *dev; |
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ata_for_each_dev(dev, link, ENABLED) { |
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ata_dev_info(dev, "configured for PIO\n"); |
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dev->pio_mode = XFER_PIO_0; |
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dev->xfer_mode = XFER_PIO_0; |
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dev->xfer_shift = ATA_SHIFT_PIO; |
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dev->flags |= ATA_DFLAG_PIO; |
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} |
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return 0; |
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} |
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static struct scsi_host_template legacy_sht = { |
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ATA_PIO_SHT(DRV_NAME), |
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}; |
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static const struct ata_port_operations legacy_base_port_ops = { |
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.inherits = &ata_sff_port_ops, |
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.cable_detect = ata_cable_40wire, |
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}; |
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|
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/* |
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* These ops are used if the user indicates the hardware |
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* snoops the commands to decide on the mode and handles the |
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* mode selection "magically" itself. Several legacy controllers |
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* do this. The mode range can be set if it is not 0x1F by setting |
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* pio_mask as well. |
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*/ |
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static struct ata_port_operations simple_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.sff_data_xfer = ata_sff_data_xfer32, |
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}; |
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static struct ata_port_operations legacy_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.sff_data_xfer = ata_sff_data_xfer32, |
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.set_mode = legacy_set_mode, |
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}; |
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|
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/* |
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* Promise 20230C and 20620 support |
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* |
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* This controller supports PIO0 to PIO2. We set PIO timings |
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* conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA |
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* support is weird being DMA to controller and PIO'd to the host |
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* and not supported. |
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*/ |
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static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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int tries = 5; |
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int pio = adev->pio_mode - XFER_PIO_0; |
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u8 rt; |
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unsigned long flags; |
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/* Safe as UP only. Force I/Os to occur together */ |
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local_irq_save(flags); |
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|
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/* Unlock the control interface */ |
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do { |
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inb(0x1F5); |
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outb(inb(0x1F2) | 0x80, 0x1F2); |
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inb(0x1F2); |
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inb(0x3F6); |
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inb(0x3F6); |
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inb(0x1F2); |
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inb(0x1F2); |
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} |
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while ((inb(0x1F2) & 0x80) && --tries); |
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local_irq_restore(flags); |
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outb(inb(0x1F4) & 0x07, 0x1F4); |
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rt = inb(0x1F3); |
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rt &= 0x07 << (3 * adev->devno); |
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if (pio) |
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rt |= (1 + 3 * pio) << (3 * adev->devno); |
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udelay(100); |
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outb(inb(0x1F2) | 0x01, 0x1F2); |
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udelay(100); |
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inb(0x1F5); |
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} |
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static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc, |
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unsigned char *buf, unsigned int buflen, int rw) |
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{ |
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struct ata_device *dev = qc->dev; |
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struct ata_port *ap = dev->link->ap; |
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int slop = buflen & 3; |
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/* 32bit I/O capable *and* we need to write a whole number of dwords */ |
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if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) |
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&& (ap->pflags & ATA_PFLAG_PIO32)) { |
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unsigned long flags; |
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local_irq_save(flags); |
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/* Perform the 32bit I/O synchronization sequence */ |
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ioread8(ap->ioaddr.nsect_addr); |
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ioread8(ap->ioaddr.nsect_addr); |
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ioread8(ap->ioaddr.nsect_addr); |
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|
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/* Now the data */ |
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if (rw == READ) |
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ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
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else |
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iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
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if (unlikely(slop)) { |
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__le32 pad; |
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if (rw == READ) { |
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pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
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memcpy(buf + buflen - slop, &pad, slop); |
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} else { |
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memcpy(&pad, buf + buflen - slop, slop); |
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iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
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} |
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buflen += 4 - slop; |
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} |
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local_irq_restore(flags); |
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} else |
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buflen = ata_sff_data_xfer32(qc, buf, buflen, rw); |
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return buflen; |
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} |
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static struct ata_port_operations pdc20230_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.set_piomode = pdc20230_set_piomode, |
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.sff_data_xfer = pdc_data_xfer_vlb, |
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}; |
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|
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/* |
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* Holtek 6560A support |
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* |
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* This controller supports PIO0 to PIO2 (no IORDY even though higher |
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* timings can be loaded). |
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*/ |
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static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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u8 active, recover; |
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struct ata_timing t; |
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|
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/* Get the timing data in cycles. For now play safe at 50Mhz */ |
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ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
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active = clamp_val(t.active, 2, 15); |
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recover = clamp_val(t.recover, 4, 15); |
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inb(0x3E6); |
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inb(0x3E6); |
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inb(0x3E6); |
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inb(0x3E6); |
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iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
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ioread8(ap->ioaddr.status_addr); |
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} |
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static struct ata_port_operations ht6560a_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.set_piomode = ht6560a_set_piomode, |
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}; |
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|
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/* |
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* Holtek 6560B support |
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* |
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* This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO |
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* setting unless we see an ATAPI device in which case we force it off. |
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* |
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* FIXME: need to implement 2nd channel support. |
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*/ |
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static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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u8 active, recover; |
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struct ata_timing t; |
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|
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/* Get the timing data in cycles. For now play safe at 50Mhz */ |
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ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
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|
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active = clamp_val(t.active, 2, 15); |
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recover = clamp_val(t.recover, 2, 16) & 0x0F; |
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inb(0x3E6); |
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inb(0x3E6); |
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inb(0x3E6); |
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inb(0x3E6); |
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iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
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if (adev->class != ATA_DEV_ATA) { |
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u8 rconf = inb(0x3E6); |
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if (rconf & 0x24) { |
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rconf &= ~0x24; |
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outb(rconf, 0x3E6); |
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} |
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} |
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ioread8(ap->ioaddr.status_addr); |
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} |
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static struct ata_port_operations ht6560b_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.set_piomode = ht6560b_set_piomode, |
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}; |
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|
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/* |
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* Opti core chipset helpers |
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*/ |
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|
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/** |
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* opti_syscfg - read OPTI chipset configuration |
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* @reg: Configuration register to read |
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* |
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* Returns the value of an OPTI system board configuration register. |
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*/ |
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|
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static u8 opti_syscfg(u8 reg) |
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{ |
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unsigned long flags; |
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u8 r; |
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|
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/* Uniprocessor chipset and must force cycles adjancent */ |
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local_irq_save(flags); |
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outb(reg, 0x22); |
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r = inb(0x24); |
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local_irq_restore(flags); |
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return r; |
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} |
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|
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/* |
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* Opti 82C611A |
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* |
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* This controller supports PIO0 to PIO3. |
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*/ |
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|
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static void opti82c611a_set_piomode(struct ata_port *ap, |
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struct ata_device *adev) |
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{ |
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u8 active, recover, setup; |
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struct ata_timing t; |
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struct ata_device *pair = ata_dev_pair(adev); |
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int clock; |
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int khz[4] = { 50000, 40000, 33000, 25000 }; |
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u8 rc; |
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|
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/* Enter configuration mode */ |
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ioread16(ap->ioaddr.error_addr); |
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ioread16(ap->ioaddr.error_addr); |
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iowrite8(3, ap->ioaddr.nsect_addr); |
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|
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/* Read VLB clock strapping */ |
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clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
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|
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/* Get the timing data in cycles */ |
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ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); |
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|
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/* Setup timing is shared */ |
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if (pair) { |
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struct ata_timing tp; |
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ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); |
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|
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ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); |
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} |
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|
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active = clamp_val(t.active, 2, 17) - 2; |
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recover = clamp_val(t.recover, 1, 16) - 1; |
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setup = clamp_val(t.setup, 1, 4) - 1; |
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|
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/* Select the right timing bank for write timing */ |
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rc = ioread8(ap->ioaddr.lbal_addr); |
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rc &= 0x7F; |
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rc |= (adev->devno << 7); |
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iowrite8(rc, ap->ioaddr.lbal_addr); |
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|
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/* Write the timings */ |
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iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
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|
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/* Select the right bank for read timings, also |
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load the shared timings for address */ |
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rc = ioread8(ap->ioaddr.device_addr); |
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rc &= 0xC0; |
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rc |= adev->devno; /* Index select */ |
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rc |= (setup << 4) | 0x04; |
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iowrite8(rc, ap->ioaddr.device_addr); |
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|
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/* Load the read timings */ |
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iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
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|
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/* Ensure the timing register mode is right */ |
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rc = ioread8(ap->ioaddr.lbal_addr); |
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rc &= 0x73; |
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rc |= 0x84; |
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iowrite8(rc, ap->ioaddr.lbal_addr); |
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|
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/* Exit command mode */ |
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iowrite8(0x83, ap->ioaddr.nsect_addr); |
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} |
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|
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|
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static struct ata_port_operations opti82c611a_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.set_piomode = opti82c611a_set_piomode, |
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}; |
|
|
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/* |
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* Opti 82C465MV |
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* |
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* This controller supports PIO0 to PIO3. Unlike the 611A the MVB |
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* version is dual channel but doesn't have a lot of unique registers. |
|
*/ |
|
|
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static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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u8 active, recover, setup; |
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struct ata_timing t; |
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struct ata_device *pair = ata_dev_pair(adev); |
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int clock; |
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int khz[4] = { 50000, 40000, 33000, 25000 }; |
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u8 rc; |
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u8 sysclk; |
|
|
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/* Get the clock */ |
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sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */ |
|
|
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/* Enter configuration mode */ |
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ioread16(ap->ioaddr.error_addr); |
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ioread16(ap->ioaddr.error_addr); |
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iowrite8(3, ap->ioaddr.nsect_addr); |
|
|
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/* Read VLB clock strapping */ |
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clock = 1000000000 / khz[sysclk]; |
|
|
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/* Get the timing data in cycles */ |
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ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); |
|
|
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/* Setup timing is shared */ |
|
if (pair) { |
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struct ata_timing tp; |
|
ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); |
|
|
|
ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); |
|
} |
|
|
|
active = clamp_val(t.active, 2, 17) - 2; |
|
recover = clamp_val(t.recover, 1, 16) - 1; |
|
setup = clamp_val(t.setup, 1, 4) - 1; |
|
|
|
/* Select the right timing bank for write timing */ |
|
rc = ioread8(ap->ioaddr.lbal_addr); |
|
rc &= 0x7F; |
|
rc |= (adev->devno << 7); |
|
iowrite8(rc, ap->ioaddr.lbal_addr); |
|
|
|
/* Write the timings */ |
|
iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
|
|
|
/* Select the right bank for read timings, also |
|
load the shared timings for address */ |
|
rc = ioread8(ap->ioaddr.device_addr); |
|
rc &= 0xC0; |
|
rc |= adev->devno; /* Index select */ |
|
rc |= (setup << 4) | 0x04; |
|
iowrite8(rc, ap->ioaddr.device_addr); |
|
|
|
/* Load the read timings */ |
|
iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
|
|
|
/* Ensure the timing register mode is right */ |
|
rc = ioread8(ap->ioaddr.lbal_addr); |
|
rc &= 0x73; |
|
rc |= 0x84; |
|
iowrite8(rc, ap->ioaddr.lbal_addr); |
|
|
|
/* Exit command mode */ |
|
iowrite8(0x83, ap->ioaddr.nsect_addr); |
|
|
|
/* We need to know this for quad device on the MVB */ |
|
ap->host->private_data = ap; |
|
} |
|
|
|
/** |
|
* opt82c465mv_qc_issue - command issue |
|
* @qc: command pending |
|
* |
|
* Called when the libata layer is about to issue a command. We wrap |
|
* this interface so that we can load the correct ATA timings. The |
|
* MVB has a single set of timing registers and these are shared |
|
* across channels. As there are two registers we really ought to |
|
* track the last two used values as a sort of register window. For |
|
* now we just reload on a channel switch. On the single channel |
|
* setup this condition never fires so we do nothing extra. |
|
* |
|
* FIXME: dual channel needs ->serialize support |
|
*/ |
|
|
|
static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) |
|
{ |
|
struct ata_port *ap = qc->ap; |
|
struct ata_device *adev = qc->dev; |
|
|
|
/* If timings are set and for the wrong channel (2nd test is |
|
due to a libata shortcoming and will eventually go I hope) */ |
|
if (ap->host->private_data != ap->host |
|
&& ap->host->private_data != NULL) |
|
opti82c46x_set_piomode(ap, adev); |
|
|
|
return ata_sff_qc_issue(qc); |
|
} |
|
|
|
static struct ata_port_operations opti82c46x_port_ops = { |
|
.inherits = &legacy_base_port_ops, |
|
.set_piomode = opti82c46x_set_piomode, |
|
.qc_issue = opti82c46x_qc_issue, |
|
}; |
|
|
|
/** |
|
* qdi65x0_set_piomode - PIO setup for QDI65x0 |
|
* @ap: Port |
|
* @adev: Device |
|
* |
|
* In single channel mode the 6580 has one clock per device and we can |
|
* avoid the requirement to clock switch. We also have to load the timing |
|
* into the right clock according to whether we are master or slave. |
|
* |
|
* In dual channel mode the 6580 has one clock per channel and we have |
|
* to software clockswitch in qc_issue. |
|
*/ |
|
|
|
static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev) |
|
{ |
|
struct ata_timing t; |
|
struct legacy_data *ld_qdi = ap->host->private_data; |
|
int active, recovery; |
|
u8 timing; |
|
|
|
/* Get the timing data in cycles */ |
|
ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); |
|
|
|
if (ld_qdi->fast) { |
|
active = 8 - clamp_val(t.active, 1, 8); |
|
recovery = 18 - clamp_val(t.recover, 3, 18); |
|
} else { |
|
active = 9 - clamp_val(t.active, 2, 9); |
|
recovery = 15 - clamp_val(t.recover, 0, 15); |
|
} |
|
timing = (recovery << 4) | active | 0x08; |
|
ld_qdi->clock[adev->devno] = timing; |
|
|
|
if (ld_qdi->type == QDI6580) |
|
outb(timing, ld_qdi->timing + 2 * adev->devno); |
|
else |
|
outb(timing, ld_qdi->timing + 2 * ap->port_no); |
|
|
|
/* Clear the FIFO */ |
|
if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA) |
|
outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); |
|
} |
|
|
|
/** |
|
* qdi_qc_issue - command issue |
|
* @qc: command pending |
|
* |
|
* Called when the libata layer is about to issue a command. We wrap |
|
* this interface so that we can load the correct ATA timings. |
|
*/ |
|
|
|
static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) |
|
{ |
|
struct ata_port *ap = qc->ap; |
|
struct ata_device *adev = qc->dev; |
|
struct legacy_data *ld_qdi = ap->host->private_data; |
|
|
|
if (ld_qdi->clock[adev->devno] != ld_qdi->last) { |
|
if (adev->pio_mode) { |
|
ld_qdi->last = ld_qdi->clock[adev->devno]; |
|
outb(ld_qdi->clock[adev->devno], ld_qdi->timing + |
|
2 * ap->port_no); |
|
} |
|
} |
|
return ata_sff_qc_issue(qc); |
|
} |
|
|
|
static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc, |
|
unsigned char *buf, |
|
unsigned int buflen, int rw) |
|
{ |
|
struct ata_device *adev = qc->dev; |
|
struct ata_port *ap = adev->link->ap; |
|
int slop = buflen & 3; |
|
|
|
if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) |
|
&& (ap->pflags & ATA_PFLAG_PIO32)) { |
|
if (rw == WRITE) |
|
iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
|
else |
|
ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
|
|
|
if (unlikely(slop)) { |
|
__le32 pad; |
|
if (rw == WRITE) { |
|
memcpy(&pad, buf + buflen - slop, slop); |
|
iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
|
} else { |
|
pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
|
memcpy(buf + buflen - slop, &pad, slop); |
|
} |
|
} |
|
return (buflen + 3) & ~3; |
|
} else |
|
return ata_sff_data_xfer(qc, buf, buflen, rw); |
|
} |
|
|
|
static int qdi_port(struct platform_device *dev, |
|
struct legacy_probe *lp, struct legacy_data *ld) |
|
{ |
|
if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) |
|
return -EBUSY; |
|
ld->timing = lp->private; |
|
return 0; |
|
} |
|
|
|
static struct ata_port_operations qdi6500_port_ops = { |
|
.inherits = &legacy_base_port_ops, |
|
.set_piomode = qdi65x0_set_piomode, |
|
.qc_issue = qdi_qc_issue, |
|
.sff_data_xfer = vlb32_data_xfer, |
|
}; |
|
|
|
static struct ata_port_operations qdi6580_port_ops = { |
|
.inherits = &legacy_base_port_ops, |
|
.set_piomode = qdi65x0_set_piomode, |
|
.sff_data_xfer = vlb32_data_xfer, |
|
}; |
|
|
|
static struct ata_port_operations qdi6580dp_port_ops = { |
|
.inherits = &legacy_base_port_ops, |
|
.set_piomode = qdi65x0_set_piomode, |
|
.qc_issue = qdi_qc_issue, |
|
.sff_data_xfer = vlb32_data_xfer, |
|
}; |
|
|
|
static DEFINE_SPINLOCK(winbond_lock); |
|
|
|
static void winbond_writecfg(unsigned long port, u8 reg, u8 val) |
|
{ |
|
unsigned long flags; |
|
spin_lock_irqsave(&winbond_lock, flags); |
|
outb(reg, port + 0x01); |
|
outb(val, port + 0x02); |
|
spin_unlock_irqrestore(&winbond_lock, flags); |
|
} |
|
|
|
static u8 winbond_readcfg(unsigned long port, u8 reg) |
|
{ |
|
u8 val; |
|
|
|
unsigned long flags; |
|
spin_lock_irqsave(&winbond_lock, flags); |
|
outb(reg, port + 0x01); |
|
val = inb(port + 0x02); |
|
spin_unlock_irqrestore(&winbond_lock, flags); |
|
|
|
return val; |
|
} |
|
|
|
static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) |
|
{ |
|
struct ata_timing t; |
|
struct legacy_data *ld_winbond = ap->host->private_data; |
|
int active, recovery; |
|
u8 reg; |
|
int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); |
|
|
|
reg = winbond_readcfg(ld_winbond->timing, 0x81); |
|
|
|
/* Get the timing data in cycles */ |
|
if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ |
|
ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
|
else |
|
ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); |
|
|
|
active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; |
|
recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; |
|
timing = (active << 4) | recovery; |
|
winbond_writecfg(ld_winbond->timing, timing, reg); |
|
|
|
/* Load the setup timing */ |
|
|
|
reg = 0x35; |
|
if (adev->class != ATA_DEV_ATA) |
|
reg |= 0x08; /* FIFO off */ |
|
if (!ata_pio_need_iordy(adev)) |
|
reg |= 0x02; /* IORDY off */ |
|
reg |= (clamp_val(t.setup, 0, 3) << 6); |
|
winbond_writecfg(ld_winbond->timing, timing + 1, reg); |
|
} |
|
|
|
static int winbond_port(struct platform_device *dev, |
|
struct legacy_probe *lp, struct legacy_data *ld) |
|
{ |
|
if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) |
|
return -EBUSY; |
|
ld->timing = lp->private; |
|
return 0; |
|
} |
|
|
|
static struct ata_port_operations winbond_port_ops = { |
|
.inherits = &legacy_base_port_ops, |
|
.set_piomode = winbond_set_piomode, |
|
.sff_data_xfer = vlb32_data_xfer, |
|
}; |
|
|
|
static struct legacy_controller controllers[] = { |
|
{"BIOS", &legacy_port_ops, ATA_PIO4, |
|
ATA_FLAG_NO_IORDY, 0, NULL }, |
|
{"Snooping", &simple_port_ops, ATA_PIO4, |
|
0, 0, NULL }, |
|
{"PDC20230", &pdc20230_port_ops, ATA_PIO2, |
|
ATA_FLAG_NO_IORDY, |
|
ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, |
|
{"HT6560A", &ht6560a_port_ops, ATA_PIO2, |
|
ATA_FLAG_NO_IORDY, 0, NULL }, |
|
{"HT6560B", &ht6560b_port_ops, ATA_PIO4, |
|
ATA_FLAG_NO_IORDY, 0, NULL }, |
|
{"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3, |
|
0, 0, NULL }, |
|
{"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3, |
|
0, 0, NULL }, |
|
{"QDI6500", &qdi6500_port_ops, ATA_PIO2, |
|
ATA_FLAG_NO_IORDY, |
|
ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
|
{"QDI6580", &qdi6580_port_ops, ATA_PIO4, |
|
0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
|
{"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4, |
|
0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
|
{"W83759A", &winbond_port_ops, ATA_PIO4, |
|
0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, |
|
winbond_port } |
|
}; |
|
|
|
/** |
|
* probe_chip_type - Discover controller |
|
* @probe: Probe entry to check |
|
* |
|
* Probe an ATA port and identify the type of controller. We don't |
|
* check if the controller appears to be driveless at this point. |
|
*/ |
|
|
|
static __init int probe_chip_type(struct legacy_probe *probe) |
|
{ |
|
int mask = 1 << probe->slot; |
|
|
|
if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { |
|
u8 reg = winbond_readcfg(winbond, 0x81); |
|
reg |= 0x80; /* jumpered mode off */ |
|
winbond_writecfg(winbond, 0x81, reg); |
|
reg = winbond_readcfg(winbond, 0x83); |
|
reg |= 0xF0; /* local control */ |
|
winbond_writecfg(winbond, 0x83, reg); |
|
reg = winbond_readcfg(winbond, 0x85); |
|
reg |= 0xF0; /* programmable timing */ |
|
winbond_writecfg(winbond, 0x85, reg); |
|
|
|
reg = winbond_readcfg(winbond, 0x81); |
|
|
|
if (reg & mask) |
|
return W83759A; |
|
} |
|
if (probe->port == 0x1F0) { |
|
unsigned long flags; |
|
local_irq_save(flags); |
|
/* Probes */ |
|
outb(inb(0x1F2) | 0x80, 0x1F2); |
|
inb(0x1F5); |
|
inb(0x1F2); |
|
inb(0x3F6); |
|
inb(0x3F6); |
|
inb(0x1F2); |
|
inb(0x1F2); |
|
|
|
if ((inb(0x1F2) & 0x80) == 0) { |
|
/* PDC20230c or 20630 ? */ |
|
printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" |
|
" detected.\n"); |
|
udelay(100); |
|
inb(0x1F5); |
|
local_irq_restore(flags); |
|
return PDC20230; |
|
} else { |
|
outb(0x55, 0x1F2); |
|
inb(0x1F2); |
|
inb(0x1F2); |
|
if (inb(0x1F2) == 0x00) |
|
printk(KERN_INFO "PDC20230-B VLB ATA " |
|
"controller detected.\n"); |
|
local_irq_restore(flags); |
|
return BIOS; |
|
} |
|
} |
|
|
|
if (ht6560a & mask) |
|
return HT6560A; |
|
if (ht6560b & mask) |
|
return HT6560B; |
|
if (opti82c611a & mask) |
|
return OPTI611A; |
|
if (opti82c46x & mask) |
|
return OPTI46X; |
|
if (autospeed & mask) |
|
return SNOOP; |
|
return BIOS; |
|
} |
|
|
|
|
|
/** |
|
* legacy_init_one - attach a legacy interface |
|
* @pl: probe record |
|
* |
|
* Register an ISA bus IDE interface. Such interfaces are PIO and we |
|
* assume do not support IRQ sharing. |
|
*/ |
|
|
|
static __init int legacy_init_one(struct legacy_probe *probe) |
|
{ |
|
struct legacy_controller *controller = &controllers[probe->type]; |
|
int pio_modes = controller->pio_mask; |
|
unsigned long io = probe->port; |
|
u32 mask = (1 << probe->slot); |
|
struct ata_port_operations *ops = controller->ops; |
|
struct legacy_data *ld = &legacy_data[probe->slot]; |
|
struct ata_host *host = NULL; |
|
struct ata_port *ap; |
|
struct platform_device *pdev; |
|
struct ata_device *dev; |
|
void __iomem *io_addr, *ctrl_addr; |
|
u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; |
|
int ret; |
|
|
|
iordy |= controller->flags; |
|
|
|
pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); |
|
if (IS_ERR(pdev)) |
|
return PTR_ERR(pdev); |
|
|
|
ret = -EBUSY; |
|
if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || |
|
devm_request_region(&pdev->dev, io + 0x0206, 1, |
|
"pata_legacy") == NULL) |
|
goto fail; |
|
|
|
ret = -ENOMEM; |
|
io_addr = devm_ioport_map(&pdev->dev, io, 8); |
|
ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); |
|
if (!io_addr || !ctrl_addr) |
|
goto fail; |
|
ld->type = probe->type; |
|
if (controller->setup) |
|
if (controller->setup(pdev, probe, ld) < 0) |
|
goto fail; |
|
host = ata_host_alloc(&pdev->dev, 1); |
|
if (!host) |
|
goto fail; |
|
ap = host->ports[0]; |
|
|
|
ap->ops = ops; |
|
ap->pio_mask = pio_modes; |
|
ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; |
|
ap->pflags |= controller->pflags; |
|
ap->ioaddr.cmd_addr = io_addr; |
|
ap->ioaddr.altstatus_addr = ctrl_addr; |
|
ap->ioaddr.ctl_addr = ctrl_addr; |
|
ata_sff_std_ports(&ap->ioaddr); |
|
ap->host->private_data = ld; |
|
|
|
ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); |
|
|
|
ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, |
|
&legacy_sht); |
|
if (ret) |
|
goto fail; |
|
async_synchronize_full(); |
|
ld->platform_dev = pdev; |
|
|
|
/* Nothing found means we drop the port as its probably not there */ |
|
|
|
ret = -ENODEV; |
|
ata_for_each_dev(dev, &ap->link, ALL) { |
|
if (!ata_dev_absent(dev)) { |
|
legacy_host[probe->slot] = host; |
|
ld->platform_dev = pdev; |
|
return 0; |
|
} |
|
} |
|
ata_host_detach(host); |
|
fail: |
|
platform_device_unregister(pdev); |
|
return ret; |
|
} |
|
|
|
/** |
|
* legacy_check_special_cases - ATA special cases |
|
* @p: PCI device to check |
|
* @master: set this if we find an ATA master |
|
* @master: set this if we find an ATA secondary |
|
* |
|
* A small number of vendors implemented early PCI ATA interfaces |
|
* on bridge logic without the ATA interface being PCI visible. |
|
* Where we have a matching PCI driver we must skip the relevant |
|
* device here. If we don't know about it then the legacy driver |
|
* is the right driver anyway. |
|
*/ |
|
|
|
static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, |
|
int *secondary) |
|
{ |
|
/* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ |
|
if (p->vendor == 0x1078 && p->device == 0x0000) { |
|
*primary = *secondary = 1; |
|
return; |
|
} |
|
/* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ |
|
if (p->vendor == 0x1078 && p->device == 0x0002) { |
|
*primary = *secondary = 1; |
|
return; |
|
} |
|
/* Intel MPIIX - PIO ATA on non PCI side of bridge */ |
|
if (p->vendor == 0x8086 && p->device == 0x1234) { |
|
u16 r; |
|
pci_read_config_word(p, 0x6C, &r); |
|
if (r & 0x8000) { |
|
/* ATA port enabled */ |
|
if (r & 0x4000) |
|
*secondary = 1; |
|
else |
|
*primary = 1; |
|
} |
|
return; |
|
} |
|
} |
|
|
|
static __init void probe_opti_vlb(void) |
|
{ |
|
/* If an OPTI 82C46X is present find out where the channels are */ |
|
static const char *optis[4] = { |
|
"3/463MV", "5MV", |
|
"5MVA", "5MVB" |
|
}; |
|
u8 chans = 1; |
|
u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; |
|
|
|
opti82c46x = 3; /* Assume master and slave first */ |
|
printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", |
|
optis[ctrl]); |
|
if (ctrl == 3) |
|
chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; |
|
ctrl = opti_syscfg(0xAC); |
|
/* Check enabled and this port is the 465MV port. On the |
|
MVB we may have two channels */ |
|
if (ctrl & 8) { |
|
if (chans == 2) { |
|
legacy_probe_add(0x1F0, 14, OPTI46X, 0); |
|
legacy_probe_add(0x170, 15, OPTI46X, 0); |
|
} |
|
if (ctrl & 4) |
|
legacy_probe_add(0x170, 15, OPTI46X, 0); |
|
else |
|
legacy_probe_add(0x1F0, 14, OPTI46X, 0); |
|
} else |
|
legacy_probe_add(0x1F0, 14, OPTI46X, 0); |
|
} |
|
|
|
static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) |
|
{ |
|
static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; |
|
/* Check card type */ |
|
if ((r & 0xF0) == 0xC0) { |
|
/* QD6500: single channel */ |
|
if (r & 8) |
|
/* Disabled ? */ |
|
return; |
|
legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), |
|
QDI6500, port); |
|
} |
|
if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { |
|
/* QD6580: dual channel */ |
|
if (!request_region(port + 2 , 2, "pata_qdi")) { |
|
release_region(port, 2); |
|
return; |
|
} |
|
res = inb(port + 3); |
|
/* Single channel mode ? */ |
|
if (res & 1) |
|
legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), |
|
QDI6580, port); |
|
else { /* Dual channel mode */ |
|
legacy_probe_add(0x1F0, 14, QDI6580DP, port); |
|
/* port + 0x02, r & 0x04 */ |
|
legacy_probe_add(0x170, 15, QDI6580DP, port + 2); |
|
} |
|
release_region(port + 2, 2); |
|
} |
|
} |
|
|
|
static __init void probe_qdi_vlb(void) |
|
{ |
|
unsigned long flags; |
|
static const unsigned long qd_port[2] = { 0x30, 0xB0 }; |
|
int i; |
|
|
|
/* |
|
* Check each possible QD65xx base address |
|
*/ |
|
|
|
for (i = 0; i < 2; i++) { |
|
unsigned long port = qd_port[i]; |
|
u8 r, res; |
|
|
|
|
|
if (request_region(port, 2, "pata_qdi")) { |
|
/* Check for a card */ |
|
local_irq_save(flags); |
|
/* I have no h/w that needs this delay but it |
|
is present in the historic code */ |
|
r = inb(port); |
|
udelay(1); |
|
outb(0x19, port); |
|
udelay(1); |
|
res = inb(port); |
|
udelay(1); |
|
outb(r, port); |
|
udelay(1); |
|
local_irq_restore(flags); |
|
|
|
/* Fail */ |
|
if (res == 0x19) { |
|
release_region(port, 2); |
|
continue; |
|
} |
|
/* Passes the presence test */ |
|
r = inb(port + 1); |
|
udelay(1); |
|
/* Check port agrees with port set */ |
|
if ((r & 2) >> 1 == i) |
|
qdi65_identify_port(r, res, port); |
|
release_region(port, 2); |
|
} |
|
} |
|
} |
|
|
|
/** |
|
* legacy_init - attach legacy interfaces |
|
* |
|
* Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. |
|
* Right now we do not scan the ide0 and ide1 address but should do so |
|
* for non PCI systems or systems with no PCI IDE legacy mode devices. |
|
* If you fix that note there are special cases to consider like VLB |
|
* drivers and CS5510/20. |
|
*/ |
|
|
|
static __init int legacy_init(void) |
|
{ |
|
int i; |
|
int ct = 0; |
|
int primary = 0; |
|
int secondary = 0; |
|
int pci_present = 0; |
|
struct legacy_probe *pl = &probe_list[0]; |
|
int slot = 0; |
|
|
|
struct pci_dev *p = NULL; |
|
|
|
for_each_pci_dev(p) { |
|
int r; |
|
/* Check for any overlap of the system ATA mappings. Native |
|
mode controllers stuck on these addresses or some devices |
|
in 'raid' mode won't be found by the storage class test */ |
|
for (r = 0; r < 6; r++) { |
|
if (pci_resource_start(p, r) == 0x1f0) |
|
primary = 1; |
|
if (pci_resource_start(p, r) == 0x170) |
|
secondary = 1; |
|
} |
|
/* Check for special cases */ |
|
legacy_check_special_cases(p, &primary, &secondary); |
|
|
|
/* If PCI bus is present then don't probe for tertiary |
|
legacy ports */ |
|
pci_present = 1; |
|
} |
|
|
|
if (winbond == 1) |
|
winbond = 0x130; /* Default port, alt is 1B0 */ |
|
|
|
if (primary == 0 || all) |
|
legacy_probe_add(0x1F0, 14, UNKNOWN, 0); |
|
if (secondary == 0 || all) |
|
legacy_probe_add(0x170, 15, UNKNOWN, 0); |
|
|
|
if (probe_all || !pci_present) { |
|
/* ISA/VLB extra ports */ |
|
legacy_probe_add(0x1E8, 11, UNKNOWN, 0); |
|
legacy_probe_add(0x168, 10, UNKNOWN, 0); |
|
legacy_probe_add(0x1E0, 8, UNKNOWN, 0); |
|
legacy_probe_add(0x160, 12, UNKNOWN, 0); |
|
} |
|
|
|
if (opti82c46x) |
|
probe_opti_vlb(); |
|
if (qdi) |
|
probe_qdi_vlb(); |
|
|
|
for (i = 0; i < NR_HOST; i++, pl++) { |
|
if (pl->port == 0) |
|
continue; |
|
if (pl->type == UNKNOWN) |
|
pl->type = probe_chip_type(pl); |
|
pl->slot = slot++; |
|
if (legacy_init_one(pl) == 0) |
|
ct++; |
|
} |
|
if (ct != 0) |
|
return 0; |
|
return -ENODEV; |
|
} |
|
|
|
static __exit void legacy_exit(void) |
|
{ |
|
int i; |
|
|
|
for (i = 0; i < nr_legacy_host; i++) { |
|
struct legacy_data *ld = &legacy_data[i]; |
|
ata_host_detach(legacy_host[i]); |
|
platform_device_unregister(ld->platform_dev); |
|
} |
|
} |
|
|
|
MODULE_AUTHOR("Alan Cox"); |
|
MODULE_DESCRIPTION("low-level driver for legacy ATA"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_VERSION(DRV_VERSION); |
|
MODULE_ALIAS("pata_qdi"); |
|
MODULE_ALIAS("pata_winbond"); |
|
|
|
module_param(probe_all, int, 0); |
|
module_param(autospeed, int, 0); |
|
module_param(ht6560a, int, 0); |
|
module_param(ht6560b, int, 0); |
|
module_param(opti82c611a, int, 0); |
|
module_param(opti82c46x, int, 0); |
|
module_param(qdi, int, 0); |
|
module_param(winbond, int, 0); |
|
module_param(pio_mask, int, 0); |
|
module_param(iordy_mask, int, 0); |
|
|
|
module_init(legacy_init); |
|
module_exit(legacy_exit);
|
|
|