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107 lines
2.5 KiB
107 lines
2.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* clear_page.S: UltraSparc optimized clear page. |
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* |
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* Copyright (C) 1996, 1998, 1999, 2000, 2004 David S. Miller (davem@redhat.com) |
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* Copyright (C) 1997 Jakub Jelinek (jakub@redhat.com) |
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*/ |
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#include <linux/pgtable.h> |
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#include <asm/visasm.h> |
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#include <asm/thread_info.h> |
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#include <asm/page.h> |
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#include <asm/spitfire.h> |
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#include <asm/head.h> |
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#include <asm/export.h> |
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/* What we used to do was lock a TLB entry into a specific |
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* TLB slot, clear the page with interrupts disabled, then |
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* restore the original TLB entry. This was great for |
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* disturbing the TLB as little as possible, but it meant |
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* we had to keep interrupts disabled for a long time. |
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* |
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* Now, we simply use the normal TLB loading mechanism, |
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* and this makes the cpu choose a slot all by itself. |
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* Then we do a normal TLB flush on exit. We need only |
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* disable preemption during the clear. |
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*/ |
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.text |
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.globl _clear_page |
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EXPORT_SYMBOL(_clear_page) |
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_clear_page: /* %o0=dest */ |
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ba,pt %xcc, clear_page_common |
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clr %o4 |
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/* This thing is pretty important, it shows up |
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* on the profiles via do_anonymous_page(). |
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*/ |
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.align 32 |
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.globl clear_user_page |
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EXPORT_SYMBOL(clear_user_page) |
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clear_user_page: /* %o0=dest, %o1=vaddr */ |
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lduw [%g6 + TI_PRE_COUNT], %o2 |
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sethi %hi(PAGE_OFFSET), %g2 |
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sethi %hi(PAGE_SIZE), %o4 |
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ldx [%g2 + %lo(PAGE_OFFSET)], %g2 |
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sethi %hi(PAGE_KERNEL_LOCKED), %g3 |
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ldx [%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3 |
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sub %o0, %g2, %g1 ! paddr |
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and %o1, %o4, %o0 ! vaddr D-cache alias bit |
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or %g1, %g3, %g1 ! TTE data |
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sethi %hi(TLBTEMP_BASE), %o3 |
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add %o2, 1, %o4 |
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add %o0, %o3, %o0 ! TTE vaddr |
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/* Disable preemption. */ |
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mov TLB_TAG_ACCESS, %g3 |
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stw %o4, [%g6 + TI_PRE_COUNT] |
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/* Load TLB entry. */ |
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rdpr %pstate, %o4 |
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wrpr %o4, PSTATE_IE, %pstate |
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stxa %o0, [%g3] ASI_DMMU |
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stxa %g1, [%g0] ASI_DTLB_DATA_IN |
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sethi %hi(KERNBASE), %g1 |
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flush %g1 |
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wrpr %o4, 0x0, %pstate |
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mov 1, %o4 |
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clear_page_common: |
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VISEntryHalf |
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membar #StoreLoad | #StoreStore | #LoadStore |
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fzero %f0 |
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sethi %hi(PAGE_SIZE/64), %o1 |
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mov %o0, %g1 ! remember vaddr for tlbflush |
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fzero %f2 |
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or %o1, %lo(PAGE_SIZE/64), %o1 |
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faddd %f0, %f2, %f4 |
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fmuld %f0, %f2, %f6 |
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faddd %f0, %f2, %f8 |
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fmuld %f0, %f2, %f10 |
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faddd %f0, %f2, %f12 |
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fmuld %f0, %f2, %f14 |
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1: stda %f0, [%o0 + %g0] ASI_BLK_P |
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subcc %o1, 1, %o1 |
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bne,pt %icc, 1b |
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add %o0, 0x40, %o0 |
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membar #Sync |
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VISExitHalf |
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brz,pn %o4, out |
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nop |
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stxa %g0, [%g1] ASI_DMMU_DEMAP |
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membar #Sync |
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stw %o2, [%g6 + TI_PRE_COUNT] |
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out: retl |
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nop |
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